Challenges and Emerging Solutions in Testing TSV-Based 3D Stacked ICs:

Test Flows, Test Contents, and Test Access Erik Jan Marinissen IMEC – Leuven, Belgium

© IMEC 2011 / CONFIDENTIAL

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Erik Jan Marinissen

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6. Conclusion

Summary 3D Test Flows • A lot of potential test moments: pre-, mid-, and post-bond testing • Test cost modeling required to determine optimal test flow 3D Test Contents • Stay alert for new intra-die defects not covered by existing test sets • TSV-based interconnect testing assumes controllability/observability 3D Test Access • Wafer Probing: external test access − Pre-bond: fine-pitch micro-bump probing and/or extra probe pads − Mid-/post-bond: non-planar topologies • DfT Architecture: internal test access − 3D-DfT Architecture defined − Part of commercial EDA tool flows, considered for standardization  IMEC/2011 | Erik Jan Marinissen | Challenges for 3D ICs and Systems – Toulouse, France – November 28+29, 2011

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6. Conclusion

References 1.

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Erik Jan Marinissen and Yervant Zorian, 'Testing 3D Chips Containing Through-Silicon Vias’, IEEE International Test Conference (ITC'09), Austin, Texas, USA, November 2009, Paper ET1.1 (http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5355573) Erik Jan Marinissen, 'Testing TSV-Based Three-Dimensional Stacked ICs’, Design, Automation, and Testing in Europe (DATE'10), Dresden, Germany, March 2010, pp. 1689-1694 (http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5457087) Erik Jan Marinissen, Jouke Verbree, and Mario Konijnenburg, 'A Structured and Scalable Test Access Architecture for TSV-Based 3D Stacked ICs’, IEEE VLSI Test Symposium (VTS'10), Santa Cruz, California, USA, April 2010, pp. 269-274 (http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5469556) Brandon Noia et al., 'Test Architecture Optimization for TSV-Based 3D Stacked ICs’, IEEE European Test Symposium (ETS'10), Prague, Czech Republic, May 2010, pp. 24-29 (http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5512787) Jouke Verbree et al., 'On the Cost-Effectiveness of Matching Repositories of Pre-Tested Wafers for Wafer-to-Wafer 3D Chip Stacking’, IEEE European Test Symposium (ETS'10), Prague, Czech Republic, May 2010, pp. 36-41 (http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5512785) Erik Jan Marinissen et al., ‘3D DfT Architecture for Pre-Bond and Post-Bond Testing’, IEEE Intnl. 3D Systems Integration Conference (3DIC’10), Munich, Germany, November 2010, Paper 3B.1 (http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5751450) Mottaqiallah Taouil et al., 'Test Cost Analysis for 3D Die-to-Wafer Stacking’, IEEE Asian Test Symposium (ATS'10), Shanghai, China, December 2010, pp. 435-441 (http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5692285) Erik Jan Marinissen, 'Challenges in Testing TSV-Based 3D Stacked ICs: Test Flows, Test Contents, and Test Access’, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS'10), Kuala Lumpur, Malaysia, December 2010, pp. 544-547 (http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5775087) Chun-Chuan Chi et al., ‘DfT Architecture for 3D-SICs with Multiple Towers’, IEEE European Test Symposium (ETS’11), Trondheim, Norway, May 2011, pp. 51-56 (http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5957922) Erik Jan Marinissen et al., 'Automated Design-for-Test for 2.5D and 3D SICs’, Chip Scale Review, September-October 2011, pp. 18-22 (http://www.chipscalereview.com/issues/0911/) Ken Smith et al., ‘Evaluation of TSV and Micro-Bump Probing for Wide I/O Testing’, IEEE International Test Conference (ITC’11), Anaheim, California, September 2011, Paper 17.2 Chun-Chuan Chi et al., ‘Post-Bond Testing of 2.5D-SICs and 3D-SICs Containing a Passive Silicon Interposer Base’, IEEE International Test Conference (ITC’11), Anaheim, California, September 2011, Paper 17.3 Sergej Deutsch et al., ‘Automation of 3D-DfT Insertion’, IEEE Asian Test Symposium (ATS’11), New Delhi, India, November 2011  IMEC/2011 | Erik Jan Marinissen | Challenges for 3D ICs and Systems – Toulouse, France – November 28+29, 2011

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6. Conclusion

Acknowledgements •

IMEC (Leuven, Eindhoven2) 3D Team + AMSIMEC + Mario Konijnenburg2

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Cadence Design Systems (Austin1, Endicott2, München3, Noida4) Vivek Chickermane2, Sergej Deutsch3, Marc Greenberg1, Brion Keller2, Subhasish Mukherjee4, Rick Schoonover2 Cascade MicroTech (Beaverton1, Dresden2) Peter Hanaway1, Stojan Kanev2, Jörg Kiesewetter2, Axel Schmidt2, Ken Smith1, Eric Strid1, Thomas Thärigen2 TEL Test Systems (Austin1, Grenoble2, Kildare3, Nirasaki4) Paul Mooney3, Eric Pradel2, Dan Rishavy1, Don Robinson1, Yoichi Shimizu4

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• •

TSMC (San Jose) Sandeep K. Goel

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Duke University (Durham) Krishnendu Chakrabarty, Brandon Noia

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National Tsing-Hua University (HsinChu) Po-Yuan Chen, Chun-Chuan Chi, Cheng-Wen Wu

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TU Delft (Delft) Said Hamdioui, Mottaqiallah Taouil, Jouke Verbree  IMEC/2011 | Erik Jan Marinissen | Challenges for 3D ICs and Systems – Toulouse, France – November 28+29, 2011

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6. Conclusion

Related Events • 3DIC IEEE Intnl. 3D System Integration Conference http://www.3dic-conf.jp/

– Rotating between California, Germany, and Japan – Next edition: January 31-February 2, 2012 – Osaka, Japan • 3D Integration Workshop Applications, Technology, Architecture, Design, Automation, and Test http://www.date-conference.com/conference/workshop-w5

– Co-located with DATE’09, DATE’10, and DATE’11 – Next edition: March 16, 2012 – Dresden, Germany (with DATE’12) • 3D-TEST IEEE Intnl. Workshop on Testing Three-Dimensional Stacked ICs http://3dtest.tttc-events.org/

– Co-located with ITC’10 and ITC’11 – Next edition: November 8+9, 2012 – Anaheim CA (with ITC’12)  IMEC/2011 | Erik Jan Marinissen | Challenges for 3D ICs and Systems – Toulouse, France – November 28+29, 2011

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