RELIABILITY
1
Reliability challenges of 3D stacked IC’s
Kristof Croes and Ingrid De Wolf Imec
Purpose • Overview of key reliability issues related to 3D-processing – TSV-integration – Wafer thinning – Stacking
• Review of key achievements in the imec’s 3D reliability research
Outline
• Introduction • Reliability issues and recent achievements • Summary
Introduction – 3D-Reliability Challenges TSV
TSV and its environment
Stacking
Backside Processing
TSV-reliability Problem
Copper Diffusion?
How to address?
Copper pumping
Suppress by post-plating anneals
TSV-stress causes stress in Si which changes device performance
Transistor performance in TSVproximity m-raman XRD (Synchrotron) Bowing
Thermal stability of TSV
To be studied as a function of thermal storage and thermal cycling
Barrier/liner integrity Scalloping makes standard TDDB difficult!
Methods to be developed!
Cu pumping – Problem statement • CTE Cu (16.7 ppm/oC) >> CTE Si (2.3 ppm/oC) è At high T, Cu expands more than Si • For TSV-middle approach, TSV sees high temperatures during BEOL integration Irreversible Cu expansion
Bowed BEOL
I. De Wolf, et al., ESREF2011
Cu pumping – Proposed solution
TSV etch
Liner + Barrier + Cu fill
Cu CMP
BEOL (@ 420oC)
Anneal
A pre-CMP anneal to stabilize the Cu.
• Question: Time and temperature effect of pre-CMP anneal I. De Wolf, et al., ESREF2011
Sample & test method pre-CMP anneal
CMP
at different T and times
Cu pumping: Dh = h1-h0
I. De Wolf, et al., ESREF2011
Cap (h0)
Sinter (h1)
to mimic the BEOL layer
at 420oC/20 min to mimic the BEOL process T
Measurement method Atomic force microscopy (AFM): – Good results but time consuming
Contact probe (HRP) scan: – Time consuming and noisy
White light interferometry (WLI): – Fast but wrong results with SiO2 Ta-cap needed
I. De Wolf, et al., ESREF2011
Results Temperature effect (Pre-CMP Time = 20min.)
300
1000
100
200
100
10
Chem. A-22um depth Chem. B-40um depth
D afte ) (m rSin
D afte ) (m rSin
Time effect (Different Pre-CMP Temp.)
Chem. C-40um depth
0 250
300
350
Pre-CMP Temp. (°C)
400
450
Chem. A-22um depth-300°C Chem. A-22um depth-350°C Chem. C-40um depth-420°C
1 1
10
100
Pre-CMP Time (min.)
– Conclusion • Increase of pre-CMP temperature and time reduces copper pumping after sinter • High pre-CMP anneal temperatures or long times are needed to suppress Cu pumping during sinter I. De Wolf, et al., ESREF2011
1000
Introduction – 3D-Reliability Challenges TSV
TSV and its environment
Stacking
Backside Processing
TSV and its environment Problem
How to address?
?
?
Copper Diffusion?
BEOL Cu reliability challenged SIV
Proper test methods to be developed
BEOL dielectric reliability challenged
Proper test methods to be developed
FEOL yield and reliability challenged due to copper presence
Asses FEOL yield and reliability in presence of TSV’s
Changes in TSVEvaluate keep-out-zones after thermal stress over time storage and thermal cycling affect keep-out-zone
Impact of TSV proximity on FEOL – Motivation • Influence of TSV presence and proximity on transistor reliability?
– Proposed tests • Gate oxide TDDB with an without presence of TSV
Functionality test – TSV presence and proximity 10
1.0
• No, 1mm away, 1.5mm away
D10, with TSV 0.8 A, no B, 1um F, 1.5um 0.6
4
10
2 -4
D10, with TSV A, no B, 1um F, 1.5um
4
0.4
10
2 -5
Gatecurn(A)
cdfF
TDDB
-3
0.2
4
0.0 -12
10
2
4 68
-11
2
4 68
-10
10 10 Gate current at 1V (A)
2
4 68
10
10 -9
By courtesy of Th. Kauerauf
2 -6
0.1
1
10 Time (s)
100
Introduction – 3D-Reliability Challenges TSV
TSV and its environment
Stacking
Backside Processing
Backside processing Problem Effect of thinning on FEOL performance
How to address? Quantify FEOL performance before and after wafer thinning
High copper volume in TSV contains stress that can Investigate released copper nail after cause reliability thermal cycling issues after TSVrelease Depending on the process, the backside of the wafer can be contaminated by copper after TSVrelease (thinning)
Develop methods to sense backside copper contamination (metrology, C-t, impact on FEOL, etc.)
Released copper nail after thermal cycling – Motivation • Stresses in Cu TSV could cause damage to the liner and backside passivation
– Test approach • Thermal cycling of released copper nails • 100 cycles between -65 and 150° C(10’/10’) performed
– Result • No damage observed
Copper TSV Liner/barrier BS Pass.
Introduction – 3D-Reliability Challenges TSV
TSV and its environment
Stacking
Backside Processing
Stacking Problem
How to address?
Relatively, smaller mbumps have more IMC-formation. IMC’s are more brittle then Cu and solder
Methods to be developed to study mechanical properties of IMC’s
Mechanical stress on mbumps varies significantly during thermal stress
Thermal cycling
mbumps need to carry high currents
Electromigration tests
Micro-bump solder joint = Flip-Chip interconnect scaling BUT: the intermetallic compounds (IMC) formed by UBM solder interaction become of increasing importance with smaller bumps Only intermetallic compounds (IMC) after solder bump reflow
IMC
F = 100µm pad diameter
150-200µm bump pitch PhD Thesis Riet Labie
F = 40µm Pitch 60µm
F = 20µm
F = 10µm
Pitch 40µm
Pitch 20µm
Sample description Flip Chip bump configurations SAC (Sn-Ag-Cu) bump
Cu redistribution layer
Cu pillar bump Cu redistribution layer Plating seed
Ni UBM
IMC Cu pillar IMC IMC Cu – package metal finish
R. Labie, et al., IRPS2011
IMC Cu – package metal finish
Electromigration experiments SAC (Sn-Ag-Cu) bump
Cu pillar bump
Bump resistance [W]
0,01 0 0 0 0 0 0
Time [h]
200
400
600
800
1000
1200
Time [h]
Large discrepancy when comparing different bump configurations:
Although initial bump resistance values are similar, a different behavior is monitored when testing time and EM damage proceeds R. Labie, et al., IRPS2011
Failure analysis – Cu pillar Experiment @ 170oC and 0.3A
EM stressed bump
Thermal reference bump
Cu pillar
Ag3Sn
Cu3Sn Cu6Sn5 Cu3Sn
Ag3Sn Cu3Sn Cu6Sn5 Cu3Sn
Cu – package metal finish
No difference in terms of micro-structural evolution Full IMC transformation of ‘thin’ Sn – Ag cap, no remaining solder left
R. Labie, et al., IRPS2011
Failure analysis – Cu pillar Experiment @ 100oC and 1A
EM damage is not observed but a difference in diffusion flux may occur Experiment is stopped before full IMC transformation occurred EM stressed bump Thermal reference bump
Asymmetry observed for EM stressed interconnection
R. Labie, et al., IRPS2011
Electromigration experiments Failure analysis
Experiment @ 170oC and 0.5A for Ni-SAC interface
EM stressed
Thermal reference
e- 500mA
Less IMC formation at cathodic Ni interface • Void formation at Ni-solder interface •
Imbalanced Ni – Sn flux
à
R. Labie, et al., IRPS2011
Conclusions • Key reliability issues related to 3Dprocessing were introduced • Key achievements – Copper pumping • Method allowing easy quantification developed • Suppressing can only be done with high and/or long pre-CMP anneals
– Initial results show FEOL yield and reliability no severly affected by TSV-presence – TSV remains reliable after release – Relatively more IMC’s do not lead to faster EM
Acknowledgment for their nice contribution to the 3D-reliability work package in imec! – – – – – – – – – – – – – – – – – – – – –
Anna Branka Alicja Lesniewska Bart Vandevelde Biljana Dimcic Chris Wilson Dimitrios Velenis Eric Beyne Gerald Beyer Ingrid De Wolf Ivan Ciofi Joke De Messemaeker Kris Vanstreels Michele Stucchi Myriam Van De Peer Olalla Varela Pedreira Piotr Czarnecki Riet Labie Thomas Kauerauf Veerle Simons Vladimir Cherman Yunlong Li
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Integration Anne Jourdain Augusto Redolfi Kenneth Rebibis Wenqi Zhang Yann Civale
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Assignees - Cristina Torregiani, Qualcomm - Dong Chan Lim, Samsung - George Vakanas, Intel - Hiroki Miyajima, Panasonic - Kenji Takenouchi, Sony - Seungduk Baek, Samsung - Stefano Guerrieri, Micron - Shih-Peng Tai, TSMC - Tatsuya Kabe, Panasonic - Yu-Hsiang Hu, TSMC (Alphabetic order) - Yuichi Miyamori, Sony
