LINEAR INTEGRATED CIRCUIT PREAMPLIFIER WITH ALC FOR CASSETTE RECORDERS • EXCELLENT VERSATILITY in USE (V s from 4 to 20V) • HIGH OPEN LOOP GAIN • LOW DISTORTION • LOW NOISE • LARGE AUTOMATIC LEVEL CONTROL RANGE • GOOD SUPPLY RIPPLE REJECTION • STEREO MATCHING BETTER THAN 3 dB The TDA 1054M is a monolithic integrated circuit in a 16-lead dual in-line plastic package. The functiens incorporated are: -- Low noise preamplifier - Automatic level control system (ALC) - High gain equalization amplifier - Supply voltage rejection facility (SVRF). It is intended as preamplifier in cassette tape recorders and players, dictaphones, compressor and ex· pander in industrial equipments, Hi-Fi preamplifiers and in wire diffusion receivers; for stereo applications the ALC matching is better than 3 dB.

ABSOLUTE MAXIMUM RATINGS Vs P tot Tstg,"J;j

Supply voltage Total power dissipation at Tamb .;;; 50°C Storage and junction temperature

ORDERING NUMBERS:

TDA 1054M mono applications 2 TDA 1054M stereo applications

MECHANICAL DATA

6/82

20 V 500 mW -40 to 150°C

Dimensions in mm

442

CONNECTION AND SCHEMATIC DIAGRAMS (top view)

16 ALe REC~~~

Ale OUTPUT

~~~~iO SUPPLY 2 1..1:

COLLECTOR

ALe INPUT

J

SUPPLY

Q2 BASE

"

VOLTAGE

Ql BASE

\3

OUTPUT

01 EMITTER

12 ccJ~~c;~ET~~ 11 NON INV~:r~~

02 EMITTER Q2 COLLECTOR

07

7

10

o.

INVERTING INPUT

GROUNO

12

01

Q2

SVRF

\3

EQUALIZATION AMPLIFIER

16

A LC

TEST CIRCUIT

~-------------------------------{)+Vs

~

1

150pF

0.47t.JF

4.7 k!l 0.47

B~

Bo

A

52 2.2I'F 6V

47}JF

6V

443

THERMAL DATA Rth

j-amb

Thermal resistance junction-ambient

max

200

°C/W

Max_

Unit

ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Tamb

=

25°C)

Parameter

Min_

Test conditions

Vs

Supply voltage

Id

Quiescent drain current

RL~ = Vs ~ 9V S1 ~S2~S3~ B

hFE

DC current gain

Ic~0.1mA

eN

Input noise voltage (Q1)

4

Ic f iN

Input noise current (Q11

NF

Noise figure (Q11

~ ~

VCE ~ 5V

V CE

0.1 mA 1 kHz

~

300

20

rnA

500

-

2

JHz

nV

5V

V CE ~ 5 V Ic~0.1mA Rg ~ 4.7 k!"l B (-3 dBI ~ 20 to 10,000 Hz

Open loop voltage gain (for equalization amplifier!

Vs

~

9V

Va

Output voltage with A.L.C.

Vs f

~

9V 1 kHz S1

~

f

~

~

1 kHz

Vi ~ 100mV S2 ~ S3 ~ A

(for SVR F systeml

V

6

..E6...

0.5

Gv

R1

Typ_

0.5

y'Hz

4

dB

60

dB

1.1

V

7.5

k!"l

see schematic diagram

R2

(for SVR F systeml

eN

Input noise voltage (for equalization amplifier pin 111

Vs

~

9V 40 dB

V OR

Drop-out (between pins 14 and 21

Vs

~

9V

Rg ~ 4.7 k!"l S1 ~ B Gv~ B (-3 dBI~ 22 Hz to 22 KHz

444

Id

~

6 mA

120

!"l

1.3

MV

0.8

V

II Fig. 2 - Equivalent input noise current vs. frequency (input transistor 0 1 )

Fig. 1 - Equivalent input spot voltage and noise current vs. bias current (input transistor 0,) 'N

0

'N

If*)

10H

(i): 10'

Fig. 3 - Equivalent input noise voltage vs. frequency (input transistor 0 1 )

tt

10 0

10'

10

10kHz

k-

10

I

10

lun'

I-":

..

100HZJri

1kHz 10kHz

00

10

10'

1~'

..

-. •

10'

50 A

50.IJA

10- 1

10'

1.

IC{J.lA)

0

..

f(Hz)

10'

10

10'

..

,

10'

o • f(Hz}

Fig. 6 - Current gain vs. collector current (input transistor 0 1 )

Fig. 5 - Optimum source resistance and minimum NF vs. bias current (input transistor 0 1 )

Fig. 4 - Noise figure vs. bias current (input transistor 0 1 )

..

lmA

'g •

•g •

(kn)

B(-3dB),,20Hzto lOkH%

G

(k11.):

.~,

10

'\ ilL

,~

'dB

2

10

j

i'..~

I i

500

10

100Hz

f--+

I

1'.."

10'

I" "

..

1-

1kHz 10kHz

II

10'

10

10'

Fig. 8 - Open loop phase response vs. frequency (equalization amplifier)

Fig. 7 - Open loop gain vs. frequency (equalization amplifier) G'rTnm~~rnrTm~~~ill~III~~ (dS)

Htttlttl--titttllf--t+tttIII-++tlfflll-! IIIII--H-ttfflfl

60r+~~~~~~~~·I~IIIIUli~ -60

-120

-180

-240

-300

10'

10'

10'

10'

10'

I (Hz)

10'

445

10'

10'

10'

lev..I.A)

APPLICATION INFORMATION Fig.9 - Application circuit for battery/mains cassette player and recorder

"

~~~~

L-l 6V

* TANTALUM

1.8,uF

R21

2.2

"'

CAPACITORS

Fig. 10 - P.C. board and component layout for the circuit fig. 9 (1:1 scale)

446

'"270n

Typical performance of circuit in fig. 9 (T amb

= 25°C, Vs = 9V) Parameter

Test conditions

Min.

Typ.

Max.

Unit

PLAYBACK

Gy

Voltage gain (open loop)

f

= 20 to 20,000 Hz

110

dB

Gy

Voltage gain (closed loop)

f

= 1 kHz

57

dB

IZjl

Input impedance

f f f

= 100 Hz = 1 kHz = 10 kHz

10 41 43

kn kn kn

IZol

Output impedance

f

= 1 kHz

12

B

Frequency response

d

Distortion

S+N -N-

Output weighted background noise

n

see fig. 12 Vo= lV

f

= 1 kHz

Output background noise ***

35

Z9 = 300 n + 120 mH (DIN 45405)

0.1

%

1.3

mV

1.3

mV

Signal to noise ratio

Vo= 1.3V Z9 = 300 n + 120 mH

60

dB

SVR

Supply voltage ripple rejection at the output

frjPPle = 100 Hz

30

dB

ton **

Switch-on time

Vo= lV

500

ms

Gy

Voltage gain (open loop)

f

= 20 to 20,000 Hz

110

dB

Gy

Voltage gain (closed loop)

f

= 1 kHz

70

dB

B

Frequency response

d*

Distortion without ALC

Va= 1.1V

f

=.1 kHz

0.3

%

d

Distortion with ALe

Vo= 1.1V

f

= 10 kHz

0.4

%

ALe

Automatic level control range (for 3 dB of output voltage variation)

Vj "40mV

f

= 10 kHz

54

dB

Vo

Output voltage before clipping without ALe

f

2.3

V

Vo

Output voltage with ALe

Vj =30mV

1.1

V

RECORDING

see fig. 14

= 1 kHz

447

f

= 10 kHz

Typical performance of circuit in fig. 9 (continued) Parameter t[ **

tset

tree

Test conditions'

Min.

Limiting time Isee fig. 11) LV;~+40dB

---

f

~

ton ** S + N **** -N-

~

LV;

Switch-on time

Vo~

1.1V

Signal to noise ratio with ALe

Vo~

1.1V

-40 dB

f

~

Max.

Unit

75

ms

300

ms

150

s

500

ms

64

dB

1 kHz

Level setting time Isee fig. 11) Recovery time Isee fig. 11)

Typ.

1 kHz

Rg~470n

* Measured with selective voltmeter This value depends on external network When the DIN 45511 norm for frequency response is not mandatory the equalization peak at 10 kHz can be avoided - so halving the output noise Weighted noise measu"ement lOIN 45405)

Fig. 11 - Limiting, level setting, recovery time Vi

'0 -.-

'0

tset

~ ~_\-

~ VO~ tl

=lIMITING

trec=RECOVERY TIME

TIME

tset:: LEVEL SETTING TIME 5_11-12

Fig. 12 - Relative frequency response for the circuit in fig.9 (playback)

Fig. 13 - Distortion vs. fre· quency for the circuit in fig. 9 (playback)

Fig. 14 - Relative frequency response for the circuit in fig.9 (recording) G,r;~TImr>-nTIlmrllll-'~mr-'nnm