LINEAR INTEGRATED CIRCUIT CHANNEL AMPLIFIER The LS 045 is a monolithic integrated circuit intended for use as channel amplifier in FDM and PCM telephone equipment. It features low quiescent power consumption, low distortion, high gain. The LS 045 is available in TO-99 metal case, while the hermetic gold chip (8000 series) is available in SO-8 (8-lead plastic micropackage). This last version is particularly suitable for professional and telecom applications wherever very high MTTF are required.

ABSOLUTE MAXIMUM RATINGS Vs Vjll)

!J.V j Top

Ptot Tstg

TO-99

JLpackage

± 18 V ± 12 V ±30V -25 to 85°C indefinite 520mW 400mW -65 to 150 °C -55 to 150°C

Supply voltage Input voltage Differential input voltage Operating temperature Output short circuit duration (2) Power dissipation at T amb= 70°C Storage temperature

(1) For supply voltages less than ± 12V, input voltage is equal to supply voltage. (2) The short circuit duration is limited by thermal dissipation.

Dimensions in mm

MECHANICAL DATA

6/82

218

CONNECTION DIAGRAMS AND ORDERING NUMBERS (top views)

OFFSET

NUll

INVERTING INPUT

-v, (case)

OB

CCMPENSATION + Vs

2

7

NON INVERTING INPUT

3

6

OUTPUT

-lis

4

5

OFFSET f'.IJlL

,,-258011

Type

TO-99

SO-8

LS 045

LS 045T

LS045M LS 8045M

LS 8045

SCHEMATIC DIAGRAM

~--.-f--+---£ Q 13

R6 2711 R7 6 2211

I

Rl 1k11

j

Rl1

50

kn 5-2053

THERMAL DATA Rth j-amb

TO-99 max

Thermal resistance junction-ambient

155°C/W

• The thermal resistance is measured with the device mounted on a ceramic substrate (25x16xO.6 mm).

219

SO-8 200* °C/W

ELECTRICAL CHARACTERISTICS (Vs= -20V, Vbal = -10V, T amb = 25°C unless otherwise specified. For Vbal see fig. 7) Parameter

Min.

Test conditions

Vos

Input offset voltage

Ib

Input bias current

Ri

Input resistance

Rg= 10kO

Typ.

Max.

Unit

± 1.5

± 10

mV

100

750

nA

2

MO

75

0

105

dB

Open loop Ro

Output resistance

Gv

Open loop voltage gain

RL= 2 kO

f = 10Hz

d

Distortion

f = 1 kHz ZLeq=4700

G v =40dB

83

Po= -5dBm Po= 8 dBm Ptot

Quiescent power dissipation

Po= 0

Po

Maximum output power

d = 1% Gv=40dB

ZLeq=4700

Rg "1.5kO G v =40dB

f = 1 kHz B = 100 Hz

f = 1 kHz

G v =40dB

Pn

SVR

Noise power referred to input

Supply voltage rejection referred to output

14

0.15 0.15

0.3 0.3

% %

20

30

mW

dBm

16

dBm

-120.5 30

dB

36

THE FOLLOWING SPECIFICATION APPLY FOR T amb = -25 to 85°C Vos

Input offset voltage

Rg= 10 kO

Ib

Input bias current

Gv

Open loop voltage gain

R L = 2 kO

r----r-,-,--r,-.,-,--,-,--r=-;=.

P tot

(mW)

H-+-::-y.-'-.-_,=.y++--+-+-t-HH

(mW)

11. 30

--

_20

20

4. ••

,. r.... Tamb("C)

,. V I.

/'

1/

V 30

I. 14

18

22

220

26 -Va (V)

IIII

IIIIIIIII Vs =-20V

1IIIIIIil 1I11111I1 111111111 C'_B,,3pF

/

!O

dB

6-2241

G,

4. I,-

IJA

Fig. 3 - Voltage gain (open loop) vs. frequency (dB )

50

20

1.5

G~2240

Ptot

30

mV

78

Fig.2 -Quiescent power dissipation vs. supply voltage

Fig. 1 - Quiescent power dissipation vs. ambient temG. " ' . , perature

± 15

I

I!I'

I 1

I

Fig. 5 - Distortion vs. output power

Fig. 4 - Maximum output power vs. load resistance

Fig. 6 - Transient response (unity gain) G-221l1l

Po (mW)

52

I

Yo

- -

'''''

Vs=-20V d'5i ,./.

)

I

I

20

I I

""10

f" 1kHz

16 44

1/ "'-

36

28

20

I

12

V..&15V Cc=lOpF AL ",2kn

CL"IOOpF

e-re-

i re-

Tamlb&ZSoC ,

II

/

'---

I' 200

I I I

l"-

I

.5

.10

600

400

IE

Rly TIIME 15

10 Po (dBm)

APPLICATION INFORMATION Fig.7 - Channel amplifier circuit

L2 =20n

Fig. 9 - Return loss Vs. voltage gain

Fig. 8 - Return loss vs. fre· quency G_UU

Vs=-20Y f ,,1kHz:

(-dB )

1

40

l..«

1

rl

v=30~

30

1