Wafer Bonding - eufanet

Wafer Bonding. • Bond process: – Plasma-activation. – Direct bonding (Si/SiO2). – Low temperature anneal. – CSAM. • Bond surfaces. – 1) Polished Si wafer.
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WAFER-BOND MICRO-VOID PHYSICAL ANALYSIS

C. Cassidy1, H. Plank2, T. Ganner2, L.G.W. Tvedt3, C. Gspan2, M. Dienstleder2, J. Wagner2, M. Krause4, C. Patzig4, S. Brand4, B. Böttge4, J. Siegert1

1austriamicrosystems

AG 2FELMI-ZFE (Graz, Austria) 3SINTEF ICT, Microsystems and Nanotechnology (Oslo, Norway) 4Fraunhofer-IWM (Halle, Germany)

Purpose • Share a 3D-integration analysis problem • Highlight real-life practical problems & difficulties • Get feedback & ideas…

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Outline 1. Introduction to bonding & “micro-voids” 2. PFA Successes  3. PFA challenges & problems  4. Summary, current status 5. Workshop question

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Technology overview Solder balls

TSVs

- CMOS processing - Wafer bonding - TSV (unfilled “via last”) - Finish CMOS/bumping

Wafer bond interface

Wachmann et al., ICMAT 2011

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Wafer Bonding • Bond process:

EVG Gemini toolset

– Plasma-activation – Direct bonding (Si/SiO2) – Low temperature anneal – CSAM Pre-bonding

• Bond surfaces – 1) Polished Si wafer – 2) Deposited oxide layer, CMP finish (lower) Post-bonding Kraft et al., ECTC 2011

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What is a “micro-void”? Wafer-level CSAM detects circular features in the bond interface. Specific size distribution (diameter ~100µm) CSAM

Micro-void

TSVs

“upper wafer”

“Micro-void”

TSV

Bond oxide

Wafer-level Scanning acoustic microscopy

“lower” wafer

Bond Interface

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Micro-void questions CSAM

– What is the root cause? – Reliability risk or cosmetic defect?

Fig. A

– Do they move or grow? – Interrupted TSV connection? – Fracture/delam initiation point?

TSVs Fig. B

Fig. C 7

Micro-void physical analysis

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Physical analysis The interface is not easy to access

Bond interface

Accessing the bond interface 9

Sample preparation approach 1. Si Etch removal, oxide underside as etch stop Lower Si removed using wet/dry etch

PRO: Defect is visible and accessible to PFA techniques CON: Defect might be changed by etch/release process

“upper wafer” Bond oxide

Lower wafer selectively etched away

Bond interface

Optical microscopy

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Optical microscopy (after Si etch removal)

CSAM

Delamination/ voids/ bond defects

“upper wafer” Bond oxide

3

Optical microscopy

2

1

11

Optical microscopy; 3 distinct zones can be discerned 11

Cross-section & in situ optical microscopy Defects appear to consist of… - A. outer debonded area - B. sealing ring (bonded/ contaminant) - C. internal debonded area

1.

1. Defect is undisturbed

2.

3.

2. Outer delaminated region is disturbed. Trapped gas escapes, unbonded oxide at the polishing front fractures off, following the contour of the ring 12

3. As 2. Polishing front is now right “in” the ring region, but has not compromised it yet.

A

4.

4. The ring is “opened” by the polishing front, allowing the gas inside to escape.

B

C

5.

5. None of the oxide at the polishing front in the vicinity of the defect is now bonded, and fractures and rips off easily during polishing

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Is there a foreign contaminant? - ToF-SIMS depth profile (F-IWM), through bond interface - No foreign elements/compounds could be detected

Defect 1

Before ToF depth profile

After ToF depth profile 13

Void collapse example (OM)

Pre-collapse

Post-collapse

- Voids collapse after e.g. ultrasonic cleaning, mechanical, pressure, vacuum exposure (SEM/FIB), time… - Complicates PFA attempts 14

What topograpy is associated with the defect? AFM on the oxide surface (ZFE), after collapse

Post-collapse (defocus) 8nm ridge

10nm recess

Ultrasonic agitation to collapse the void

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TEM & analysis (bond oxide still in place) What are the recess and ridge composed of?

Bond oxide

Si substrate

Successful microvoid TEM lamella preparation

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TEM Sample prep Pt

2.8 nm

Thick (5-8nm) oxide layer? 5

Si

n m

Bond oxide

Bond oxide

EFTEM shows Si and O

EFTEM shows Pt EFTEM shows Si and O

5

Si

n m

Reference area

Si 5

n

m

Defect area

Typically 1-2nm native oxide expected. e.g. Suni et al, J. ECS, 2002

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Sample preparation approach 2. (Assisted) Debonding

A

B PRO: Bond interface is exposed for surface analysis CON: Unreliable debonding, possible material transfer, defect navigation, contamination

C 18

White light interferometry (debonded Si surface) WLI (Sintef) identified a slight recess (~-10nm, blue in the image below), with an enclosing raised ring (~+15nm, red in the image below).

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AFM (debonded surfaces, ZFE) Topographical surface analysis on both surfaces… Polished backside Si surface

Polished oxide surface AFM artifact

No significant topography

Problem stems from topography on polished Si surface.

Polished oxide surface is OK!

Summary of useful PFA results • Micro-voids are caused by existing surface topography. • This topography is uniquely associated with the polished Si wafer. • ToF-SIMS indicates that no foreign species are present. • TEM identifies a suspiciously thick oxide layer (5-8nm) in the defect region 21

Pending • Further defect TEMs • Reference, pre-bonding TEMs (surface polishing, cleans, plasma activation) – Characterization of surface, particularly oxidation

• Elemental analysis on debonded defects 22

PFA Problems

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1. Targeting/navigation - Buried, featureless surfaces, disappearing voids

Optical

Laser marks

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2. FIB/SEM problems • Cross-sections: Nothing at the interface – A) Void collapsed? – B) Insufficient resolution/lack of contrast mechanism

Micro-void

Oxide

Deposite d FIB markers

Si

Bond interface

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- Lamella fracture, owing to unbonded/weakly bonded surfaces

Oxide

Fracture at micro-void area

1

Bond interface

µ m

3.TEM problems

Si

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3.TEM problems “reweld”

after 19 seconds (in the electron beam)

2 0

2 0

n m

1

µ m

n m

Bright Field 27

4. ToF-SIMS problems • Spikes (+ve, -ve) in ToF depth profiles • Assumption is instability of defect, opening of void, “explosions” of trapped gas +ve spikes 5

10

4

4

10

10

3

3

10

10

2

10

2

1

10

0

10

10

OHIntensity (counts)

Intensity (counts)

C-

5

10

FSiO2ClSiOBr-

1

10

0

10

200

400

600

800 Time (s)

All counts fall to zero as bond interface is exposed

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Process improvement/reliability assessment

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Strategy 1: Elimination • No progress to date – Physical root cause – Identification of processing step(s) – Process improvement

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Strategy 2: Reliability assessment

(A)

• Accelerated stresses – Micro-voids are stable (A)

• Micro-manipulation

(B)

– Trapped bubbles can’t be “micro-maneuvered” beyond their original boundaries (B)

• Bond strength tests – Micro-void presence has no detectable effect on fracture mode or fracture stress values (C)

(C) 31

Conclusions • Micro-void origin – Micro-voids are caused by nm-scale local topography on the backside of the polished bond surface, perhaps caused by local oxide thickness variations. – The root cause not yet found. – Reliability data: Do not pose a reliability risk

• PFA of wafer-bond interface defects is challenging – – – –

Buried defects, navigation/targeting Instability of defects during FA (trapped bubbles) Aspect ratio (defect, defect to enclosing material) High bond strength

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Thank you for your attention Workshop question…

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Workshop question Until now, we always had to bond the wafers to find the defect in CSAM. How could we find the flaws on the surface prior to bonding? 34

Backup

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What topograpy is associated with the defect? AFM on the oxide surface (ZFE)

Micro-void

40nm air bubble

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AFM (oxide surface)

Pre-collapse

40nm air bubble

Post-collapse (defocus) 8nm ridge

10nm recess 37

Strategies

1. Prove that there is no reliability risk

2. Eliminate microvoids

a) Understand the mechanism b) Gather reliability data c) Convince customers

a) Understand the mechanism b) Process improvement

Both approaches require physical analysis to determine the root cause.

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Probe needle

Exposed oxide: micro-manipulation • Defect oxide cap is very elastic – Voids disappear with gentle pressure – Re-appear when pressure removed

Probe needle

• Collapse – With extensive force and scratching, voids can be permanently collapsed

• Movement – The debonded area/bubble cannot be moved, manipulated or increased beyond its original area

TSV

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4. ToF-SIMS problems • Si etch process (sample prep) shows some nonuniformity and consumption of oxide (A) • Large sputter volume, thin defect layer - 0.9-2.2µm oxide sputter, 15nm defect • Interpretation of depth profiles was difficult (B)

Sputtering direction ILD0 Bond oxide

(A)

(B)

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1. Targeting/navigation • If debonding the surfaces, no surface defect can be seen afterwards. • No navigation guides.

Intact oxide

Oxide etched (HF) Debonded surface, oxide side

Debonded surface, Si side

The defect cannot be seen 41

1. Targeting/navigation • Invisible in electron/ion microscopy. • Laser marking is possible, but often void disappears

Laser marks

Void has disappeared

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5. White light interferometry • Excellent for Si surface • Not possible for transparent BO surface => Large area AFM a better option

WLI: Si surface 43