MOTOROLA
MPC555PB/D Rev. 2, December 2001
SEMICONDUCTOR PRODUCT BRIEF
MPC555 Product Brief
MPC555 Microcontroller Features • MPC555 core with floating-point unit • 26 Kbytes fast RAM and 6 Kbytes TPU microcode RAM • 448 Kbytes flash EEPROM with 5-V programming • 5-V I/O system • Serial system: queued serial multi-channel module (QSMCM), dual CAN 2.0B controller modules (TouCANTM) • 50-channel timer system: dual time processor units (TPU3), modular I/O system (MIOS1) • 32 analog inputs: dual queued analog-to-digital converters (QADC64) • Submicron HCMOS (CDR1) technology • 272-pin plastic ball grid array (PBGA) packaging • 40-MHz operation, -40 °C to 125 °C with dual supply (3.3 V, 5 V) • 32-bit architecture (compliant with the PowerPC architecture, Book 1) • Core performance measured at 52.7-Kbyte Dhrystones (v2.1) @ 40 MHz • Fully static, low power operation • Integrated double-precision floating-point unit • Precise exception model • Extensive system development support — On-chip watchpoints and breakpoints — Program flow tracking — BDM on-chip emulation development interface
This document contains information on a new product. Specifications and information herein are subject to change without notice. © MOTOROLA 2001, All Rights Reserved
256 Kbytes Flash
192 Kbytes Flash
Burst Interface
U-bus E-bus USIU
RCPU
10 Kbytes SRAM
16 Kbytes SRAM
L2U
L-bus
QADC
QADC
QSMCM
UIMB TouCAN
IMB3
TPU3
TPU3
DPTRAM
TouCAN
MIOS1
Figure 1 RISC MCU Central Processing Unit (RCPU) Four-Bank Memory Controller • Works with SRAM, EPROM, flash EEPROM, and other peripherals • Byte write enables • 32-bit address decodes with bit masks U-Bus System Interface Unit (USIU) • Clock synthesizer • Power management • Reset controller • MPC555 decrementer and time base • Real-time clock register • Periodic interrupt timer • Hardware bus monitor and software watchdog timer • Interrupt controller that supports up to eight external and eight internal interrupts • IEEE 1149.1 JTAG test access port • External bus interface — 24 address pins, 32 data pins — Supports multiple master designs — Four-beat transfer bursts, two-clock minimum bus transactions — Supports 5V inputs, provides 3.3-V outputs
MPC555
PRODUCT BRIEF Rev. 2, September 2001
MOTOROLA 2
Flexible Memory Protection Unit • Four instruction regions and four data regions • 4-Kbyte to 16-Mbyte region size support • Default attributes available in one global entry • Attribute support for speculative accesses 448-Kbyte Flash EEPROM Memory • One 256-Kbyte and one 192-Kbyte module • Page read mode • Block (32-Kbyte) erasable • External 4.75-V to 5.25-V program and erase power supply 26-Kbytes of Static RAM • One 16-Kbyte and one 10-Kbyte module • Fast (one-clock) access • Keep-alive power • Soft defect detection (SDD) General-Purpose I/O Support • Address (24) and data (32) pins can be used for general-purpose I/O in single-chip mode • Nine general-purpose I/O pins in MIOS1 unit • Many peripheral pins can be used for general-purpose I/O when not used for primary function • 5-V tolerant inputs/outputs Two Time Processor Units (TPU3) • Each TPU3 module provides these features: — A dedicated micro-engine operates independently of the RCPU — 16 independent programmable channels and pins — Each channel has an event register consisting of a 16-bit capture register, a 16-bit compare register and a 16-bit comparator — Nine pre-programmed timer functions are available — Any channel can perform any time function — Each timer function can be assigned to more than one channel — Two timer count registers with programmable prescalers — Each channel can be synchronized to one or both counters — Selectable channel priority levels — 5-V tolerant inputs/outputs • 6-Kbyte dual port TPU RAM (DPTRAM) is shared by the two TPU3 modules for TPU microcode 18-Channel Modular I/O System (MIOS1) • Ten double action submodules (DASM) • Eight dedicated PWM sub-modules (PWMSM) • Two 16-bit modulus counter submodules (MCSM) • Two parallel port I/O submodules (PIOSM) • 5-V tolerant inputs/outputs Two Queued Analog-to-Digital Converter 2 Modules (QADC64) Each QADC provides: • Up to 16 analog input channels, using internal multiplexing • Up to 41 total input channels, using internal and external multiplexing • 10-bit A/D converter with internal sample/hold • Typical conversion time of 10 µs (100,000 samples per second) • Two conversion command queues of variable length • Automated queue modes initiated by:
MPC555
PRODUCT BRIEF Rev. 2, September 2001
MOTOROLA 3
— External edge trigger/level gate — Software command • 64 result registers • Output data that is right- or left-justified, signed or unsigned • 5-V reference and range Two CAN 2.0B Controller Modules (TouCANTM) Each TouCANTM provides these features: • Full implementation of CAN protocol specification, version 2.0A and 2.0B • Each module has 16 receive/transmit message buffers of 0 to 8 bytes data length • Global mask register for message buffers 0 to 13 • Independent mask registers for message buffers 14 and 15 • Programmable transmit-first scheme: lowest ID or lowest buffer number • 16-bit free-running timer for message time-stamping • Low power sleep mode with programmable wake-up on bus activity • Programmable I/O modes • Maskable interrupts • Independent of the transmission medium (external transceiver is assumed) • Open network architecture • Multimaster concept • High immunity to EMI • Short latency time for high-priority messages • Low power sleep mode with programmable wakeup on bus activity Queued Serial Multi-Channel Module (QSMCM) • Queued serial peripheral interface (QSPI) — Provides full-duplex communication port for peripheral expansion or interprocessor communication — Up to 32 preprogrammed transfers, reducing overhead — 160-byte queue buffer — Programmable transfer length: from 8 to 16 bits, inclusive — Synchronous interface with baud rate of up to system clock divided by 4 — Four programmable peripheral-select pins support up to 16 devices — Wrap-around mode allows continuous sampling for efficient interfacing to serial peripherals (e.g., – serial A/D converters, I/O latches, etc.) • Two serial communications interfaces (SCI). Each SCI offers these features: — UART mode provides NRZ format and half-or full-duplex interface — 16 register receive buffer and 16 register transmit buffer (SCI1 only) — Advanced error detection and optional parity generation and detection — Word length programmable as 8 or 9 bits — Separate transmitter and receiver enable bits and double buffering of data — Wakeup functions allow the CPU to run uninterrupted until either a true idle line is detected or a new address byte is received — External source clock for baud generation — Multiplexing of transmit data pins with discrete outputs and receive data pins with discrete inputs, allowing realization of a low-speed serial protocol
MPC555
PRODUCT BRIEF Rev. 2, September 2001
MOTOROLA 4
0x00 0000 CMF Flash A 256 Kbytes 0x04 0000 0x06 FFFF
CMF Flash B 192 Kbytes
0x07 0000
0x2F C000 USIU Control Registers 1 Kbyte FLASH Module A (64 bytes) 0x2F C800 FLASH Module B (64 b ytes)
Reserved for Flash (2.6 Mbytes -–16 Kbytes)
0x2F C840 0x2F C880
Reserved for USIU 0x2F BFFF 0x 2F C000 0x 2F FFFF 0x30 0000
U SI U & F l ash Control 16 Kbytes IMB3 Address Space UIMB Interface & IMB3 Modules (32 Kbytes)
DPTRAM (6 Kbytes)
Reserved for IMB3 (480 Kbytes)
Reserved (2 Kbytes) 0x30 4000
TPU3_B (1 Kbyte)
0x30 4400
SR A M C on t r ol A ( 8 bytes)
QADC_A (1 Kbyte)
0x30 4800
QADC_B (1 Kbyte)
0x30 4C00
SR A M C on t r ol B ( 8 bytes)
QSMCM (4 Kbytes)
0x30 5000
0x30 6000
0x 38 0010
MIOS1 (4 Kbytes)
Reserved (485.98 Kbytes)
0x 3F C000 0x 3F FFFF
0x30 2000
TPU3_A (1 Kbyte)
0x 37 FFFF 0x 38 0000
0x 3F 9800
0x30 0000
Reserved (8180 bytes)
0x 30 7 FFF 0x 30 8000
0x 38 0008
DPTRAM Control (12 bytes)
TouCAN_A (1 Kbyte)
0x30 7080
TouCAN_B (1 Kbyte)
0x30 7480
SRAM A (10 Kbytes)
Reserved (1920 bytes)
0x30 7884
SRAM B (16 Kbytes)
UIMB Registers (128 bytes)
0x30 7F80 0x30 7FFF
Figure 2 MPC555 Internal Memory Map
MPC555
PRODUCT BRIEF Rev. 2, September 2001
MOTOROLA 5
Figure 3 MPC555 Pinout Data
MPC555
PRODUCT BRIEF Rev. 2, September 2001
MOTOROLA 6 y Dees
2
3
4
B_TPUCH2
G
TMS
WEB_ AT[1]
RD_WRB
OEB
TSIZ0
BURSTB
P
R
T
U
V
Y
BDIPB
VDDL
CS1B
CS0B
VDDI
A_TPUCH5
A_TPUCH9
VSSA
VDDA
VRH
8
9
10
11
12
13
14
15
VDDL
Data_ SGP29 Data_ SGP27 Data_ SGP25 Data_ SGP23
VDDL
Data_ SGP20 RCFB_TXP
VDDI
VDDL
VPP
Addr_ SGP14 Addr_ SGP16 Addr_ SGP18 Addr_ SGP20 Addr_ SGP23 Addr_ SGP26 Data_ SGP1 Data_ SGP3 Data_ SGP5 Data_ SGP7 Data_ SGP9 Data_ SGP11 Data_ SGP13 Data_ SGP15 Data_ SGP17 IRQ5B _SGP
CLKOUT
EXTCLK
KAPWR
VDDF
EPEE
TXD1_ QGPO
PCS0 _QGP
PCS1 _QGP
RXD1_ QGPI
VFLS1 _MPIO4
VFLS0 _MPIO3
VDDL
VF2 _MPIO2
MPIO15
MPIO8
MPWM18
MPWM17
MPWM1
MDA29
MDA15
Note: The pinout is a top down view of the package.
VSS
VSS
VSS
MPIO10
MPIO5
MPWM16
MPWM0
VDDL
MDA27
MDA14
18 MDA12
PCS2 _QGP VSS
VSS
VSS
VSS
VDDI
ETRIG1
ETRIG2
17 MDA11
PCS3 _QGP
VSS
VSS
VSS
VSS
16 VDDH
VSS
VSS
VSS
VSS
VSS
AAN1_PQB1 AAN50_PQB6 AAN55_PQA3 AAN58_PQA6 BAN50_PQB6 BAN55_PQA3 BAN58_PQA6 BAN59_PQA7
AAN2_PQB2 AAN51_PQB7 AAN56_PQA4 AAN59_PQA7 BAN49_PQB5 BAN53_PQA1 BAN56_PQA4 BAN57_PQA5
AAN3_PQB3 AAN49_PQB5 AAN53_PQA1 AAN57_PQA5 BAN1_PQB1 BAN48_PQB4 BAN52_PQA0 BAN54_PQA2
AAN0_PQB0 AAN48_PQB4 AAN52_PQA0 AAN54_PQA2 BAN0_PQB0 BAN2_PQB2 BAN3_PQB3 BAN51_PQB7
Addr_ SGP31 Addr_ SGP30 Addr_ SGP28 Addr_ SGP29
VDDI
A_TPUCH13
7 VRL
Addr_ SGP11 Addr_ SGP10 Addr_ SGP9 Addr_ SGP8 Addr_ SGP22 Addr_ SGP27 Data_ SGP31 Data_ SGP30 Data_ SGP28 Data_ SGP26 Data_ SGP24 Data_ SGP22 Data_ SGP21 Data_ SGP19 Data_ SGP18
TSB
TSIZ1
CS2B
WEB_ AT[3]
BBB _IWP3
SGP_ IRQOUTB
IRQ2B _SGP
BGB_LWP1
6
Ball Map 19
=3 volt power (I/O)
VDDi
=3 volt power (internal)
=ground 21 November 1997
VSS
VDDH
=5 volt power
20
MPIO13
MPIO12
MPIO9
MPIO6
MPWM3
MDA31
MDA28
VDDH
A_CNRX0
VDDH
PORESETB
ECK_ BUCK
VSSSYN
XFC
VSSF
RXD2_ QGPI
ECK
Version 10.2
=Misc power
VDDH
HRESETB
SRESETB
XTAL
EXTAL
VDDSYN
VDDH
TXD2_ QGPO
SCK_ QGP6
MISO _QGP4 MOSI _QGP5
A_CNTX0
VF0 _MPIO0 VF1 _MPIO1
MPIO14
MPIO11
MPIO7
MPWM19
MPWM2
MDA30
VDDH
MDA13
Addr_ SGP13 Addr_ SGP15 Addr_ SGP17 Addr_ SGP19 Addr_ SGP21 Addr_ SGP24 Addr_ SGP25 Data_ SGP0 Data_ SGP2 Data_ SGP4 Data_ SGP6 Data_ SGP8 Data_ SGP10 Data_ SGP12 Data_ SGP14 Data_ SGP16 IRQ6B _mck2 IRQ7B _mck3
VDDH
BIB_STSB
TAB
TEAB
CS3B
WEB_ AT[2]
BRB_IWP2
IRQ1B _SGP
Substrate 9/30/97a
VDDH
VDDH
W Addr_ SGP12
WEB_ AT[0]
N
M IRQ0B _SGP
IRQ4B _SGP
VDDL
VDD SRAM
B_CNTX0
B_TPUCH9
B_TPUCH12
VDDL
IRQ3B _SGP
SGP_FRZ
TRST_B
TDO_ DSDO
TDI_DSDI
B_CNRX0
B_TPUCH4
B_TPUCH8
B_TPUCH0
B_TPUCH3
B_TPUCH6
B_TPUCH10 B_TPUCH14
L IWP1 _VFLS IWP0 _VFLS
K
J TCK_ DSCK
B_TPUCH1
B_TPUCH5
F
H
B_TPUCH7
A_TPUCH2
E
5 A_TPUCH12 A_TPUCH15
A_TPUCH10 A_TPUCH11 A_TPUCH14
A_TPUCH8
D B_TPUCH11 B_TPUCH13 A_TPUCH0
A_TPUCH6
A_TPUCH4
A_TPUCH7
A_T2CLK
VDDH
A_TPUCH1
A_TPUCH3
C B_TPUCH15
B_T2CLK
B
1 VDDH
A
MPC555
Ordering Information Table 1 MPC555 Package Information Device Name
Order Part Number
Package Info
Temp. Range
MPC555
MPC555LFMZP40
272 PBGA
-40 to +125 °C
MPC555
MPC555LFCZP40
272 PBGA
-40 to +85 °C
MPC555
MPC555LFMZP40R2
272 PBGA Shipped in tape and reel media
-40 to +125 °C
MPC555
MPC555LFCZP40R2
272 PBGA Shipped in tape and reel media
-40 to +85 °C
Table 2 lists the documents that provide a complete description of the MPC555 and are required to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola Semiconductor documentation page on the Internet (the source for the latest information). Table 2 Available Documentation Document Number MPC555UM/AD
MPC555
Title MPC555/556 User’s Manual
AN1282/D
Board Strategies for Ensuring Optimum Frequency Synthesizer Performance.
AN1778/D
Using the MIOS on the MPC555 Evaluation Board
AN1821/D
Exception Table Relocation and Multi-Processor Address Mapping in the Embedded MPC5XX Family
AN1837/D
Non-Volatile Memory Technology Overview
AN2001/D
Designing Expansion Boards for the Motorola EVB555/ETAS ES200.
AN2109/D
MPC555 Interrupts.
AN2127/D
EMC Guidelines for MPC500-Based Automotive Powertrain Systems
PRODUCT BRIEF Rev. 2, September 2001
MOTOROLA 7
