E2G0010-17-41
¡ Semiconductor MSM514256C/CL ¡ Semiconductor
This version: Jan. 1998 MSM514256C/CL Previous version: May 1997
262,144-Word ¥ 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
DESCRIPTION The MSM514256C/CL is a 262,144-word ¥ 4-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM514256C/CL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/single-layer metal CMOS process. The MSM514256C/CL is available in a 20-pin plastic DIP, 26/20-pin plastic SOJ, or 20-pin plastic ZIP. The MSM514256CL (the low-power version) is specially designed for lower-power applications.
FEATURES • 262,144-word ¥ 4-bit configuration • Single 5 V power supply, ±10% tolerance • Input : TTL compatible, low input capacitance • Output : TTL compatible, 3-state • Refresh : 512 cycles/8 ms, 512 cycles/64 ms (L-version) • Fast page mode, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • Package options: 20-pin 300 mil plastic DIP (DIP20-P-300-2.54-W1) (Product : MSM514256C/CL-xxRS) 26/20-pin 300 mil plastic SOJ (SOJ26/20-P-300-1.27) (Product : MSM514256C/CL-xxJS) 20-pin 400 mil plastic ZIP (ZIP20-P-400-1.27) (Product : MSM514256C/CL-xxZS) xx indicates speed rank.
PRODUCT FAMILY Family MSM514256C/CL-45
Access Time (Max.) tRAC
tAA
tCAC
tOEA
Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.)
45 ns 24 ns 14 ns 14 ns
90 ns
468 mW
MSM514256C/CL-50
50 ns 26 ns 14 ns 14 ns
100 ns
446 mW
5.5 mW/
MSM514256C/CL-60
60 ns 30 ns 15 ns 15 ns
120 ns
385 mW
1.1 mW (L-version)
MSM514256C/CL-70
70 ns 35 ns 20 ns 20 ns
130 ns
330 mW
1/17
¡ Semiconductor
MSM514256C/CL
PIN CONFIGURATION (TOP VIEW) DQ1 1 DQ2 2 WE 3 RAS 4 NC 5 A0 6 A1 7 A2 8
20 VSS
19 DQ4 18 DQ3 17 CAS 16 OE 15 A8 14 A7 13 A6
A3 9
12 A5
VCC 10
11 A4
OE 1
DQ1 1
26 VSS
DQ2 2
25 DQ4
DQ3 3
WE 3
24 DQ3
VSS 5
RAS 4
23 CAS
DQ2 7
NC 5
22 OE
RAS 9 A0 11
A0 9
18 A8
A2 13
A1 10
17 A7
VCC 15
A2 11
16 A6
A5 17
A3 12
15 A5
A7 19
VCC 13
14 A4
2 CAS 4 DQ4 6 DQ1 8 WE NO LEAD 12 A1 14 A3 16 A4 18 A6 20 A8
20-Pin Plastic ZIP 26/20-Pin Plastic SOJ
20-Pin Plastic DIP
Pin Name A0 - A8
Function Address Input
RAS
Row Address Strobe
CAS
Column Address Strobe
DQ1 - DQ4
Data Input/Data Output
OE
Output Enable
WE
Write Enable
VCC
Power Supply (5 V)
VSS
Ground (0 V)
NC
No Connection
2/17
¡ Semiconductor
MSM514256C/CL
BLOCK DIAGRAM RAS
Timing Generator Timing Generator
CAS
9
Column Address Buffers
9
Write Clock Generator
Column Decoders
WE OE 4
Internal Address Counter
A0 - A8
Refresh Control Clock
Sense Amplifiers
4
I/O Selector
Row Address Buffers
9
Row Decoders
Word Drivers
4
4
4 4
9
Output Buffers Input Buffers
DQ1 - DQ4
4
Memory Cells
VCC On Chip VBB Generator VSS
3/17
¡ Semiconductor
MSM514256C/CL
ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter
Symbol
Rating
Unit
VT
–1.0 to 7.0
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD*
1
W
Operating Temperature
Topr
0 to 70
°C
Storage Temperature
Tstg
–55 to 150
°C
Voltage on Any Pin Relative to VSS
*: Ta = 25°C Recommended Operating Conditions Parameter Power Supply Voltage
(Ta = 0°C to 70°C)
Symbol
Min.
Typ.
Max.
Unit
VCC
4.5
5.0
5.5
V
VSS
0
0
0
V
Input High Voltage
VIH
2.4
—
6.5
V
Input Low Voltage
VIL
–1.0
—
0.8
V
Capacitance
(VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Symbol
Typ.
Max.
Unit
Input Capacitance (A0 - A8)
CIN1
—
5
pF
Input Capacitance (RAS, CAS, WE, OE)
CIN2
—
5
pF
Output Capacitance (DQ1 - DQ4)
CI/O
—
6
pF
Parameter
4/17
¡ Semiconductor
MSM514256C/CL
DC Characteristics
Parameter
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Symbol
Condition
MSM514256 MSM514256 MSM514256 MSM514256 C/CL-45 C/CL-50 C/CL-60 C/CL-70 Unit Note
Min. Max. Min. Max. Min. Max. Min. Max. Output High Voltage
VOH
IOH = –5.0 mA
2.4
VCC
2.4
VCC
2.4
VCC
2.4
VCC
V
Output Low Voltage
VOL
IOL = 4.2 mA
0
0.4
0
0.4
0
0.4
0
0.4
V
Input Leakage Current
ILI
All other pins not
–10
10
–10
10
–10
10
–10
10
mA
–10
10
–10
10
–10
10
–10
10
mA
—
85
—
80
—
70
—
60
mA
1, 2
RAS, CAS = VIH
—
2
—
2
—
2
—
2
RAS, CAS
—
1
—
1
—
1
—
1
mA
1
≥ VCC –0.2 V
—
200
—
200
—
200
—
200
mA
1, 5
—
85
—
80
—
70
—
60
mA
1, 2
—
5
—
5
—
5
—
5
mA
1
—
85
—
80
—
70
—
60
mA
1, 2
—
80
—
75
—
65
—
55
mA
1, 3
—
300
—
300
—
300
—
300
mA
1, 2, 4, 5
0 V £ VI £ 6.5 V; under test = 0 V Output Leakage Current
ILO
Average Power Supply Current
ICC1
(Operating) Power Supply Current (Standby)
ICC2
0 V £ VO £ 5.5 V RAS, CAS cycling, tRC = Min.
RAS cycling,
Average Power Supply Current
DQ disable
ICC3
(RAS-only Refresh)
CAS = VIH, tRC = Min. RAS = VIH,
Power Supply Current (Standby)
ICC5
Average Power Supply Current
ICC6
(CAS before RAS Refresh)
RAS cycling, CAS before RAS RAS = VIL,
Average Power Supply Current
CAS = VIL, DQ = enable
ICC7
CAS cycling,
(Fast Page Mode)
tPC = Min.
Average Power
tRC = 125 ms,
Supply Current (Battery Backup)
Notes : 1. 2. 3. 4. 5.
ICC10 CAS before RAS, tRAS £ 1 ms
ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V. L-version.
5/17
¡ Semiconductor
MSM514256C/CL
AC Characteristics (1/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 4, 5 Parameter
Symbol
MSM514256 MSM514256 MSM514256 MSM514256 C/CL-45 C/CL-50 C/CL-60 C/CL-70 Unit Note
Min. Max. Min. Max. Min. Max. Min. Max. tRC
90
—
100
—
120
—
130
—
ns
tRWC
140
—
150
—
170
—
185
—
ns
tPC
34
—
36
—
40
—
45
—
ns
tPRWC
75
—
77
—
90
—
95
—
ns
Access Time from RAS
tRAC
—
45
—
50
—
60
—
70
ns
6, 7, 8
Access Time from CAS
tCAC
—
14
—
14
—
15
—
20
ns
6, 7
Access Time from Column Address
tAA
—
24
—
26
—
30
—
35
ns
6, 8
Access Time from CAS Precharge
tCPA
—
28
—
30
—
35
—
40
ns
6
Access Time from OE
tOEA
—
14
—
14
—
15
—
20
ns
6
Output Low Impedance Time from CAS
tCLZ
0
—
0
—
0
—
0
—
ns
6
CAS to Data Output Buffer Turn-off Delay Time tOFF
0
10
0
10
0
10
0
10
ns
9
OE to Data Output Buffer Turn-off Delay Time tOEZ
0
10
0
10
0
10
0
10
ns
9 3
Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time
Transition Time
tT
3
50
3
50
3
50
3
50
ns
Refresh Period
tREF
—
8
—
8
—
8
—
8
ms
Refresh Period (L-version)
tREF
—
64
—
64
—
64
—
64
ms
RAS Precharge Time
tRP
35
—
40
—
50
—
50
—
ns
RAS Pulse Width
tRAS
45 10,000 50 10,000 60 10,000 70 10,000 ns
RAS Pulse Width (Fast Page Mode)
tRASP
45 100,000 50 100,000 60 100,000 70 100,000 ns
RAS Hold Time
tRSH
14
—
14
—
15
—
20
—
ns
RAS Hold Time referenced to OE
tROH
10
—
10
—
10
—
10
—
ns
CAS Precharge Time (Fast Page Mode)
tCP
10
—
10
—
10
—
10
—
ns
CAS Pulse Width
tCAS
14 10,000 14 10,000 15 10,000 20 10,000 ns
CAS Hold Time
tCSH
45
—
50
—
60
—
70
—
ns
CAS to RAS Precharge Time
tCRP
5
—
5
—
5
—
5
—
ns
RAS Hold Time from CAS Precharge
tRHCP
28
—
30
—
35
—
40
—
ns
RAS to CAS Delay Time
tRCD
17
31
18
36
20
45
20
50
ns
7
RAS to Column Address Delay Time
tRAD
12
21
13
24
15
30
15
35
ns
8
Row Address Set-up Time
tASR
0
—
0
—
0
—
0
—
ns
Row Address Hold Time
tRAH
7
—
8
—
10
—
10
—
ns
Column Address Set-up Time
tASC
0
—
0
—
0
—
0
—
ns
Column Address Hold Time
tCAH
12
—
13
—
15
—
15
—
ns
Column Address Hold Time from RAS
tAR
35
—
40
—
50
—
55
—
ns
Column Address to RAS Lead Time
tRAL
24
—
26
—
30
—
35
—
ns
6/17
¡ Semiconductor
MSM514256C/CL
AC Characteristics (2/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 4, 5 Parameter
Symbol
MSM514256 MSM514256 MSM514256 MSM514256 C/CL-45 C/CL-50 C/CL-60 C/CL-70 Unit Note
Min. Max. Min. Max. Min. Max. Min. Max. Read Command Set-up Time
tRCS
0
—
0
—
0
—
0
—
ns
Read Command Hold Time
tRCH
0
—
0
—
0
—
0
—
ns
10
Read Command Hold Time referenced to RAS tRRH
0
—
0
—
0
—
0
—
ns
10
Write Command Set-up Time
tWCS
0
—
0
—
0
—
0
—
ns
11
Write Command Hold Time
tWCH
10
—
10
—
10
—
15
—
ns
Write Command Hold Time from RAS
tWCR
35
—
40
—
50
—
55
—
ns
Write Command Pulse Width
tWP
10
—
10
—
10
—
15
—
ns
OE Command Hold Time
tOEH
12
—
13
—
15
—
20
—
ns
Write Command to RAS Lead Time
tRWL
14
—
14
—
15
—
20
—
ns
Write Command to CAS Lead Time
tCWL
14
—
14
—
15
—
20
—
ns
Data-in Set-up Time
tDS
0
—
0
—
0
—
0
—
ns
12
Data-in Hold Time
tDH
12
—
13
—
15
—
15
—
ns
12
Data-in Hold Time from RAS
tDHR
35
—
40
—
50
—
55
—
ns
OE to Data-in Delay Time
tOED
12
—
13
—
15
—
20
—
ns
CAS to WE Delay Time
tCWD
36
—
38
—
50
—
50
—
ns
11
Column Address to WE Delay Time
tAWD
48
—
52
—
60
—
65
—
ns
11
RAS to WE Delay Time
tRWD
70
—
75
—
90
—
100
—
ns
11
CAS Precharge WE Delay Time
tCPWD
11
50
—
53
—
60
—
70
—
ns
CAS Active Delay Time from RAS Precharge tRPC
0
—
0
—
0
—
0
—
ns
RAS to CAS Set-up Time (CAS before RAS) tCSR
10
—
10
—
10
—
10
—
ns
RAS to CAS Hold Time (CAS before RAS)
25
—
25
—
30
—
30
—
ns
tCHR
7/17
¡ Semiconductor Notes:
MSM514256C/CL
1. A start-up delay of 100 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. VIH = 3.0 V and VIL = 0.0 V are reference levels for measuring input timing signals (speed ranks 45 and 50). 5. VIH = 2.4 V and VIL = 0.8 V are reference levels for measuring input timing signals (speed ranks 60 and 70). 6. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 7. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 8. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 9. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 10. tRCH or tRRH must be satisfied for a read cycle. 11. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 12. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle.
8/17
E2G0092-17-41E ¡ Semiconductor
MSM514256C/CL
, ,, , ,,,, TIMING WAVEFORM Read Cycle
tRC
tRP
tRAS
RAS
VIH – VIL –
tAR
tCSH
tCRP
tRCD
VIH – CAS VIL – VIH – VIL –
tRSH tCAS
tRAD
tASR
Address
tCRP
tRAH tASC
tRAL
tCAH
Column
Row
tRCS
WE OE
VIH – VIL –
tAA
tROH
tOEA
VIH – VIL –
tCAC
tRAC
DQ
tRCH
tRRH
VOH –
tOEZ
Open
VOL –
tOFF
Valid Data-out
tCLZ
"H" or "L"
Write Cycle (Early Write)
tRC
tRP
tRAS
RAS
VIH – VIL –
tAR
tCRP
CAS
VIH – VIL –
WE
VIH – VIL –
tCSH
tRCD
tRSH
tCAS
tRAD tRAH
tASR
Address
tCRP
tASC
Row
tCAH
Column
tWCS
tWCH
VIH –
tRWL
VIH –
VIL –
tDS
DQ
tCWL
tWP
VIL –
tWCR
OE
tRAL
VIH –
VIL –
tDHR
tDH
Valid Data-in
Open
"H" or "L"
9/17
, ,, ¡ Semiconductor
MSM514256C/CL
Read Modify Write Cycle
tRWC
tRAS
RAS
VIH – VIL –
tRP
tAR
tCRP
tCSH
tCRP
tRCD
tRSH
tCAS
VIH – CAS VIL –
tASR
VIH – Address VIL – WE
VIH – VIL –
OE
VIH – VIL –
tRAH
tASC
tCAH
Column
Row
tRAD
tRWD
tAA
tAWD
tRCS
tOEA
tOED
tCAC
tRAC
DQ
VI/OH–
VI/OL–
tCWL tRWL tWP
tCWD
tCLZ
tOEZ
Valid Data-out
tOEH
tDS
tDH
Valid Data-in
"H" or "L"
10/17
,,, , ,,, ¡ Semiconductor
MSM514256C/CL
Fast Page Mode Read Cycle
tRASP
VIH – RAS V – IL VIH – CAS VIL –
Address
WE
VIH – VIL –
tAR
tCRP
tRHCP
tPC
tRCD
tRAD
tASR
tRAH tASC
tCP
tCAS
tCSH tCAH
tASC
Column
Row
VIH – VIL –
Column
tRCS
tRCH
tCAC
tOEZ
tRRH
tCPA
tOEA
tOFF
tRCH
tAA
tAA
tCAC
tOEA
tOFF
tCAC
tOEZ
tCLZ
Valid Data-out
tCLZ
tRCS
tCPA
tOEA
VOH – VOL –
tRAL tCAH
tASC
Column
tAA
tRAC
tCAS
tCAH
tRCH
tRCS
tCRP
tRSH
tCP
tCAS
VIH – OE VIL –
DQ
tRP
tCLZ
tOFF
tOEZ
Valid Data-out
Valid Data-out
"H" or "L"
Fast Page Mode Write Cycle (Early Write)
tRASP
tAR
VIH – RAS V – IL
tCRP
VIH – CAS VIL –
Address
VIH – VIL –
tRCD
tRAH tASC
Row
tWCS
WE
VIH – VIL –
tDS
VIH – DQ VIL –
tCSH tCAH
Column tCWL tWCH tWP
tRAD
tRHCP
tRSH
tCAS
tASR
tRP
tPC
tWCR tDH
Valid Data-in
tDHR
tCP
tCRP
tCP
tCAS
tASC
tCAH
tASC
Column tCWL tWCS tWCH tWP
tDS
tDH
Valid Data-in
tCAS
tCAH
tRAL
Column tRWL tCWL tWCS tWCH tWP tDS
tDH
Valid Data-in
Note: OE = "H" or "L"
"H" or "L"
11/17
¡ Semiconductor
MSM514256C/CL
,, , , ,, ,
Fast Page Mode Read Modify Write Cycle
tRASP
VIH – RAS VIL –
tAR
tRP
tCSH
tPRWC
tRCD
VIH – CAS VIL –
tASC
tCAH
tRAH
VIH – VIL –
tCRP
tCAS
tASC
tCAH
tCAH
Column
Column
tASC
Column
Row
tRCS tCPWD tCWD
tRWD
tCWD
tRCS
V WE IH – VIL –
tCWL
tAWD
tCWL
tWP tDH
VI/OH– VI/OL –
Out
tCLZ
tOEA
tOED
tOEZ
tCAC
In
tDH
tDS
tOEA
tOEZ
tCAC
tWP
tCPA tAA
tOED
VIH – OE V – IL
tCWL
tROH
tWP tDH
tDS
tOEA
tRWL
tAWD
tCPA tAA
tAA
tRAL
tRCS tCPWD tCWD
tAWD
tDS
tRAC
DQ
tCP
tCAS
tRAD
tASR
Address
tCP
tCAS
tRSH
Out
tOED
In
tCLZ
tOEZ
tCAC
Out
In
tCLZ
"H" or "L"
RAS-Only Refresh Cycle
tRC
RAS
CAS
Address
VIL –
VIH – VIL –
VIH – VIL –
tRP
tRAS
VIH –
tCRP
tASR
tRPC
tRAH
Row
tOFF
DQ
VOH – VOL –
Open
Note: WE, OE = "H" or "L"
"H" or "L"
12/17
,, , ,,
¡ Semiconductor
MSM514256C/CL
CAS before RAS Refresh Cycle
tRC
tRP
RAS
VIH – VIL –
DQ
tRP
tRPC
tRPC
tCSR
tCP
CAS
tRAS
VIH – VIL –
tCHR
tOFF
VOH – VOL –
Open
Note: WE, OE, Address = "H" or "L"
"H" or "L"
Hidden Refresh Read Cycle
tRC
tRAS
RAS
VIH –
tRP
tAR
VIH – VIL –
VIH – VIL –
tRSH
tRCD
tRAD tASC tRAH
tASR
Address
tRAS
tRP
VIL –
tCRP
CAS
tRC
Row
tCHR
tCAH
Column
tRCS
tRAL
VIH – WE V IL –
tRRH
tAA
tROH
tOEA
VIH – OE V IL –
tRAC DQ
VOH – VOL –
tCAC tCLZ
tOFF tOEZ Valid Data-out "H" or "L"
13/17
, ,, , ¡ Semiconductor
MSM514256C/CL
Hidden Refresh Write Cycle
tRC
tRP
tRAS
RAS
VIH –
tRP
tAR
VIH –
VIH – VIL –
tRSH
tRCD
tRAD tASC tRAH
VIL –
tASR
Address
tRAS
VIL –
tCRP
CAS
tRC
tCHR
tCAH t RAL
Column
Row
tWCS
VIH – WE V – IL
tWCH
tWP
tWCR
VIH – OE V IL –
tDS
DQ
VIH – VIL –
tDH
Valid Data-in tDHR
"H" or "L"
14/17
¡ Semiconductor
MSM514256C/CL
PACKAGE DIMENSIONS (Unit : mm) DIP20-P-300-2.54-W1
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.50 TYP.
15/17
¡ Semiconductor
MSM514256C/CL
(Unit : mm)
SOJ26/20-P-300-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.80 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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¡ Semiconductor
MSM514256C/CL
(Unit : mm)
ZIP20-P-400-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.50 TYP.
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