MB1501/MB1501H/MB1501L SERIAL INPUT PLL FREQUENCY SYNTHESIZER SERIAL INPUT PLL FREQUENCY SYNTHESIZER WITH 1.1GHz PRESCALER The Fujitsu MB1501/MB1501H/MB1501L, utilizing BI-CMOS technology, is a single chip serial input PLL frequency synthesizer with pulse-swallow function. The MB1501 series contain a 1.1GHz two modulus prescaler that can select either 64/65 or 128/129 divide ratio; control signal generator; 16-bit shift register; 15-bit latch; programmable reference divider (binary 14-bit programmable reference counter); 1-bit switch counter; phase comparator with phase inverse function; charge pump; crystal oscillator; 19-bit shift register; 18-bit latch; programmable divider (binary 7-bit swallow counter and binary 11-bit programmable counter). The MB1501 operates on a low supply voltage (3V typ) and consumes low power (45mW at 1.1GHz).
PLASTIC PACKAGE DIP-16P-M04
MB1501 Product Line DO Output Width MB1501 8V max 8.5V max Middle speed Middle MB1501H 10V max 10.0V max High speed Low MB1501L 8V max 8.5V max Low speed High VP Voltage
VOOP Voltage
Lock up time
High-level Low-level Output Output Current Current Middle Middle High Low Low High
• • • • •
High operating frequency: fIN MAX=1.1GHz (PIN MIN=0.20VP-P) On-chip prescaler Low power supply voltage: 2.7V to 5.5V (3.0V typ) Low power supply consumption: 45mW (3.0V, 1.1GHz operation) Serial input 18-bit programmable divider consisting of: Binary 7-bit swallow counter (Divide ratio: 0 to 127) Binary 11-bit programmable counter (Divide ratio: 16 to 2047) • Serial input 15-bit programmable reference divider consisting of: Binary 14-bit programmable reference counter (Divide ratio: 8 to 16383) 1-bit switch counter (SW) Sets divide ratio of prescaler • 2types of phase detector output On-chip charge pump (Bipolar type) Output for external charge pump • Wide operating temperature: TA=–40°C to +85°C
Symbol VCC VPH VP,VPL VOUT VOOPH
Power Supply Voltage Output Voltage Open-drain Output
VOOP,VOOPL
Output Current Storage Temperature NOTE:
Copyright
IOUT TSTG
MB1501H MB1501/1501L
16 ØR 15 ØP
OSCIN 1 OSCOUT 2 VP 3 VCC 4 GND 6
Condition MB1501H MB1501/1501L
PIN ASSIGNMENT
DO 5
ABSOLUTE MAXIMUM RATINGS (see NOTE) Rating
PLASTIC PACKAGE FPT-16P-M06
Value
Unit
LD 7
–0.5 to +7.0 VCC to 12.0 VCC to 10.0 –0.5 to VCC +0.5 –0.5 to 11.0 –0.5 to 9.0 ±10 –55 to +125
V
fin 8
14 fP ( TOP VIEW )
13 fr 12 FC 11 LE 10 Data 9 Clock
V V V mA °C
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1994 by FUJITSU LIMITED
and FUJITSU MICROELECTRONICS, INC.
1
MB1501 MB1501H MB1501L
MB1501/MB1501H/MB1501L BLOCK DIAGRAM
VCC
16-Bit Shift Register
4
16-Bit Shift Register GND
6 15-Bit Latch
LE
15-Bit Latch
11
Programmable Reference Divider OSCIN
1
OSCOUT
2
Crystal Oscillator Circuit
1-bit Binary 14-Bit Reference Counter SW
Phase Comparator
13
fr
12
FC
7
LD
16
R
15
P
3
VP
5
DO
14
fP
19-Bit Shift Register 19-Bit Shift Register
fin
8
Prescaler Circuit
18-Bit Latch 7-Bit Latch
11-Bit Latch
Programmable Divider
Data
10
Clock
9
Control 1-Bit Latch
Binary 7-Bit Swallow Counter
Binary 11-Bit Programmable Counter
Control Circuit
2
Charge Pump
MB1501 MB1501H MB1501L
PIN DESCRIPTIONS Pin No.
Pin Name
I/O
Descriptions
1 2
OSCIN OSCOUT
I O
Oscillator input. Oscillator output. A crystal is placed between OSCIN and OSCOUT.
3
VP
—
Power supply input for charge pump.
4
VCC
—
Power supply voltage input.
5
DO
O
Charge pump output. Phase characteristic can be inversed depending upon FC input.
6
GND
—
Ground.
7
LD
O
Phase comparator output. This pin outputs high when the phase is locked. While the phase difference of fr and fp exists, the output level goes low.
8
fin
I
Prescaler input. The connection with an external VCO should be an AC connection.
9
Clock
I
Clock input for 19-bit shift register and 16-bit shift register. Each rising edge of the clock shifts one bit of data into the shift registers.
10
Data
I
Serial data of binary code input. The last bit of the data is a control bit. The last data bit specifies which latch is activated. When the last bit is high level and LE is high-level, data is transferred to 15-bit latch. When the last bit is low level and LE is high level, data is transferred to 18-bit latch.
11
LE
I
Load enable input (with internal pull up resistor). When LE is high level (or open), data stored in the shift register is transferred to latch depending on the control data.
12
FC
O
Phase selecting input of phase comparator (with internal pull up resistor). When FC is low level, charge pump and phase detector characteristics can be inversed.
13
fr
O
Monitor pin of phase comparator input. It is the same as programmable reference divider output.
14
fP
O
Monitor pin of phase comparator input. It is the same as programmable divider output.
15 16
P R
O O
Outputs for external charge pump. Phase characteristics can be inversed depending on FC input. P pin is an N-channel open-drain output.
3
MB1501 MB1501H MB1501L
FUNCTIONAL DESCRIPTIONS SERIAL DATA INPUT Serial data input is input using Data pin, Clock pin and LE pin, The 15-bit programmable reference divider and 18-bit programmable divider are controlled respectively. On rising edge of the clock shifts one bit of the data into the internal shift registers. When load enable (LE) is high level (or open), data stored in shift resisters is transferred to 15-bit latch or 18-bit latch depending upon the control bit level. Control data “H” ; Data is transferred into 15-bit latch. Control data “L” ; Data is transferred into 18-bit latch.
PROGRAMMABLE REFERENCE DIVIDER Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit reference counter. Serial 16-bit data format is shown below.
Last data input
Data input Divide ratio of prescaler setting bit MSB
Control bit LSB
C
First data input
S
S
S
S
S
S
S
S
S
S
S
S
S
S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SW
Divide ratio of programmable reference counter setting bits
14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO Divide ratio R
S
S
S
S
S
S
S
S
S
S
S
S
S
S
14
13
12
11
10
9
8
7
6
5
4
3
2
1
8
0
0
0
0
0
0
0
0
0
0
1
0
0
0
9
0
0
0
0
0
0
0
0
0
0
1
0
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Divide ratio less than 8 is prohibited. Divide ratio R: 8 to 16383 SW: Divide ratio of prescaler setting bit. SW=“H” : 64 SW=“L” : 128 S1 to S14: Divide ratio of programmable reference counter setting bits (8 to 16383) C: Control bit (Control bit is set to high.)
4
MB1501 MB1501H MB1501L
FUNCTIONAL DESCRIPTIONS PROGRAMMABLE DIVIDER Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter. Serial 19-bit data format is shown below.
Data input
Last data input
C
First data input
Control bit LSB
MSB
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Divide ratio of swallow counter setting bits
7-BIT SWALLOW COUNTER DIVIDE RATIO
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO S
S
S
S
S
S
S
S
S
S
S
1
Divide ratio N
18
17
16
15
14
13
12
11
10
9
8
0
0
16
0
0
0
0
0
0
1
0
0
0
0
0
0
1
17
0
0
0
0
0
0
1
0
0
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
2047
1
1
1
1
1
1
1
1
1
1
1
Divide ratio A
S
S
S
S
S
S
S
7
6
5
4
3
2
0
0
0
0
0
0
1
0
0
0
0
•
•
•
•
127
1
1
1
Divide ratio A : 0 to 127
Divide ratio of programmable counter setting bits
Divide ratio less than 16 is prohibited. Divide ratio N : 16 to 2047
S8 to S18 :Divide ratio of programmable counter setting bits (16 to 2047) S1 to S7 : Divide ratio of swallow counter setting bits (0 to 127) C: Control bit (Control bit is set to low.) Dara is input from MSB data.
5
MB1501 MB1501H MB1501L SERIAL DATA INPUT TIMING
Data
S18=MSB *(SW)
S17
S10
S9
S1=LSB
C: Control bit
(S14)
(S8)
(S7)
(S1)
(C: Control bit)
Clock
LE t3
t2
t1
t5 t1 – t5 ≥ 1µs
t4
On the rising edge of the clock shifts one bit of the data into the shift registers. Parenthsis data is used for setting the divide ratio of the programmable reference divider.
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