Layered reconfiguration management for designing novel reconfigurable SoC Xun ZHANG, Hassan RABAH, Serge WEBER Nancy University Laboratoire d’Instrumentation Electronique de Nancy BP239, 54506, Vandoeuvre-les-Nancy Email: xun.zhang, hassan.rabah, [email protected]

I. I NTRODUCTION Reconfigurable architectures for Field Programmable Gate Arrays(FPGAs) have become more and more popular. Due to the rapid technology improvements, it is possible to design systems which are dynamically reconfigurable. In the research area of reconfigurable computing systems, most of recent works focus on the re-use of devices like FPGAs for different application of different partitions of an application. However, it is well known that reconfiguration overhead drastically affects both the system performance and energy consumption [1]. Due to the reconfiguration efficiently that mainly depends on the size and number of re-used device or partition, a huge or number of reconfigurable device takes great reconfiguration time. Different approaches have been proposed in order to cope with this problem. Among these researches, scheduling algorithms are used to minimize the reconfiguration overhead in partially reconfigurable hardware by hiding reconfiguration latency [2] [3]. In this case, a particular effort must be done in the design of scheduler and reconfiguration manager. Reconfiguration overhead can also be reduced using a multi-context technology, as used in coarse grained reconfigurable circuits, to the detriment of flexibility and huge among of memory requirement [4]. A concept of hyper-configurable architecture has been introduced as an alternative [5] [6]. In this concept, a resource allowing reconfiguration is reconfigurable itself by defining different levels of reconfiguration. The drawbacks of this method are the reconfiguration memory requirement, the complex control circuitry and the use of specific target architecture. On other hand, with the down scaling technology, the modern FPGAs integrate huge among of mixed grain hardware resources ranging from several hard microprocessors, hard arithmetic operators to hundred of thousand of simple gates allowing the integration of various soft cores. Thus, the problem of resources management becomes then very acute especially in reconfigurable systems. This situation attracts us to have the research motivation to research a novel reconfigurable SoC at which the reconfiguration overhead could be efficiently reduced through designing layered reconfiguration management in corresponding with the possible requirement of system.

II.

HIERARCHICAL RECONFIGURATION MANAGEMENT

The layered reconfiguration management is represented on two reconfiguration levels. One application is decomposed into various parts which are installed on the two reconfiguration levels to adapt with the particular requirement of system. The rule of decomposition is the Adaptation of SoC that is an ability of SoC to adapt the external requirement during run-time by adjusting its structure. The switching of different application is depicted on the first reconfiguration level; the exchanging between different versions of application is represented on the second reconfiguration level, which are: the global reconfiguration level and the local reconfiguration level. The communication between two levels is unique built through the communication module on two levels. A. Global reconfiguration level In the global reconfiguration level, it is possible to reconfigure the communication between clusters and elements of a cluster in order to meet a particular need. One or more Reconfigurable Processing Module (RPM) which is represented on the local reconfiguration level is composed on this level with others on chip peripheral. Each RPM can not only be reconfigured totally at runtime, but also can be reconfigured partially on the local reconfiguration level. Fig. 1.

Layered architecture

B. Local reconfiguration level The local reconfiguration level represents the adaptive of task by reconfiguration at processing element level, where versions of a task can be mapped into software or hardware. The software version can be executed on a general purpose embedded processor or a specific embedded core processor. The hardware versions can be mapped on a RPM. The reconfiguration of RPM is achieved by reconfiguring the interface of reconfiguring the data-path or the two. Fig. 2.

General architecture of the RPM

Fig. 3.

R EFERENCES

Target architecture.

III. I MPLEMENTATION DETAILS AND RESULTS A. Design methodology and framework A 2-D Inverse Discret Wavelet Transform is implemented using the 5/3 and 9/7 − F filters. the IDWT architecture targeting a Xilinx FPGAs of the Virtex family(Virtex-4) [7]. We choose a 50MHz frequency of operation for an adequate comparison with other architectures. In the proposed organisation, the data image can be read from different memory area allowing an efficient parallelism. The IDWT module can reconstruct the image with different resolutions according to the requirement. The number of computational modules could be changed at run-time as well as its interface with memory. It requires that the Reconfigurable Interface be used not only to build the connection with the memory and computation module, but also be used like a controller to manage the working sequence of system. the result of decomposition of application in our experiment is shown in the Table I. the table I shows different parts of the system, the size of corresponding bitstream file and their configuration time. The system consists of a static part and reconfigurable parts ( P art1 and P art2 are the two versions of reconfigurable communication allowing the switching between two filters, P art3 corresponds to 5/3 filter, and P art4 is the difference between 5/3 filter and 9/7 filter ). The configuration time is measured using a free running counter (timer) incremented every system clock cycle, and capturing the start time and the end time. We see that the configuration time as expected depends linearly on the size of bitstream. TABLE I C ONFIGURATION OVERHEAD System parts

Size KB

Overhead

(ms)

TBRAM

TICAP

Tconf ig

Static part

582

by JTAG

2 seconds

P art1

63

87.6

0.97

90

P art2

11

15.6

0.19

16

P art3

33

41.7

0.43

45.3

P art4

28

38.9

0.27

40.2

IV. C ONCLUSION AND FUTURE WORK In this paper, we have described one organization solution, the layered reconfiguration management, used for designing reconfigurable architecture. hierarchical reconfiguration levels are defined in order to minimize the reconfiguration overhead and support the system switch it’s application or it’s function more flexibility. In the future work, the reconfiguration controller that supports auto-adaptation corresponding to the application requirement will be optimized. An efficient reconfiguration management is under study to reduce the reconfiguration overhead.

[1] S. Mallat, ”A Theory for Multiresolution Signal Decomposition: The Wavelet Representation”, IEEE Transactions on Pattern Analysis and Machine Intellignece, Vol. 11, no. 7, pp674-693, July 1989. [2] L.Shang and N.K.Jha Hardware/Software Co- Synthesis of Low Power Real-time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs Proc.Asia South Pacific Design Automation Conf.(ASPDAC 02). ACM Press. 2002, PP. 345-354. [3] R.Maestre et al., Configuration Management in Multi-context Reconfigurable Systems for Simultaneous Performance and Power Optimizations, Proc.13 Intl Symp. System Synthesis(ISSS 00), IEEE Press,2000,pp.107113 [4] IPFlex,Inc. DAP/DNA Overview. http://www.ipFlex.com/ [5] S.Lange, Martin Middendorf, On the Design of Two- Level Reconfigurable Architectures, reconfig, p. 9, 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig05), 2005. [6] S.Lange,M.Middendorf: Models and Reconfiguration Problems for MultiTask Hyperreconfigurable Architectures. Accepted for the 11th Reconfigurable Architecture Workshop(RAW 2004),Santa Fe,New Mexico ,2004. [7] Datasheet.V4,Xilinx, Inc.2004. ”Virtex-4 Data sheet”, Xilinx Inc. San Jose, CA [8] XAPP-290,Xilinx Inc. ”Two flows for partial reconfiguration: modulebased or difference based.” Xilinx App. Note 290 Sep., 2004