HARDWARE EMULATION OF A NETWORK ON CHIP ARCHITECTURE BASED ON A CLOCKWORK ROUTED MANHATTAN STREET NETWORK Kurian Oommen
David Harle
Institute for System Level Integration Livingston Scotland, UK email:
[email protected]
University of Strathclyde Glasgow Scotland, UK email:
[email protected]
Memory Elements (Lookup tables)
Traditionally, the interconnection of intellectual property blocks (IP) on integrated circuits (IC) was implemented using bus-based architectures and dedicated wires satisfying the communication requirements of, at most, several dozen interacting IPs. The International Roadmap for Semiconductors (ITRS) predicts the productional use of integrated circuits supporting over four billion transistors by the end of the decade. However, such shrinking systemon-chip (SoC) geometries mean that device scaling generally progresses more rapidly than interconnect performance. To alleviate inter-connect problems and achieve future performance demands, previous studies have identified networks on chip (NoC) as an emerging alternative to dedicated wires and shared bus architectures [1, 2].
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connects incoming to outgoing links. The Clockwork (CW) Routing Scheme is a time-slotted system that enhances the MSN by including a simple routing mechanism employed at intermediate nodes that prevents resource contentions, requires no re-sequencing of packets at the destination node and has comparable throughput to conventional routing schemes [4]. Due to the deterministic nature of the routing mechanism, upper bounds on the network delay can be established. This makes the CW particularly suited to applications involving real time constraints.
A shift in focus from computation to communication can be predicted in the future designs because communication is now a major bottleneck [3]. This study proposes a tile based NoC architecture based on the Manhattan Street Network (MSN) using clockwork routing for the implementation of high speed network within a chip. The proposed architecture has a contention-free network layer, removing the need for storing in transit packets in intermediate routing nodes; the throughput remains comparable to the conventional routing schemes. The use of such a network architecture in place of the globally spanning wires provides structure, performance and modularity in design.
3. ROUTING IN THE MSN The routing function at each node was initially performed using a routing table which contained the timeslot and the output port for the various source destination combinations. One of the key features of the MSN with CW is the ability to implement the functionality in hardware without the need for custom routing tables at each node. In addition to the reduced complexity, this also provides great saving in terms of the area as the hardware routing complexity increases linearly in comparison to the routing table memory requirement which, in turn increases exponentially as the network scales. This trend is illustrated in Fig 1.
2. BACKGROUND (MANHATTAN STREET NETWORK) The MSN is a self-routing regular topology, originally proposed for local and metropolitan area network applications. An MSN is characterised as a two-connected regular mesh with the nodes connected as rows and columns. Each node consists of a 2x2 cross-bar switch that
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1. INTRODUCTION
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This is not a significant overhead when considered in the context of an ASIC and can be further improved with additional optimisations. Fig 2 illustrates the floor plan view of the placed and routed MSN. On careful observation the 16 nodes can be identified. The study aims to further evaluate various buffering schemes within an MSN NoC node. 5. REFERENCES
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4x4 MSN Floor Plan
4. IMPLEMENTATION A 4x4 MSN hardware emulation platform was assembled and synthesized onto the Xilinx Virtex 2 6000 FPGA. The MSN System occupied 40% (14,000 slices) of the resources on the FPGA. An MSN node was synthesized independently and was found to contain approximately 2,500 ASIC gates, a figure which is considerably smaller than the 13,000 gate NoC node described in [5].
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[1]
L. Benini and G. D. Micheli, "Networks on Chips: A New SoC Paradigm," IEEE Computer, vol. 35, pp. 70-78, 2002.
[2]
W. j. Dally and B. Towles, "Route Packets, Not Wires: OnChip Interconnection Networks," presented at Design and Automation Conference, Las Vegas, USA, 2001.
[3]
A. Jantsch and H. Tenhunen, "Will networks on chip close the productivity gap," in Networks on chip: Kluwer Academic Publishers, 2003, pp. 3--18.
[4]
F. Chevalier, "Performance Evaluation of the Clockwork Routing Scheme in Optical Packet Switching Networks," in Department of Electronic and Electrical Engineering. Glasgow: Univerisity of Strathclyde, 2000, pp. 208.
[5]
P. Bhojwani and R. Mahapatra, "Interfacing Cores with Onchip Packet-Switched Networks," presented at 16th International Conference on VLSI Design, New Delhi, India, 2003.
