MOS LSI
TMS4116 16,384-811 DYNAMIC RANDOM-ACCESS MEMORY OCTOBER 1977 - REVISED MAY 1982
16,384 X 1 Organization
0
• • 0
TMS4116 .•• NL PACKAGE (TOP VIEW)
10% Tolerance on All Supplies VBB D
All Inputs Including Clocks TTL-Compatible
iN
Unlatched Three-State Fully TTL-Compatible Output
•
TMS4116-15 TMS4116-20 TMS4116-25 0
150 ns 200 ns 250 ns
100 ns 135 ns 165 ns
READ OR WRITE CYCLE (MIN)
READ, MODIFYWRITEt CYCLE (MIN)
375 ns 375 ns 410 ns
375 ns 375 ns 515 ns
• 0
A6
AO
A3
Common I/O Capability with "Early Write" Feature Low-Power Dissipation - Operating 462 mW (Max) 20 mW (Max) Standby
A2
A4
Al
A5
VDD ........._ _--'"-VCC
PIN NOMENCLATURE AO-A6
Addresses
CAS
Column Address Strobe
D
Page-Mode Operation for Faster Access Time
Q
RAS
3 Performance Ranges: ACCESS ACCESS TIME TIME ROW COLUMN ADDRESS ADDRESS (MAX) (MAX)
VSS CAS
, Data Input
Q
Data Output
RAS
Row Address Strobe
VBB
-5-V Power Supply
VCC
+ 5-V
Power Supply
VDD
+ 12-V Power Supply
VSS
Ground
IN
Write Enable
CI) Q)
CJ
"S;
Q)
C
......
oQ. Q.
:::l
Ul
1-T Cell Design, N-Channel Silicon-Gate Technology
0
•
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16-Pin 300-Mil (7.62 mm) Package Configuration
E Q)
~
description
"t:J
The TMS4116 series is composed of monolithic high-speed dynamic 16,384-bit MOS random-access memories organized as 16,384 one-bit words, and employs single-transistor storage cells and N-channel silicon-gate technology. All inputs and outputs are compatible with Series 74 TTL circuits including clocks: Row Address Strobe RAS (or R) and Column Address Strobe CAS (or C). All address lines (AO through A6) and data in (D) are latched on chip to simplify system design. Data out (Q) is unlatched to allow greater system flexibility. Typical power dissipation is less than 350 milliwatts active and 6 milliwatts during standby (VCC is not required during standby operation). To retain data, only 10 milliwatts average power is required which includes the power consumed to refresh the contents of the memory.
c::
CO
~
RAS3 CAS
R/W D
E Q)
TIMING & CONTROL
~
~----------------------------~
'C C
~
ca
A6
ROW
H~ ROW
A5 A4
ADDRESSI-
11/21 MEMORY ARRAY
up
~ DECODE
A3 A2
BUFFERS 171
11/21 1 OF 64 COLUMN DECODE SENSE AMP
f---7--
-
-
CONTROL
11/21 1 OF 64 COLUMN DECODE
COLUMN
'---
DUMMY CELLS
ADDRESS
""-
'---
128 SENSE REFRESH AMPS
c:t: a:
IN REG
DUMMY CELLS
A1 AD
~
110
._--f-::::~~, f-4-~
----
'""'''
10F2 1/0 SELECTIO
(,)
'E
ca
DATA OUT REG.
c >
C
f- 1/0
ROW
BUFFERS
~ DECODE
~~
11/21 MEMORY ARRAY
AD·A6
TEXAS
INSTRUMENTS POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
4-3
TMS4116 16,384-8IT DYNAMIC RANDOM-ACCESS MEMORY
absolute maximum ratings over operating free-air temperature range (unless other~ise noted) t Voltage on any pin (see Note 1) ............................................. -0.5 V to 20 V -1 V to 15 V Voltage on Vee, Voo supplies with respect to Vss ................................ Short circuit output current ........................................................ 50 mA Power dissipation ................................................................. 1 W Operating free-air temperature range ............................................ ooe to 70 0 e Storage temperature range ................................................ - 65 °e to 150 0 e t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affact device reliability. NOTE 1: Under absolute maximum ratings, voltage values are with respect to the most-negative supply voltage, Vee (substrate), unless otherwise noted. Throughout the remainder of this data sheet, voltage values are with respect to VSS'
recommended operating conditions MIN
NOM
MAX
UNIT
Supply voltage, VSS
4.5
-5
-5.5
V
Supply voltage, VCC Supply voltage, VOO
4.5 10.8
5 12
5.5 13.2
V V
PARAMETER
c
-
C
. ,'TEXAS INSTRUMENTS POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
4-5
TMS4116 16,384·BIT DYNAMIC RANDOM·ACCESS MEMORY
timing requirements over recommended supply voltage range and operating free-air temperature range ALT.
PARAMETER
SYMBOL
TMS4116-15
TMS4116-20
TMS4116-25
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
tC(PI
Page-mode cycle time
tpc
170
225
275
ns
tc(rd)
Read cycle time
tRC
375
375
410
ns
tc(WI
Write cycle time
twc
375
375
410
ns
tc(rdW)
Read, modify-write cycle time
375
375
515
ns
tw{CHl
Pulse width,
tRWC tcp
60
80
100
ns
tCAS tRP
100
tRAS twp
150
CAS
high (precharge time)
tw(CL)
Pulse width, CAS low
tw(RHI
Pulse width RAS high (precharge time)
twIRL)
Pulse width, ~ low
tw(W)
Write pulse width
tt
Transition times (rise and fall) for
135
10,000
120 10,000
45 3
tT
RAS and CAS
10,000
100
200
3
10,000
150 10,000
55 35
165 250
ns 10,000
ns
50
ns
75 50
3
ns
ns
tsu(CA)
Column address setup time
tASC
-10
-10
-10
ns
tsu(RA)
Row address setup time
tASR
0
0
0
ns
o
tsu(D)
Data setup time
tDS
0
0
0
ns
tsu(rd)
Read command setup time
tRCS
0
0
0
ns
C»
tsu(WCH)
tCWL
60
80
100
ns
tRWL
60
80
100
ns
tCAH
45
55
75
ns
tRAH
20
25
35
ns
tAR
95
120
160
ns
-
tsu(WRH)
3: CD 3 o...
-
C
TEXAS
INSTRUMENTS POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
4-7
1MS4116 16,384·811 DYNAMIC RANDOM·ACCESS MEMORY
early write cycle timing
c
fI)
4-8
TEXAS
INSTRUMENTS POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
TMS4116 16,384·811 DYNAMIC RANDOM·ACCESS MEMORY
write cycle timing
en
Q) (J
'S; Q)
C
ADDRESSES
.......
oQ. Q. ~
rJ)
...>o
E
Q)
~ "C
C a:1
DI
~
« 0: (J
'Ea:1
DO
c >
C
t The enable time (ten) for a write cycle is equal in duration to the access time from
CAS (ta(C)) in a read cycle; but the active levels at the output are invalid.
TEXAS
INSTRUMENTS POST OFFICE
aox
225012 • DALLAS. TEXAS 75265
4-9
TMS4116 16,384·8IT DYNAMIC RANDOM·ACCESS MEMORY
read·write/read-modify-write cycle timing
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ADDRESSES
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ADDRESSES
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