The Design Technology Leader Mark Flomenhoft VP of High Level Synthesis System Level Design
1-June-01 ©2001 Synopsys, Inc. (MF)
Chip content growing Application Market Growth
35% 30%
CAGR % (1997-2002)
25% 20% 15%
Video Camera
10%
Digital Camera and Camcorder Set-Top Handheld Computing Box DVD Devices”Pilot” Player Internet Game Consoles Smart Cards/Kiosks Internet Smart Access Devices Appliance-Phone Advanced Desktop PC and Workstation Multimedia PC Automotive Applications/GPS Portable 1st Generation Computing Switching 2nd Generation & LAN 3rd Generation HDTV
Car Radio
CD
Color TV
5%
Semiconductor Industry
0% 0%
5%
10%
15%
20%
25%
30%
Semiconductor Content (% of Equipment Cost) Source: Applied Materials, Dataquest
© 2001 Synopsys, Inc. (MF #2)
35%
Design productivity impacted by EDA innovation waves Silicon Opportunity
Physical Synthesis Synthesis
Place and Route
Design Productivity
Pattern Generation
1960 © 2001 Synopsys, Inc. (MF #3)
1970
1980
1990
2000
The design landscape IP and System Design
Services IC Implementation
Verification and Test
Transistor Level Design © 2001 Synopsys, Inc. (MF #4)
Design challenges HW/SW Complexity
IP and Systems Design
Timing Closure
Verification Crunch
Test Services IC Implementation Low Power
© 2001 Synopsys, Inc. (MF #5)
Verification and Test Signal Integrity Transistor Level Design
Design challenges IP and Systems Design Timing Closure
Test Services
IC Implementation Low Power
© 2001 Synopsys, Inc. (MF #6)
Verification and Test
Transistor Level Design
< 0.18µm: Interconnect dominates delay Timing Closure is the critical implementation problem Delay (ps) 70
Cu 1.7µΩ-cm Low κ===2.0 Line 43µ long .8µ=thick
60 50 40 30
Interconnect Delay
20 10
Gate Delay 650
500
© 2001 Synopsys, Inc. (MF #7)
350
250
180
150
100
70 (nm)
< 0.18µm designs taking off Designs Completed by Feature Dimension 100%
75%
50% 0.35µ 0.25µ
25%
0.18µ and below
0% 1999 2000 2001 2002 2003 2004 2005 2006 2007 Source: IBS 7/00 © 2001 Synopsys, Inc. (MF #8)
Timing closure: Market leaders are taping out with Synopsys Physical Synthesis
Giga-flop Vector CPU
Graphics 5M+ gates, 366 MHz 0.18 micron
Enterprise Server 1.5M Gates 200 MHz 0.18 micron
Wireless 200k Gates 180 MHz 0.18 micron
Computing 8M+ gates, 450 MHz 0.12 micron
64 completed designs, 71 customers, 12 of top 15 semi companies © 2001 Synopsys, Inc. (MF #9)
Test integrated with Physical Compiler RTL RTL Physical & Synthesis Synthesis Scan Insertion & Scan Insertion
P&R ATPG Scan Chain Reordering Route ATPG
© 2001 Synopsys, Inc. (MF #10)
Optimized scan chain, simplified flow
Power integrated with Physical Compiler RTL RTL
Better results, simplified flow
Synthesis Physical Synthesis with P&R Power Opt. Reoptimize Design
Incremental Route P&R Power Consumed = 1.2W 2.4W © 2001 Synopsys, Inc. (MF #11)
Design challenges IP and Systems Design
Verification Crunch Services
IC Implementation
Verification and Test
Transistor Level Design © 2001 Synopsys, Inc. (MF #12)
Complexity Growing 100T Vectors
How time is spent 2007 Design 30%
100B Vectors
2001 100M Vectors
1995 1M Gates
10M Gates
100M Gates
Verification 70% Source: Collett International
100B simulation cycles for a 10M-gate design! © 2001 Synopsys, Inc. (MF #13)
Synopsys verification solution Faster & Smarter Testbench Automation
Code Coverage Vera ®
Verification IP
CoverMeter
Mixed-HDL DesignWare ®
LEDA ®
HDL Checking
VCS Scirocco Formal Verification
Static Timing Analysis © 2001 Synopsys, Inc. (MF #14)
NanoSim™
Formality ®
Circuit Simulation
Mixed-Signal PrimeTime ® PathMill ®
PrimePower
Power Analysis
VCS: the fastest Verilog simulator Gate-level Performance
Performance
Roadrunner Radiant
6.0
5.2
ASIC Sign-Off 5.0/5.1 Cycle & 2-State Language Optimizations 4.0 Native Code Compiled 2.0 Code
3.X
4.1/4.2
>
/ X 2
r a Ye
1.0 1993
1994
© 2001 Synopsys, Inc. (MF #15)
1996
1997
1998
1999
2000
2001
VHDL: back in the race with Scirocco VCS
Performance
Roadrunner Radiant
5.2 Scirocco
ASIC Sign-Off 5.0/5.1 Cycle & 2-State Language Optimizations 4.0 Native Code Compiled 2.0 Code
1.0 1993
1994
© 2001 Synopsys, Inc. (MF #16)
3.X
6.0
4.1/4.2
>
/ X 2
r a Ye
VHDL Simulators 1996
1997
1998
1999
2000
2001
Multi-Level Simulation Flow Verilog-A Models
SPICE Netlist
NanoSim
Simulation output
© 2001 Synopsys, Inc. (MF #17)
Verilog-D Netlist
VCS
Waveform Viewer
Simulation output
Design challenges IP and Systems Design
Services
IC Implementation
Verification and Test Signal Integrity Transistor Level Design
© 2001 Synopsys, Inc. (MF #18)
Crosstalk becoming a 1st-order problem Delay (ps) 70
Cu 1.7µΩ-cm Low κ===2.0 Line 43µ long .8µ=thick
60 50
Interconnect Delay due to Crosstalk
40 30
Interconnect Delay
20 10 650
500
© 2001 Synopsys, Inc. (MF #19)
350
250
180
150
100
70 ( nm)
Timing Analysis with Signal Integrity: PrimeTime-SI Static Crosstalk Analysis
•
Added to industry-leading PrimeTime
•
Crosstalk considered throughout design
• •
Physical Physical Synthesis Synthesis
Route Route
Integrated into proven flow Multi-million gate capacity & performance
© 2001 Synopsys, Inc. (MF #20)
Integrated Integrated Static Static Timing Timing & & Crosstalk Crosstalk Analysis Analysis
Design challenges HW/SW Complexity
IP and Systems Design
Services
IC Implementation
Verification and Test
Transistor Level Design © 2001 Synopsys, Inc. (MF #21)
HW/SW Complexity Growing 2000 EY
2007
Strategies to win
200 EY
– Design Re-Use
2001 20 EY
– System Level Design
1995 1M Gates
10M Gates
100M Gates
“To manage the complexity of our most advanced systems, it is necessary to explore all design options at the system level in a C-based design environment.” - Jouko Junkkari, VP of System Design, Nokia © 2001 Synopsys, Inc. (MF #22)
The NEW DesignWare Library Total IP Solution Star IP
MacroCells
Foundation Components
Eg . , ARM IPS C, M , MIP rP S, owe P ... …
M USB PEG2 , 805 2.0, P CI 1, P -X CI, 165 50, ...
Bus Interface Models (BIMs) t, rne
I-X, PC the A, E .0, , AMB 2 d B US iBan E1394 n I n fi I , I E E : PC >1 nts rs, e 4 n Ari e o thm 0 com mp ntroll ), o p C e o o t ,… 0 Flo Pipeli ics ( + nents ,00 rs, µC ltera s, 7 atin 1 ned : A o ie > gP Mu < < > > ess ilinx, emor… c o o l X r t *) ip FI F i nt , µP As ( als, mogic, JTA lier, O /F I FO FPG riphermon l G, L ro pe com ... CTL, FSR, mP e M
Imp lem ent atio n IP © 2001 Synopsys, Inc. (MF #23)
Bus-Functional Models (BFMs) M, AR
SmartModel® Library
IP n o ti a c i if r e V
SystemC: becoming the de-facto standard for Concept-to-RTL design Why SystemC is important – – –
System level design starts in C/C++ SystemC is a standard library for HW/SW modeling Rapid TTM demands a unified HW/SW co-design language
15,000 12,500 10,000
SystemC momentum 7,000+ individuals 500+ organizations
Synopsys strategy for System Level Design – Lead SystemC standardization – Provide best SystemC tools
7,500 5,000 2,500 0 S O N D J
1999 © 2001 Synopsys, Inc. (MF #24)
F M A M J
J
2000
A S O N D
Designing at the system level using SystemC CoCentric System Studio C/SystemC
Performance Exploration
HW/SW co-design
SystemC Execut. Specification
Chip verification
© 2001 Synopsys, Inc. (MF #25)
SystemC Synthesizable Model
CoCentric Chip synthesis SystemC Compiler
Processor Model
SW C-code
SW implementation
Design needs Services IP and Systems Design
Services
IC Implementation
Verification and Test
Transistor Level Design © 2001 Synopsys, Inc. (MF #26)
Synopsys Professional Services Tampere, Tampere, Finland Reading, England
Beaverton Mountain View Irvine
Dallas
Marlboro
Orlando
Aachen, Germany Munich, Germany Montpellier France
Austin
Tokyo, Japan Bangalore, Bangalore, India
Hsinchu, Hsinchu, Taiwan Singapore
• 350+ professionals in 16 major centers worldwide • Range of design services from concept to GDSII • Specialize in high gate-count, high-frequency SOCs • Expertise in wireless & broadband communications • Flexible engagement models © 2001 Synopsys, Inc. (MF #27)
= Engineering Center = Design Center
What do EDA customers say?
© 2001 Synopsys, Inc. (MF #28)
EE Times: Technology leader today Synopsys
28%
Cadence Design Systems
17%
Agilent Technologies
13% 9%
Mentor Graphics OrCAD
8% 6%
Avant! Corporation Synplicity
3%
PADS Software
3%
Viewlogic Systems
3% 0%
© 2001 Synopsys, Inc. (MF #29)
5%
Base = 180 10%
15%
20%
25%
30%
EE Times: Technology leader in 3 years Synopsys
24% 19%
Cadence Design Systems 14%
Agilent Technologies 10%
Mentor Graphics Avant! Corporation
8%
OrCAD
8% 4%
PADS Software Magma Design Automation 0% © 2001 Synopsys, Inc. (MF #30)
Base = 132
2% 5%
10%
15%
20%
25%
30%
The Design Technology Leader
©2001 Synopsys, Inc. (MF)
