THE ARMADEUS PROJECT
DATASHEET
APF9328 0C
31. July 2006
Disclaimer The informations in this manual have been carefully checked and are believed to be accurate. Armadeus assumes no responsibility for any inaccuracies that may be contained in this document. Armadeus makes no commitment to update or keep current the informations contained in this manual. Armadeus reserves the right to make improvements to this document and / or product at any time without notice. Armadeus shall not be responsible for any loss or damage caused to the user by the direct or indirect use of its products.
Warranty This product is supplied with a 1 year warranty. Product warranty covers failure caused by any manufacturing defects. Armadeus will make all reasonable effort to repair the product or replace it with an identical variant. Armadeus reserves the right to replace the returned product with an alternative part or an equivalent fit, form and functional product. Delivery charges will apply to all returned products.
Trademarks ARM is a registered trademark of ARM Ltd. IMX, MC9328MXL, MC9328MXS are registered trademarks of Freescale semiconductor DM9000 is a trademark of Davicom semiconductor. Spartan3 is a registered trademark of Xilinx Linux is a registered trademark of Linus Torvalds
File name: Last editing:
DataSheet_APF9328.sxw Jul 31, 2006 20:23:58
The Armadeus Project Edition
Date
Changes
Edition 0.A (PCB ed 1)
16. February 2006
Initial version
Edition 0.B (PCB ed 1)
10. July 2006
Add power consumption results.
Edition 0.C (PCB ed 1)
31. July 2006
Add APF picture
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Table of Contents Chapter 1: APF9328............................................................................................................6 1.1 1.2 1.3 1.4 1.5
Introduction..................................................................................................... 6 Part Number Descriptor.................................................................................... 7 Mechanical Overview........................................................................................ 7 APF9328 Features.............................................................................................8 Handling precautions....................................................................................... 9
Chapter 2: Hardware Description................................................................................... 10
2.1 Memory Mapping............................................................................................11
2.1.1 Translations made by the MMU......................................................................................... 11
2.2 MC9328 Processor......................................................................................... 12 2.2.1 Real Time Clock............................................................................................................... 2.2.2 Watchdog......................................................................................................................... 2.2.3 PWM................................................................................................................................. 2.2.4 TIMER.............................................................................................................................. 2.2.5 SPI................................................................................................................................... 2.2.6 SSI / I2S........................................................................................................................... 2.2.7 I2C................................................................................................................................... 2.2.8 UART............................................................................................................................... 2.2.9 USB.................................................................................................................................. 2.2.10 CSI................................................................................................................................. 2.2.11 MSHC............................................................................................................................. 2.2.12 MMC/SD........................................................................................................................ 2.2.13 LCD................................................................................................................................ 2.2.14 DMA.............................................................................................................................. 2.2.15 MMA.............................................................................................................................. 2.2.16 GPIO.............................................................................................................................. 2.2.17 RESET.............................................................................................................................
12 13 13 13 13 13 14 14 14 15 15 15 16 16 17 17 17
2.3 10/100Base TX Ethernet (optional)................................................................. 18 2.4 Spartan3 FPGA (optional)................................................................................ 18 2.5 AD / DA converters (optional)......................................................................... 18
2.5.1 Analog to Digital converter............................................................................................... 18 2.5.2 Digital to Analog converter............................................................................................... 19
2.6 Power Management........................................................................................ 19
2.6.1 Power estimations (3.3V supply)....................................................................................... 19
2.7 Electrical Characteristics................................................................................ 20 2.8 Connectors..................................................................................................... 20
2.8.1 Connector X1 (connector L).............................................................................................. 20 2.8.2 Connector X2 (Connector R )............................................................................................. 23
Chapter 3: Appendix......................................................................................................... 26 3.1 3.2 3.3 3.4
MC9328 Port / Pin Table................................................................................ 26 Spartan3 Port / Pin Table................................................................................ 28 Mechanical..................................................................................................... 30 References..................................................................................................... 31
3.4.1 3.4.2 3.4.3 3.4.4 3.4.5
APF9328
Freescale (www.freescale.com).......................................................................................... Davicom (www.davicom.com.tw)....................................................................................... Xilinx (www.xilinx.com).................................................................................................... Maxim (www.maxim-ic.com)............................................................................................ Philips (www.semiconductors.philips.com)........................................................................ 0C
31 31 31 31 31
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Chapter 1: APF9328 1.1 Introduction The APF9328 is an ultra low power single board computer based on the MC9328MXL/S ARM9 processors from Freescale. This board offers a wide range of features making it ideal for power sensitive embedded communications, controller and multimedia applications. Moreover, software packages (Uboot and Linux) are provided to reduce the development time. Two processors are supported: the MC9328MXL and the MC9328MXS. Both can be mounted on the same PCB. The only difference resides in the processor performances and the price. The MXS is the low cost version of both processors and can be an ideal choice for cost sensitive products. This document is based on the MC9328MXL version. Nevertheless we will use a common name for both processors: MC9328. In case of a MXS version, the differences have to be checked.
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1.2 Part Number Descriptor APF9328-S-MxFx-AEPx Processor speed: 100, 200 MHz
A: ADC/DAC E: 10/100 Base TX Ethernet Px: Spartan 3 FPGA with 50, 200 or 400k gates
SDRAM size: 8 or 16 Mbyte FLASH size: 4, 8 or 16Mbyte
The board is available in the following version: ► APF9328-200-M16F8-E: iMXL 200MHz, 16MByte SDRAM, 8MByte Flash with 10/100 Mbits Ethernet The non standard versions are only available in volume. Please contact Armadeus informations.
for more
1.3 Mechanical Overview Size: 71 mm x 39 mm ( 2.8” x 1.5” ) FLASH
MC9328
DC/DC
FPGA
Figure 1: mechanical overview
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1.4 APF9328 Features Microprocessor
ARM920T 200MHz RISC processor
Cache
16KByte program, 16KByte data
System memory
up to 16MByte 32bits SDRAM (96MHz) and 16MByte 16bits Flash
Video
LCD controller up to 640x512 (64K colors) CSI (CMOS sensor interface)
Serial ports
1x RS232 compatible (RX/TX) with on board transceiver 1 x RS232 with TTL levels (RX, TX, CTS, RTS) 1 x I2C 2 x SPI 1 x SSI (high speed synchronous serial port) USB 1.1 slave only
Network
10/100 Mbits
SD/MMC RTC PWM
16 bits resolution
Timer
2 x 32 bits with input capture/output compare
Watchdog
Adjustable timeout between 0.5s and 64s (0.5s step)
General purpose I/O (GPIO)
up to 90 x 3.3V compatible inputs/outputs
JTAG port
Debug (ICE) and test
Power
+3.3V ± 5%. Typically 300mW (without board options) Power management features allowing current requirements to be as low as 30mA.
Cooling
None for temperature below 45°C*.
Operating temperature range Storage temperature range Humidity MTBF
0..45°C* (without cooling) -10..70°C 5-90% 80 000 hours ( MIL-HDBK-217F with generic failure rates)
* FPGA not taken into account. Depending on IP used the cooling can be required and max temperature can be decreased.
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1.5 Handling precautions •
Anti-static handling
This board contains CMOS devices that could be damaged in the event of static electricity discharged through them. At all times, please observe anti-static precautions when handling the board. This includes storing the board in appropriate anti-static packaging and wearing a wrist strap when handling the board. •
Packaging
Please ensure that should a board need to be returned to Armadeus, it is adequately packed, preferably in the original packing material. •
Electromagnetic compatibility (EMC)
The APF9328 is classified as a component with regard to the European Community EMC regulations and it is the user responsibility to ensure that systems using the board are compliant with the appropriate EMC standards.
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Chapter 2: Hardware Description
USB
SDRAM
UART1
ETHERNET*
MC9328
Data / Address / CTRL
FLASH
ADC*
RS232 Transceiver
FPGA*
USB Transceiver
The following section provides a detailed description of the functions available on the APF9328.
RX/TX
CTS/RTS
UART2 TIMER/PWM SD/MMC
I2C SSI
DAC*
SPI
LCD CSI
* Optional
Figure 2: APF9328 block diagram
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2.1 Memory Mapping MC9328 Chip Select
Physical address
Width
Description
CSD0
0x08000000
32-bit
Reserved for internal SDRAM
-
reserved
16-bit
Reserved for internal Flash
16-bit
FPGA*
16-bit
Free
16-bit
Free
16-bit
Ethernet* (0x15C00000 – 0x15C00002)
0x0BFFFFFF CSD1
0x0C000000 0x0FFFFFFF
CS0
0x10000000 0x1FFFFFFF
CS1
0x12000000 0x12FFFFFF
CS2
0x13000000 0x13FFFFFF
CS3
0x14000000 0x14FFFFFF
CS4
0x15000000 0x15FFFFFF
CS5
otherwise Free
0x16000000
16-bit
Free
0x16FFFFFF * Optional.
2.1.1 Translations made by the MMU For details of translations made by the MMU under Linux, please refer to the APF9328 Software Manual.
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2.2 MC9328 Processor Two processors are available (same footprint, same pinout ). The MC9328MXS (up to 100MHz core frequency) is a reduced version of the MC9328MXL. The MC9328 is a low power ARM 9 RISC processor. It does not include a floating point unit but it contains a DSP co-processor to enhance multimedia / computational applications. It is driven by a standard 32.768kHz quartz which generates all the clocks within the device. The default run mode frequency is 200MHz (100MHz for the MXS) but this can be adjusted depending on the target system. The processor has two supply inputs. The core supply (1.85V) is generated on the APF9328 from the main +3.3V. A high efficiency DC/DC converter is used to reduce the overall power consumption. The I/O supply is taken directly from the main +3.3V. The MC9328 has an integrated memory controller supporting several kind of memories (SDRAM, Flash, SRAM). The 100MHz memory bus (adjustable) is 32bits wide for the SDRAM and 16bits for the Flash. The internal program and data cache are 16KByte both. The MC9328 provides up to 97 GPIO pins which can be configured (by the user) as standard GPIOs or alternate functions like I2C, SPI, SSI.... Details of the pin configurations are provided in the following section (MC9328 pin assignment).
The MC9328 also has the following features that can be used on the APF9328: • • • • •
Connectivity: MMC/SD, SPI1/SPI2, UART1/UART2, SSI, I2C, USB (slave), Memory Stick System control: JTAG, Bootstrap, Power control, PLL and DMA Standard system IO: GPIOs, PWM, Timer1/Timer2, RTC, watchdog Multimedia: multimedia accelerator (MMA), video port (CMOS sensor) Human Interface: LCD controller
For more informations please refer to the MC9328MXL and MC9328MXS reference manuals.
2.2.1 Real Time Clock One RTC is provided on the APF9328 with the following features: • • • • • • •
Full clock features: seconds, minutes, hours, and days Capable of counting up to 512 days Minute countdown timer with interrupt Programmable daily alarm with interrupt Sampling timer with interrupt Once-per-second, once-per-minute, once-per-hour, and once-per-day interrupts Interrupt generation for digitizer sampling or keyboard debouncing
This RTC must be used for power management events/timers as no battery backup is provided. If accurate and backuped Time/Date are required, an external RTC, connected on the I2C bus, has to be used.
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2.2.2 Watchdog The watchdog timer module of the APF9328L protects against system failures by providing a method of escaping from unexpected events or programming errors. Once activated, the timer must be serviced by software on a periodic basis. If servicing does not take place, the timer times out. Upon a time-out, the watchdog timer module either asserts a system reset signal or an interrupt request depending on software configuration. The APF9328 Watchdog Module features: • •
Programmable time out of 0.5 s to 64 s Resolution of 0.5 s
2.2.3 PWM The APF9328 PWM Module features: • •
4⋅ 16 FIFO to minimize interrupt overhead 16-bit resolution
It can be use to drive LCD backlight, motor or to generate melodies.
2.2.4 TIMER Two general purpose 32 bits timers are available. • • • •
Automatic interrupt generation Programmable timer input/output pins Input capture capability with programmable trigger edge Output compare with programmable mode
2.2.5 SPI Two Serial Peripheral Interfaces are available. SPI1 is used has primary SPI while SPI2 shares the LCD GPIOs. • • •
SPI 1is master/slave configurable, SPI 2 is master only Up to 16-bit programmable data transfer 8×16 FIFO for both Tx and Rx data
2.2.6 SSI / I2S The SSI is a full-duplex serial port that allows the APF9328L to communicate with a variety of serial devices. These serial devices include standard codecs, digital signal processors (DSPs), microprocessors, peripherals that implement the Motorola Serial Peripheral Interface (SPI), and popular industry audio codecs that implement the inter-IC sound bus standard (I2S). The SSI Module features: • •
Supports generic SSI interface for external audio chip or interprocessor communication Supports Philips standard Inter-IC Sound (I2S) bus for external digital audio chip interface
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2.2.7 I2C I2C is a two-wire bidirectional serial bus that provides a simple and efficient method of data exchange while minimizing the interconnection between devices. This bus is most suitable for applications requiring occasional communication between many devices in close proximity. The flexible I2C bus allows additional devices to be connected to the bus for expansion and system development. One I2C Module is available with the following features: • • • • • • • • • • • •
Support for Philips I2C-bus standard for external digital control Support for 3.3 V tolerant devices Multiple-master operation Software-programmable for 1 of 64 different serial clock frequencies Software-selectable acknowledge bit Interrupt-driven, byte-by-byte data transfer Arbitration-lost interrupt with automatic mode switching from master to slave Calling address identification interrupt Start and stop signal generation and detection Repeated START signal generation Acknowledge bit generation and detection Bus-busy detection
2.2.8 UART Two Universal Asynchronous Receiver / Transmitter are available. An on board transceiver allows connecting RX/TX of the UART1 directly to a RS232 port without external component (+/-15kV ESD protections). UART1 CTS/RTS and UART2 signals are TTL compliant only • • • • •
Support for serial data transmit/receive operation: 7 or 8 data bits, 1 or 2 stop bits, and programmable parity (even, odd, or none) Programmable baud rates up to 1.00 MHz 32-byte FIFO on Tx and 32 half-word FIFO on Rx that support autobaud IrDA 1.0 support
2.2.9 USB One USB 1.1 slave controller is available with the following features: • • • • • • • • • •
Compliant with Universal Serial Bus Specification, revision 1.1 Up to six logical endpoints. Support for isochronous communications pipes Frame match interrupt feature notifies the user when a specific USB frame occurs For DMA access, the maximum packet size for the isochronous endpoint is restricted by the FIFO size of the endpoint For programmed I/O, isochronous data packets range from 0 bytes to 1023 bytes Support for control, bulk, and interrupt pipes Packet sizes are limited to 8, 16, 32, or 64 bytes Maximum packet size depends on the FIFO size of the endpoint Full-speed (12 MHz) operation
An onboard tranceiver allows connecting the board to an USB master without external component. D+ and D- are although protected against ESD (+/-12kV). APF9328
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2.2.10 CSI The APF9328 CMOS Sensor Interface features: • • • • •
Configurable interface logic to support Motorola and other commonly available CMOS sensors 8bit data port for YCC, YUV, or Bayer-RGB data input 32 × 32 FIFO for storing image data that supports ARM920T processor data reads and DMA data burst transfers to system memory Single interrupt source to interrupt controller from maskable sensor interrupt sources: start of frame, FIFO full, and FIFO overrun Configurable master clock frequency output to sensor Statistic data generation for auto exposure (AE) and auto white balance (AWB) control of the camera
2.2.11 MSHC The APF9328 Memory Stick Host Controller features: • • • • • • • • • •
Integrated 8-byte (4-word) FIFO buffer for transmit and receive Integrated CRC circuit Support for internal or external serial clock source Integrated Serial Clock Divider DMA support; DMA request condition is selectable based on FIFO status Automatic command execution when an interrupt from the Memory Stick is detected (can be toggled on/off) RDY time-out period set by the number of serial clock cycles Interrupt output to the ARM920T core when a time-out occurs Two integrated general-purpose input pins for detecting Memory Stick insertion/extraction 16-bit host bus access (byte access not supported)
2.2.12 MMC/SD The Multimedia Card (MMC) is a universal low cost data storage and communication medium implemented as a hardware card with a simple control unit and a compact, easy-to-implement interface that is designed to cover a wide variety of applications such as electronic toys, organizers, PDAs, and smart phones. MMC communication is based on an advanced 7-pin serial bus designed to operate in a low voltage range at medium speed (20 Mbps). The Secure Digital Card (SD) is an evolution of the MMC with an additional 2 pins in the form factor that is specifically designed to meet the security, capacity, performance, and environmental requirements inherent in new audio and video consumer electronic devices. The physical form factor, pin assignment, and data transfer protocol are compatible with the MMC. The SD is composed of a memory card and an I/O card. The memory card includes a copyright protection mechanism that complies with the security requirements of the Secure Digital Music Initiative (SDMI) standard, and is faster and has a higher memory capacity. The I/O card combines high-speed data I/O with low-power consumption for mobile electronic devices. The Multimedia Card/Secure Digital Host Controller module (MMC/SD module) integrates MMC support with SD memory and I/O functions. The copyright protection mechanism employs mutual authentication and a new cipher algorithm, and is handled in software post-processing. The APF9328 MultiMediaCard and Secure Digital Host Controller features: • •
Compatible with the MultiMediaCard System Specification (SPI mode excluded), version 3.1 Compatible to 1/4 bit with the SD Memory Card Specification (SPI mode excluded), version 1.0 and SD I/O Specification (SPI mode excluded), version 1.0 with 1 or 4 channel(s)
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Up to ten MMC cards and one SD are supported by standard (maximum data rate with a maximum of ten cards) Support for hot swappable operation Support for data rates from 20 Mbps to 80 Mbps
2.2.13 LCD The Liquid Crystal Display Controller (LCDC) provides display data for external gray-scale or color LCD panels. The LCDC is capable of supporting black-and-white, gray-scale, passive-matrix color, and active-matrix color LCD panels. The APF9328 LCD Module features: • • • • • • • • • • • • • • • • •
Software programmable screen size (a maximum of 640 × 512 pixels) to support single (non-split) monochrome, color STN panels, and color TFT panels Support for 4 bpp (bits per pixel), 8 bpp and 12 bpp for passive color panels Support for 4 bpp, 8 bpp, 12 bpp and 16 bpp for TFT panels Up to 256 colors out of a palette of 4096 for 8 bpp True 64K color for 16 bpp In color STN mode, the maximum bit depth is 12 bpp In BW mode, the maximum bit depth is 4 bpp Up to 16 gray levels out of 16 palettes Capable of directly driving popular LCD drivers from manufacturers including Motorola, Sharp, Hitachi, and Toshiba Support for data bus width for 12- or 16-bit TFT panels Panel interface of 8-, 4-, and 2-bits, and a 1-bit wide LCD panel data bus for monochrome panels Direct interface to Sharp® 320 × 240 HR-TFT panel Support for logical operation between color hardware cursor and background Uses system memory as display memory LCD contrast control using 8-bit PWM Support for self-refresh LCD modules Hardware panning (soft horizontal scrolling)
2.2.14 DMA The Direct Memory Access Controller (DMAC) of the APF9328L provides eleven channels supporting linear memory, 2D memory, FIFO and end-of-burst enable FIFO transfers to provide support for a wide variety of DMA operations. The APF9328 DMA Module features: • • • • • • •
11 channels to support linear memory, 2D memory, FIFO, and End-of-Burst Enable FIFO for both source and destination Support for 8-, 16-, or 32-bit FIFO port size and memory port size data transfer Support for big-endian and little-endian Configurable DMA burst length for each channel up to 16 words, 32 half-words, or 64 bytes Bus utilization control for a channel that is not triggered by DMA requests Bulk data transfer complete or transfer error interrupts provided to interrupt handler (and then to the core) DMA burst time-out error terminates the DMA cycle when the burst cannot be completed within a programmed timing period
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2.2.15 MMA The APF9328 Multimedia Accelerator features: • •
MAC for FIR and FFT operation.MP3 applications save 10% to 15% CPU MIPS DCT/iDCT hardware accelerator.MPEG4 decode applications save approximately 10% CPU MIPS
2.2.16 GPIO Each GPIO can be configured as a standard Input/Output or connected to the MC9328 internal peripherals. • •
Interrupt capability (user programmable) 97 total I/O pins multiplexed with most dedicated functions for pin efficiency
2.2.17 RESET The APF9328 can be reseted by means of an active low signal (RESETN). Internal debouncing circuit prevents spurious reset of the board. If the main supply (+3.3V) falls below 2.88V, the board is automatically reseted.
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2.3 10/100Base TX Ethernet (optional) A Davicom DM9000 Ethernet controller provides a single 10/100BaseTX interface. The device features an embedded PHY and MAC, and complies with the IEEE802.3u 10/100BaseTX and IEEE802.3x Full-duplex Flow Control specifications. Configuration data and MAC information are stored in an external EEPROM (user programmable). The controller is directly connected to the MC9328 bus (see memory mapping) and uses the SSI1_RXFS pin has interrupt line. An external RJ45 connector with integrated isolation transformer is required (ie Pulse J0C-0005). External leds can be connected to provide link informations (like activity, status..).
2.4 Spartan3 FPGA (optional) The Spartan3 FPGA provides a highly flexible way to add new common or specialized peripherals to the board without adding new components. • • • • • • •
The APM9328 FPGA Module features: High Performance Xilinx FPGA up to 400K gates (50, 200 and 400k available) Several IO types including LVDS, High output current.... Direct communication with the APM9328 Processor (16bits 25MHz) Internal high speed RAM blocks Internal PLL Provides up to 59 user IOs
The FPGA is mapped on the CS1 (see memory mapping for details). The FPGA firmware is downloaded under control of the MC9328. The SSI1 lines (RX_CLK, TX_DAT, TX_CLK, RX_DAT and TX_FS) are used and can not be shared with other components. The MC9328 clock out signal is although connected to the FPGA and can be used as master clock input. The TIN signal (TIMER input) is used as FPGA interrupt. No external supply is necessary as two on board LDO regulators are provided for the core supply (+1.2V) and the aux supply (+2.5V)
2.5 AD / DA converters (optional) 2.5.1 Analog to Digital converter The APF9328 ADC Module features: • • • • • • •
Single Chip 8 inputs ADC (MAX1027) Resolution: 10 Bits 10MHz SPI compliant interface Internal reference Internal temperature sensor (+/-1°) Internal 16 entry FIFO Differential or single ended inputs
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Several modes (Scan mode, Internal averaging and clock mode)
As the ADC uses the SPI1 bus (MOSI, MISO, CLK and Ssn), an extra SPI chip select has to be configured to connect an other component on the bus. This new chip select can be a GPIO. It has to be noted that the ADC end of conversion signal is not connected to the SPI_RDY signal. Please refer to MAX1027 datasheet for more details.
2.5.2 Digital to Analog converter The APF9328 DAC Module features • • • •
Single chip Dual DACs ( MAX5821) Resolution: 10 Bits I2C 400kHz compliant interface Integrated output buffer Please refer to MAX5821 datasheet for more details.
2.6 Power Management The power management of the APF9328 offers the ability to disable the clocks of the different internal peripherals. By default, all clocks are enabled after reset. To reduce power consumption disable the clocks for any unused peripherals. The clock speed of the processor can although be changed to achieve a balance between performance and power consumption. Moreover, the peripherals like FPGA, ethernet controller can be switched off/on under control of the MC9328.
2.6.1 Power estimations (3.3V supply) APF9328 without Ethernet and FPGA: 60mA static, 100mA during memory copy,
