FDS6912 Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFET General Description
Features
These N-Channel Logic Level MOSFETs have been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers.
• 6 A, 30 V.
RDS(ON) = 0.028 Ω @ VGS = 10 V RDS(ON) = 0.042 Ω @ VGS = 4.5 V.
• Optimized for use in switching DC/DC converters with PWM controllers
These MOSFETs feature faster switching and lower gate charge than other MOSFETs with comparable RDS(ON) specifications.
• Very fast switching. • Low gate charge
The result is a MOSFET that is easy and safer to drive (even at very high frequencies), and DC/DC power supply designs with higher overall efficiency.
D1 D1
5
D2
6
D2
4 3
Q1
7
SO-8 S2
G2
S1
G1
Absolute Maximum Ratings Symbol
8
2 Q2
1
o
TA=25 C unless otherwise noted
Parameter
Ratings
Units
VDSS
Drain-Source Voltage
30
V
VGSS
Gate-Source Voltage
±25
V
ID
Drain Current
6
A
PD
Power Dissipation for Dual Operation
– Continuous
(Note 1a)
– Pulsed
20 2
Power Dissipation for Single Operation
TJ, Tstg
(Note 1a)
W
1.6
(Note 1b)
1
(Note 1c)
0.9 -55 to +150
°C
(Note 1a)
78
°C/W
(Note 1)
40
°C/W
Operating and Storage Junction Temperature Range
Thermal Characteristics RθJA
Thermal Resistance, Junction-to-Ambient
RθJC
Thermal Resistance, Junction-to-Case
Package Marking and Ordering Information Device Marking
Device
Reel Size
Tape width
Quantity
FDS6912
FDS6912
13’’
12mm
2500 units
2000 Fairchild Semiconductor Corporation
FDS6912 Rev F (W)
FDS6912
July 2000
Symbol
Parameter
TA = 25°C unless otherwise noted
Test Conditions
Min
VGS = 0 V, ID = 250 µA ID = 250 µA, Referenced to 25°C
30
Typ
Max Units
Off Characteristics BVDSS ∆BVDSS ∆TJ IDSS
Drain–Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current
VDS = 24 V,
IGSSF
Gate–Body Leakage, Forward
IGSSR
Gate–Body Leakage, Reverse
On Characteristics
V 20
mV/°C µA
VGS = 25 V,
VGS = 0 V TJ = 55°C VDS = 0 V
1 10 100
nA
VGS = –25 V
VDS = 0 V
–100
nA
2 –5
3
V mV/°C
0.024 0.034 0.035
0.028 0.048 0.042
Ω
(Note 2)
VDS = VGS, ID = 250 µA ID = 250 µA, Referenced to 25°C
VGS(th) ∆VGS(th) ∆TJ RDS(on)
Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static Drain–Source On–Resistance
VGS = 4.5 V,
ID = 6 A TJ = 125°C ID = 4.9 A
ID(on)
On–State Drain Current
VGS = 10 V,
VDS = 5 V
gFS
Forward Transconductance
VDS = 10 V,
ID = 6 A
VDS = 15 V, f = 1.0 MHz
V GS = 0 V,
VGS = 10 V,
1
20
A 20
S
Dynamic Characteristics Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Switching Characteristics td(on)
Turn–On Delay Time
tr
Turn–On Rise Time
td(off) tf Qg
Total Gate Charge
Qgs
Gate–Source Charge
Qgd
Gate–Drain Charge
740
pF
170
pF
75
pF
(Note 2)
8
16
ns
13
24
ns
Turn–Off Delay Time
18
29
ns
Turn–Off Fall Time
8
16
ns
7
10
nC
VDD = 15 V, VGS = 10 V,
VDS = 10 V, VGS = 5 V
ID = 1 A, RGEN = 6 Ω
ID = 6 A,
3.8
nC
2.5
nC
Drain–Source Diode Characteristics and Maximum Ratings IS
Maximum Continuous Drain–Source Diode Forward Current
VSD
Drain–Source Diode Forward Voltage
VGS = 0 V,
IS = 1.3 A
(Note 2)
0.75
1.3
A
1.2
V
Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
a) 78°/W when 2 mounted on a 0.5in pad of 2 oz copper
b) 125°/W when mounted on a 0.02 2 in pad of 2 oz copper
c) 135°/W when mounted on a minimum mounting pad.
Scale 1 : 1 on letter size paper 2.
Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
FDS6912 Rev E (W)
FDS6912
Electrical Characteristics
FDS6912
Typical Characteristics
30
VGS = 10V
2
6.0V 5.0V
4.5V
1.8 V GS = 4.0V
1.6 18
4.5V
1.4
4.0V
5.0V 12
1.2
3.5V
10V
1
6
3.0V
0.8 0
0 0
1
1 2 2 V DS, D RAIN-SOUR CE VOLTAGE (V)
3
20
30
50
Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 8
I = 3.0A
ID = 6.3A V GS =10V
D
7
R DS(ON) ,(OHM)
1.4 1.3 1.2 1.1 1.0 0.9
DRAIN-SOURCE ON-RESISTANCE
1.5
6
5
o
TA = 125 C 4
3
0.8 2
25 oC
0.7 0.6 -50
-25
0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C)
125
150
1 2
4 V
Figure 3. On-Resistance Variation withTemperature.
GS
6 ,GATE-SOURCE VOLTAGE (V)
8
10
Figure 4. On-Resistance Variation with Gate-to-Source Voltage.
20
100
VDS = 5V I D , DRAIN CURRENT (A)
40
ID, DRAIN CURRENT (A)
1.6 DRAIN-SOURCE ON-RESISTANCE
10
3
Figure 1. On-Region Characteristics.
R DS(ON) ,NORMALIZED
6.0V 7.0V
D
I , DRAIN-SOUR CE CURREN T (A)
24
TJ = -55°C
VGS = 0V
25°C 10
125°C
o
15
TA = 125 C 1 o
25 C 0.1
10
o
-55 C 0.01
5
0.001 0.0001
0
0 1
2 3 4 V GS , GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics.
0.4
0.8
1.2
1.6
5 V SD, BODY DIODE FORWARD VOLTAGE (V)
Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature.
FDS6912 Rev E (W)
FDS6912
Typical Characteristics (continued)
2000
10 ID = 6.3A
VDS = 5V
10V
CAPACITANCE (pF)
8 15V 6
4
2
500
C oss 200 80
0 0
4
8
12
C iss
1000
16
f = 1 MHz VGS = 0V 0.1
0.3
Figure 7. Gate Charge Characteristics.
100 us
IT LIM
30
1s
DS
ms
10 s DC
VGS = 10V SINGLE PULSE RθJA = 135 °C/W TA = 25°C 0.5 V
20
s POWER (W)
100
0.2
SINGLE PULSE R θJA= 135°C/W TA = 25°
25
1m s
0.5
15
10
5
1 2 5 10 , DRAIN-SOURCE VOLTAGE (V)
20
0
0.01
Figure 9. Maximum Safe Operating Area.
0.1
1 10 SINGLE PULSE TIME (SEC)
100
1000
Figure 10. Single Pulse Maximum Power Dissipation.
1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE
I D , DRAIN CURRENT (A)
N) S(O RD
2
0.01 0.1
10
30
10m
0.05
3
Figure 8. Capacitance Characteristics.
100
10
1
V DS , DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
20
C rss
0.5
D = 0.5
0.2
0.2
0.1 0.05 0.02 0.01
R θJA (t) = r(t) * R θJA R θJA = 135°C/W
0.1 0.05
P(pk)
0.02 0.01
t1
Single Pulse
0.005
Duty Cycle, D = t1 /t2
0.002 0.001 0.0001
t2
TJ - TA = P * R θJA (t)
0.001
0.01
0.1 t 1, TIME (sec)
1
10
100
300
Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1c. Transient thermal response will change depending on the circuit board design.
FDS6912 Rev E (W)
TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
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Advance Information
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This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
Preliminary
First Production
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No Identification Needed
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Rev. H4
