Explicit 2D Compact Model of Independent Double Gate MOSFET Reyboz Marina, Rozeau Olivier, Poiroux Thierry, Martin Patrick, Mickaël Cavelier
Jomaah Jalal IMEP/INPG Minatec Grenoble, FRANCE
CEA/LETI Minatec Grenoble, FRANCE Tel: +33 4 38 78 27 68 Fax: +33 4 38 78 90 73 e-mail:
[email protected]
Tel: +33 4 38 78 27 68 Fax: +33 4 38 78 90 73 e-mail:
[email protected] .
II Explicit Vth model for a long device Abstract - This paper describes an explicit 2D threshold
voltage based compact model of Independent Double Gate (IDG) MOSFET with undoped channel. The validity of this model is demonstrated by comparison with Atlas
Fig. 1 shows the device structure. L is the gate length, Tsi
simulations. The model was implemented in circuit
the silicon film thickness (10 nm), Tox1,2 the front and back
simulator in VerilogA language to design digital and analog circuits using the independent gate structures.
gate oxide thicknesses (1nm). Vg1,2 are the front and back gate voltages. Without generality loss, ∆Φm1,2 the work function differences between the front and the back gate and the
I Introduction
intrinsic silicon are supposed null.
Vg1 IDG MOSFET is a particularly promising device, which is expected for sub-32nm node. To take advantage of the second gate, which can be independently driven and to design new circuits, a compact model including Short Channel Effects (SCE) is crucial. For the first time, an explicit 2D compact model of IDG
-Tox1 0 Source T si Tsi+Tox2
MOSFET is presented. The model is a threshold-voltage (Vth)
Front Gate
L
Drain
Y
Back Gate
X
Vg2
based compact model. We first explain the compact model in
Fig. 1: An IDG MOSFET.
the case of a long transistor. Then, we show how short channel effects are added in the core of the model. Finally, the model is implemented in simulator in VerilogA language and validity
In [2], explicit drain current Ids is given as:
is demonstrated by confrontation with Atlas numerical
I ds = I ds1 + I ds 2
simulations [1]. I ds1 =
Vds1,eff W Vds1,eff µ Cox1 Vgt1,eff 1 − n1,eff ( ) 2 + 2 L V u gt1,eff t
I ds 2 =
W µ C ox 2 V gt 2,eff L
Vds 2,eff 1 − n2,eff Vds 2,eff 2 ( V + 2 u ) gt 2 ,eff t
(1) (2a) (2b)
Where W is the gate width, µ the mobility (assumed constant),
an explicit compact model, we assume that for the correction
ut the thermal voltage and, Coxj the front and the back gate
term, the current mainly flows in xmax, the maximum potential
oxide capacitances respectively. Index j is 1 or 2. Vgtj,eff
in the x direction and in ymin, the minimum potential in the y
represent the effective gate voltages. They unify weak and
direction. It is the point where the electron density is maximal.
strong inversion thanks to an analytical threshold voltage,
xmax and ymin are obtained when the respective derivative is
which takes into account the coupling between both front and
zero. Thus, we get the following explicit expression of Ids in
back interfaces. nj,eff are the effective coupling factors. Vdsj,eff
weak inversion:
correspond to the effective drain voltages. They allow a good modeling of the drain saturation voltage. All these parameters
W I ds = − µ q ni Tsi u t2 L
ψ ψ exp s1 − exp s 2 ut ut exp ∆ψ ( xmax , y min ) exp − Vds u (ψ s1 − ψ s 2 ) ut t
− 1
(5)
are analytical and explicit. x max
λ λ1 = arcsin 1 π π
III Explicit SCE model y min =
π L − b1 2 − c1 2 2 b1 c1 ch λ1 π L sh λ1
(6a)
b1 π L exp −1 λ1 c1 λ1 ln π b1 πL 1 - c exp − λ 1 1
(6b)
ψs1 and ψs2 are the front and the back gate surface potentials, 2D Poisson equation is analytically solved in weak inversion. The evanescent-mode analysis is used as in [3] to
derived considering the DG MOSFET as a capacitive divider. Thus,
get the channel potential distribution: ∆ψ (x max ,y min ) =
ψ ( x , y ) = ψ 1D ( x ) + ∆ψ (x, y) π π b 1 sh (L − y ) + c1 sh λ1 λ1 ∆ψ (x, y) = π sh L λ1
y cos π λ 1
(3a) x
πL sh λ1 πL 2 2 2b1c1ch − b1 − c1 λ1
(7)
Eq. (5) could be written as the sum of Ids1 and Ids2 with Idsj
(3b)
given by: I dsj
ψ1D(x) is the 1D surface potential and ∆ψ(x,y) the 2D correction term. λ1, b1 and c1 are given in [3]; we are in the same assumptions.
Vgj −Vthj ∆ψ ( xmax, y min ) n j ut ut
−Vds W = − µ n j coxj u t2 e ut − 1 e L
e
(8)
Vthj is the 1D threshold voltage and nj the 1D coupling factor. To include SCE in our compact model, we want to express Idsj
Consequently, the drain current for a short channel device
as:
in weak inversion is expressed as: V I ds = µWu t 1 − exp − ds ut
L 2 2 2.b1 .c1 cosh π − b1 − c1 λ λ1 cos arcsin 1 L π sinh π λn
∫
L
0
1 dy Tsi ψ ( x, y ) 2 q.n exp ∫−Tsi i u t dx 2
I dsj
−Vds Vgj −Vthj , sce W n u 2 ut = − µ n j coxj u t e − 1 e j , sce t L
(9)
(4)
Vds is the drain voltage, q the electronic charge and ni the intrinsic carrier concentration. Due the double integral, this expression can not be considered as explicit. In order to obtain
The 2D threshold voltages Vthj,sce and coupling factors nj,sce will be obtained by identification of (7) and (8). Then, expressions (10a, b, c, d and e) and (11) are obtained.
a=
0.018
2
Atlas simulation
(10a)
0.016
IDG Model
0.014
πL χ πL sh 2 − ch − 1 λ1 2 λ1 2
1 nj
−b+ ∆ 2a
(10b)
E g Vthj + V gj ' πL + Vds ch − 1 − b = χ 2 2 2 2 λ1 + + E V V E V V πL g thj gj ' gj ' 2 g − thj − + Vds ch − 1 + Vds c = −2 χ 2 2 2 2 2 λ1 Toxj Tsi 2 sin π 2λ1 tan π λ1 2λ1 χ= T sin π si T λ1 π 2Toxj si + Toxj 2 Toxj + Toxj ' sin π λ 1
(10c)
0.012
Ids (A)
Vthj ,sce = Vthj +
(10d)
0.01
Vg1 = Vg2=Vg
V
ds
0.008
0
(10e)
0
0.1
0.2
0.3
0.4
0.5
V + Vg 2 πL E ch − 2 g − th1,sce λ 2 2 1
0.8
0.9
1
1.1
1.2
voltage.
0.018
Atlas simulation IDG Model
0.014
Ids (A)
Vth1, sce + V g 2 Eg 2 + Vds − 2
0.7
Fig. 2: Drain current versus gate voltage for several drain
Vg1 = Vg2=Vg V
πL sh λ1
0.6
Vg (V)
0.012
1 + n1
0.2V
0.002
the front gate), so j’=2 (for the back one) and if j=2 then j’=1.
of
0.004
0.016
1 πL E g Vds Vth1, sce + V g 2 χ 1 − ch + − 2 2 λ1 2
0.0V to 1.2V
step
0.006
Eg is the energy gap. j’ represents the opposite gate: if j=1 (for
n1, sce =
from by
0.01
g
from
0.0V to 1.2V
by step
of
0.2V
0.008 0.006
(11)
0.004 0.002 0 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
Vds (V)
These 2D expressions are replaced in (2a) and (2b) to get a
Fig. 3: Drain current versus drain voltage for several gate voltages.
unified model. We also add an expression of the early voltage (BSIM like) to take into account the channel length modulation.
For the case when the gates are independently driven, results are exposed on Fig. 4 to 7 for a short channel device L=30nm (W=1µm). 10-04 2.5x10-4
IV Implementation and Results 10-06
2.0x10-4 Vg2 from 0.0V to 1.2V by step of 0.2V
Ids (A)
Ids (A)
10-08
1.5x10-4
10-10
This compact model was written in VerilogA to allow
1.0x10-4 10-12
simulations with Eldo (Mentor Graphics) or ADS (Agilent)
5.0x10-5 10-14
circuit simulators. Comparisons between Atlas and ADS simulations of Ids for the symmetrical case are shown in Fig. 2 and 3.
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0 1.1 1.2
Vg1 (V)
Fig. 4: Drain current versus front gate voltage for several back gate voltages at low drain voltage (Vds=5mV) in logarithmic and linear scales.
1.5x10-2
10-02
1.8x10-2
Vg1 from 0.0V to 1.2V by step of 0.2V 1.4x10-2
10-06 Ids (A)
Ids (A)
Vg2 from 0.0V to 1.2V by step of 0.2V
Gds (S)
10-04
1.0x10-2
1.0x10-2
10-08 10-10
5.0x10-3
6.0x10-3
0
10-12
0
2.0x10-3 10-14
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
0.1
0.2
0.3
0.4
0.5 0.6 0.7 Vds (V)
0.8
0.9
1
1.1
1.2
Fig. 8: Drain conductance versus Vds for several Vg1 at
Vg1 (V)
Fig. 5: Drain current versus Vg1 for several Vg2 at Vds=1.2V.
Vg2=0.0V.
This proves again the good accuracy of our new compact 5x10-3 Vg1 from 0.0V to 1.2V by step of 0.2V
model.
Ids (A)
4x10-3 3x10-3
V Conclusion
2x10-3 10-3 0 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
An explicit compact model of IDG MOSFET with SCE was presented. This new model was written in VerilogA and
Vds (V)
Fig. 6: Drain current versus Vds for several Vg1 at Vg2=0.0V.
implemented in Eldo and in ADS. Atlas and ADS simulations were confronted and prove the accuracy of our model. Not only the drain current model agrees very well with numerical
1.6x10-2
Ids (A)
Atlas simulations, but also the drain conductance.
Vg1 from 0.0V to 1.2V by step of 0.2V
1.2x10-2
8.0x10-3
4.0x10-3
References
0 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
Vds (V)
[1] ATLAS User’s Manual – Device Simulation Software, SILVACO
Fig. 7: Drain current versus Vds for several Vg1 at Vg2=1.2V. International Inc.
Our 2D compact model of IDG MOSFET agrees very well
[2] M. Reyboz, T. Poiroux, O. Rozeau, P. Martin and J. Jomaah,
with Atlas simulations. That proves the accuracy and the
“Explicit threshold voltage based compact model of independent
validity of this model.
double gate MOSFET”, NSTI Nanotech, WCM, 2006. [3] X. Liang and Y. Taur, “A 2-D analytical solution for SCEs in DG
Moreover, the drain conductance is compared to Atlas simulations in Fig. 8.
MOSFETs”, IEEE Transac. On Electron Devices, vol.51, n°8, 2004.
