Investigation on Defect Localization Techniques for Three-Dimensional (3D) Interconnects

CHALLENGES FOR THREE-DIMENSIONAL (3D) ICS AND SYSTEMS

WORKSHOP BOOKLET Toulouse Monday, November 28, 2011 - Tuesday, November 29, 2011

Investigation on Defect Localization Techniques for Three-Dimensional (3D) Interconnects

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Summary

Summary .................................................................................................................... 2 Workshop purpose ..................................................................................................... 3 Organizing Committee ................................................................................................ 4 Final Program ............................................................................................................. 5 Abstracts..................................................................................................................... 8 Technical sponsors ................................................................................................... 26 Buffet sponsors......................................................................................................... 27 Companies briefs ...................................................................................................... 28 Attendee list .............................................................................................................. 37 NOTES ..................................................................................................................... 40

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Workshop purpose

3D integration is a key new trend for microelectronics. At system level, it allows incredible heterogeneous System in Packages with sensors, power, analog, digital and wireless possibilities. For Integrated Circuit manufacturer, the third dimension gives opportunities to stack dies by using 3D interconnections with Through Silicon Vias. In order to fully benefit from these new technologies challenges have to be overcome. It comprises - Design (including design for test, design for manufacturing, design for reliability, design for failure analysis), - Manufacturing, - Electrical test, - Reliability test - Characterization and Reliability challenges - Failure analysis. The aim of this workshop is to mix skills coming from involved industries. Contributions on all these topics are welcome. A specific focus will be on characterization and analysis: - Sample preparation (chip access, repackaging, cross sectioning, ...) - Acoustic microscopy - Xray (2D, Computed Tomography) - Magnetic Microscopy - Time Domain Reflectometry - Thermal measurements, hot spot localization - Terahertz imaging - Holography, 3D optical - High resolution electron and ion microscopy (SEM, TEM, HIM, TOFSIMS) - Thermo mechanical simulation and measurements -… 3

Organizing Committee

Michael HERTL, INSIDIX – France Chee Lip GAN (Assoc Prof), NTU – Singapore Frank ALTMANN, Fraunhofer IWM Halle – Germany Matthias PETZOLD, Fraunhofer IWM Halle – Germany Olivier CREPEL, Freescale – France Philippe PERDU, CNES – France Bernd KRUGER, Infineon – Germany Jerome TOUZEL, Infineon – Germany Yves OUSTEN, IMS – France Fulvio INFANTE, Intraspec Technologies – France Suzel LAVAGNE, Thales – France Ingrid De Wolf, IMEC – Belgium

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Final Program

Monday, November 28th, starting at 9:00 Welcome - Introduction (Philippe Perdu, CNES) Tutorial 9:10-9:40 "System in Package - how to cope with increasing challenges?", W. Mack, Infineon 2 - Manufacturing (Chair Jerome Touzel, Infineon) 9:40-10:05 2-1 "Stacking of Known Good Rebuilt Wafer without TSV Applications to heterogeneous System in Package", C. Val, 3D+ 10:05-10:35 2-2 "Wafer-bond micro-void physical analysis", C. Cassidy, AMS Coffee break 11:00-11:40 2-3 "3D low profile Si-interposer using Integrated Passive Devices and Advanced Packaging Processes suitable for complex electronic micromodule applications ", S. Bellenger, IPDIA 11:40-12:10 2-4 "3D Integration developments & manufacturing offer @ CEA-LETI", D. Henry, CEA/LETI Lunch 3 - Reliability Test (Chair Ingrid DeWolf, IMEC) 13:10-13:35 3-1 "Reliability challenges of 3D stacked Ics", K. Croes IMEC 13:35-14:00 3-2 "Reliability of TSV interconnects in 3D-IC Electromigration voiding analysed through 3D-FIB-SEM", T. Frank, STM 14:00-14:25 3-3 "Sample preparation, tests and coupling of experimental and simulation results for the extraction of reliability's parameters of an interface of packages". X. Chauffleur, Insidix / Epsilon 14:25-14:50 3-4 "Wear out Analysis in Vertical DMOS Under Repetitive Short Circuit Testing", J. Rhayem, ON Semiconductor Coffee break

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4 - Non destructive techniques (I)(Chair Chee Lip Gan, NTU) 15:20-15:55 4-1 "Application of Micro CT for Non Destructive FA", M. Cason, ST 15:55-16:20 4-2 "Failure analysis with X-ray micro computed tomography: state-ofthe-art, limitations and future developments", P. Schütz, EMPA 16:20-16:45 4-3 "Contactless high resolution characterization of 3D current path in advanced SIP packages", F. Infante, Intraspec Technologies 16:45-17:10 4-4 "3D Current Path in Stacked Devices", K. Kor, NTU Coffee break 5 - Non destructive techniques (II)(Chair Franck ALTMANN, IWM) 17:40-18:05 5-1 "Advanced techniques for non destructive characterization of MEMS devices and packaging - case studies", J. Dhennin, Novamems 18:05-18:30 5-2 "Improved Inspection of Miniaturised Interconnections by Digital Xray Inspection and Computed Tomography", J. Lübbehüsen, GE 18:30-18:55 5-3 "Novel Non-Destructive Characterization of Metal to Metal Bonding Interface Methodology for 3D-IC", R. I Made, NTU 18:55-19:20 5-4 "SAM failure analysis using scanning acoustic microscopy for diagnostics of electronic devices and 3D system integration technologies", P. Czurratis, Peter Hoffrogge, Tepla PVA AS Wrap-up day 1 (Fulvio Infante) Buffet

Tuesday, November 29th, starting at 8:30 Welcome - Introduction (Jerome Touzel, Infineon) 6 - Electrical Test and Localization (I) (Chair Suzel Lavagne, Thales) 8:40-9:05 6-1 "3D Defect localization on System in Packages using Lock-in Thermographie", Ch. Schmidt, IWMH) 9:05-9:30 6-2 "Extension of Lock in thermography for thermal conductivity characterization and localisation of defects in depth", A. Porcher, Epsilon 9:30-9:55 6-3 "Use of Lock-In Thermography for non-destructive 3D Defect Localization on System in Package and Stacked-Die Technology", A. Reverdy Sector 9:55-10:20 6-4 "3D Localization by Lock-in Thermography", A. Loubaresse, STEricsson 6

10:20-11:50 Coffee, Poster & Discussion Corner Lunch 7 - Electrical Test and Localization (II)(chair Bernd KRUGER, Infineon) 12:50-13:30 7-1 "Electrical test challenges for 3D", E.J. Marinissen, IMEC 13:30-13:55 7-2 "New methodology to characterize packaging with acoustic microscopy", Y. Ousten, IMS 13:55-14:20 7-3 "Current Induced Failure Analysis of Ni-based Microinsert Interconnections for Flip Chip Die on Wafer Attachment.", D. Arias Sector/CEA-Leti Coffee break 8 - Sample Preparation and Failure Analysis (chair Fulvio Infante, Intraspec Technologies) 14:50-15:15 8-1 "3D failures: Identify and meet the challenge of the third axis", S. Lavagne, Thales 15:15-15:40 8-2 "Failure Analysis for eWLB-Packages - Strategy, Fail Mechanisms", B. Krueger, Infineon 15:40-16:15 8-3 "High throughput cross sectioning by plasma FIB and combined laser ablation", L. Kwakman, FEI 16:15-16:40 8-4 " Laser chip access in 3D ICs ", M. Lefevre, Digit Concept Wrap-up day 2 (Philippe Perdu, CNES) Lab Tour CNES

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Abstracts Tutorial "System in Package - how to cope with increasing challenges?" Walter Mack, Infineon Technologies, Wernerwerkstrasse 2, 93049, Regensburg, Germany A short summary will be given on challenges which electronic device industry faces in failure analysis and reliability assessment of System in Packages (SiP). In consequence the main trends are described how companies try to cope with the new requirements by further development of analytical instrumentation. Feasible approaches are shown how to drive tool development as well as what is needed to setup crucial expertise in semiconductor companies. 2-1 "Stacking of Known Good Rebuilt Wafer without TSV Applications to heterogeneous System in Package", Christian Val, Pascal Couderc , Nadia Boulay and Jérôme Noiray 641 rue Helene Boucher, 78532 BUC – Cedex, France We launched the 3D modules 20 years ago, first with Thales and then, from 1996 as 3D Plus. The 3D technologies named: Flow 1 and Flow 2 has been fully qualified by a lot of Agencies: CNES, ESA, NASA, JPL, JAXA, ISRO, CAST etc… The main steps qualified in Flows 1 & 2 are used with the Flow 3 named: Wirefree Die on Die (WDoD): Dicing Plating Direct laser patterning A technological break started on 2002, it consists in 20 to 30 reduction factor of the weight and volume of these new 3-D modules. The Z pitch is 100 µm and the XY size is given by the size of the larger die plus 100 µm of polymer around it. The Flow 3 allows to stack the Known Good Rebuilt wafers (KGRW) from 200 to 300 mm). The main advantages of the KGRW are: -Using of Known Good Rebuilt Wafers due to the fact that only the good die are taken by Pick and Place equipment to reconstitute a good wafer. The dice are placed on a sticky tape, then, a compression moulding with an epoxy resin allows to have a new wafer. After the removing of the sticky tape, a redistribution layer (RDL) allows to interconnect each pad from each die to the edges of each die. The RDL can have from 1 to 4conductive layers according to the complexity of the layout. -Using of any kind of components. The multisourcing die without TSV can be used. -Different sizes of the die can be used because the size of the stacked module will be given by the larger die plus 100 µm around it. - Several dice can be used on the same level; recently one ASIC plus 3 silicon capacitors were placed on the same level. - Known Good Burn-In wafers can be used among the Known Good Rebuilt Wafers. - The panelization allows to process all the 3-D modules together from the step A to the step Z, even the electrical tests. The status of the WDoD technology is: 8

- Technological qualification for medical applications like pacemaker made by Medtronic/USA in 2010. - Full JEDEC qualification is in process with a 4 high module DDR3 (800 MHz). The Rebuilt Wafer with the DDR3 has been made by Nanium/Portugal and 3D Plus stacked these wafers. The main applications will be presented: Camera for endoscopy, Hard X Ray camera, memories, MEMS and associated electronics, pacemaker (0,6 cm3), stacked thin film batteries, abandoned sensors. 2-2 "Wafer-bond micro-void physical analysis" C. Cassidy1, H. Plank2, T. Ganner2, L.G.W. Tvedt3, C. Gspan2, J. Wagner2, M. Krause4, C. Patzig4, J. Siegert1 1 austriamicrosystems AG, Tobelbaderstrasse 30, A-8141, Austria 2 FELMI-ZFE, Steyrergasse 17, A-8010 Graz, Austria 3 SINTEF ICT, Microsystems and Nanotechnology, Gaustadalleen 23C, 0373 OSLO, Norway 4 Fraunhofer-IWM, Walter-Hülse-Straße 1, 06120 Halle, Germany Wafer-bonding is an enabling technology for a variety of semiconductor industry segments (such as MEMS technology, 3D integration, and SOI). A comprehensive understanding of relevant defect modes and potential reliability weaknesses is a requisite ingredient in successful development of process technologies utilizing wafer-bonding. This article is concerned with investigations of local delamination within a wafer bond interface, detected after-bonding using scanning acoustic microscopy. With a specific physical mechanism giving rise to typical delamination diameters of ~100µm, such features have been referred to as micro-voids. Analysis challenges include the inaccessibility of the buried interface, enormous aspect ratios, and the difficulty in chasing sometimes elusive gas bubbles which vanish unpredictably during analysis. Two custom sample preparation approaches have been utilized to enable access to the surfaces and defects of interest, and a variety of material and surface analysis techniques have been leveraged to gain insight into the root cause behind the formation of such wafer-bond interfacial micro-voids. 2-3 "3D low profile Si-interposer using Integrated Passive Devices and Advanced Packaging Processes suitable for complex electronic micromodule applications" S.Bellenger , F.Murray, C. Bunel IPDIA, 2 rue de la Girafe, 14000 CAEN, France Thanks to their 3D structure, the Silicon Capacitors offer drastic improvements in terms of performances compared to the commonly used ceramic and tantalum capacitors. They are also a smart way to reduce the application volume and increase the IP protection level. With the increasing complexity in the die and package designs and ever increasing demand for footprint and volume reduction while the number of functionalities is increasing at the same time, in a cost-competitive daily pressure in today’s microelectronic industry, IPDIA is offering for a large range of products, customized or standard components, using its unique Passive Inter-Connective Substrate technology (IPD with ultra-high capacitor density values, very interesting 9

compromise between Q-factor/surface integration for self). Hardly addressing the heterogeneous 3D packaging challenge, IPDiA is using and extending PICS technology to 2D/3D interposer platforms, suitable for an heterogeneous packaging process between external ICs onto the interposer, with a very high routing density thanks to silicon design rules competitive advantage, and an additional vertical interconnection using through silicon via technology (TSV) for the 3D-interposer platform. With an industrial access of advanced packaging processes such as wafer thinning down to 80μm, wafer bumping (Ultra-fine pitch), various and complementary flip-chip processed (Within the most state-of-the-art solution for medical, industrial, space, avionic, lighting or mobile phone applications), this technology range is an interesting access for 2.5D and 3D technologies suitable for high integration density solution at the application module level. While wire-bond interface may remain the preference for many applications, face-down direct chip attachment has gained wide acceptance. More than interacting on electrical functionality, WLCSP is interacting on mechanical and thermo mechanical properties with a higher miniaturization and a transfer directly on printed circuit boards without additional packaging steps. This paper presents the main characteristics of the 3D Si-interposer with Passive Integration advanced technologies emphasizing on its capability and advantages versus discrete components illustrated by different applications. REFERENCES [1] P. Philippe, and A. Oruk, “A highly miniaturized 2.4 GHz Bluetooth radio utilizing an advanced System-in-Package technology,” European Microwave Week., Amsterdam, October 2004. [2] J.T.M. van Beek, M. van Delden, A. van Dijken, P. van Eerd, A.B.M. Jansman, A.L.A.M. Kemmeren, T.G.S.M. Rijks, P.G. Steeneken, J. den Toonder, M.J.E. Ulenaers, A. den Dekker, P. Lok, N. Pulsford, F. van Straten, L. van Teeffelen, J. de Coster and R. Puers, “High-Q integrated passives and RF-MEMS on silicon”, Mater. Res. Soc. Symp. Proc. 783 (2003) pp. 97-108 [3] F. Roozeboom, R. Elfrink, T.G.S.M. Rijks, J. Verhoeven, A. Kemmeren and J. van den Meerakker, “High-Density, Low-Loss MOS Capacitors for Integrated RF Decoupling”, Int. J. Microcircuits and Electronic Packaging, 24 (3) (2001) pp. 182196, and refs. therein. [4] F. Roozeboom, A. Kemmeren, J. Verhoeven, F. van den Heuvel, H. Kretschman and T. Frič, “High-Density, Lowloss MOS Decoupling Capacitors integrated in a GSM Power Amplifier”, Mat. Res. Soc. Symp. Proc. 783 (2003) pp. 157-162. [5] F. Roozeboom, A. Kammeren, J. Veroeven, F van der Heuvel, J. Klootwijk, H. Kretschmann, T. Fric, E van Grunsven, S. Bardy, C. Bunel, D. Chevrie, F. LeCornec, S. Ledain, F. Murray and P. Philippe, “More than Moore: Towards Passive and Si Based System-in-Package integration”, ISB Micro Conference, Florianopolis, Brazil, Sept 4-7, 2005, Invited Paper [6] L. Tiemeijer, R Havens, R. de Kort, Y. Bouttement, P. Deixler and M. Ryczek, “Predictive spiral inductor 2-4 "3D Integration developments & manufacturing offer @ CEA-LETI" David HENRY, CEA-Leti MINATEC Campus, 17 rue des Martyrs, 38054 GRENOBLE Cedex 9 Introduction 10

3D technologies have been considered at the laboratory level since a long time, using advanced chip stacking for very specific applications. In this field, CEA-Léti has been a very early developer of stacking and interconnection technologies. However, in the last few years, those technologies have gained a considerable interest from the industrial players of the microelectronic world. R&D centres are more and more approached to back the industrial developments with associated constraints of swift product development, prototyping, and short time-to-market. To face this paradigm, CEA-LETI has now developed a specific approach in the field of 3D integration, including a very advanced R&D part focused on the most promising technologies and integration flows, and the industrial validation of the most mature process flows already assessed at the laboratory scale or on specific industrial themes. 3D Integration R&D activities @ LETI In the first part of the presentation, the original R&D approach developed by LETI In order to answer to their customer’s requirements will be developed. This approach is based on the following three points:  The development at the process level, of a generic toolbox fitting the particular needs of the 3D integration developments.  The definition of a limited number of generic integration schemes covering the different targeted applications.  The setting up of dedicated 200 and 300mm 3D lines including the most suitable up-to-date tools to transfer to industrial partners the developed 3D technologies as swiftly as possible. In this presentation, some example of generic 3D processes and integration schemes specifically developed for 3D integration will be illustrated. A specific focus will be done on Through Silicon Vias (TSV) which is a very good example of 3D generic process developed by LETI and used for many applications and customers. Industrial applications example will be also shown in this presentation, like TSV for Cmos Image sensors, components partitioning and 3D IC’s applications. Prototyping activities: Open 3D platform In the second part of the presentation, the Open 3D™ structure will be presented. Open 3D is a new platform started by LETI in April 2011. The concept is to offer to industrial or academics partners, 3D innovative technologies for their advanced products. With few elements coming from the customer, Open 3D™ proposes a global offer, including 3D design, layout, technologies, reliability tests and final packaging for components or systems achievement. It’s possible, for the customer, to achieve proof of concept with a small quantity of wafers but also to make prototyping in small volume with R&D effort limitation. This offer is based on limited mature technologies, previously developed in the LETI R&D activities. Open 3D™ is now fully operational for 200 mm wafers and will be operational in 2012 for 300 mm wafers. Those technologies are operated on Minatec Campus @ Grenoble, by the LETI technological platforms and teams . The today’s technological catalogue is including the following modules :  Through Silicon Vias (TSV) with aspect ratios from 1:1 to 1:3  Interconnections  Redistribution layers (RDL)  Under bump metallurgy (UBM)  Temporary bonding, thinning and debonding  Components stacking and underfilling .

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The catalogue will be regularly enriched with new technological modules, corresponding to new 3D mature technologies and customer requirements. 3-1 "Reliability challenges of 3D stacked Ics" Kristof Croes and Ingrid De Wolf Imec, Kapeldreef 75, 3001-Heverlee [email protected] 3D integration using 3D-Stacked IC’s induce unknown reliability issues related to TSV-integration, wafer thinning processes and the stacking of these thinned chips. In this presentation, various reliability related challenges encountered in imec during the development of the 3D-SIC process will be discussed. Amongst others, these include: - Methods to quantify and suppress copper pumping. - Methods to study stresses induced in the silicon by the TSV. - Effect of wafer thinning on FEOL performance. - CuSn micro-bumps reliability in bump-sizes down to 40µm pitch 3-2 "Reliability of TSV interconnects in 3D-IC Electromigration voiding analysed through 3D-FIB-SEM" Thomas FRANK 1,3, Cédrick CHAPPAZ 1, Patrick LEDUC 2, Lucile ARNAUD 1,2, Stéphane MOREAU 2, Aurélie THUAIRE 2, Frédéric LORUT 1, Lorena ANGHEL 3 1 : STMicroelectronics – 850, rue Jean Monnet – 38926 Crolles cedex – France 2 : CEA-LETI/MINATEC – 17, rue des Martyrs – 38054 Grenoble cedex 9 – France 3 : TIMA – 45, avenue Félix Viallet – 38031 GRENOBLE Cedex – France 3D integration is today one of the most promising solution to achieve high density connections, getting around limits of CMOS scaling. An essential element of it, Through Silicon Via (TSV) enables dice to be connected through a vertical stack. Nowadays as TSV processes become mature, it is essential to analyse the reliability of theses interconnections. Electromigration (EM), a major reliability concern of interconnects, is an atomic flow (in our case copper atoms) driven by the electrons and enhanced by temperature. Any divergence (e.g. barrier, diffusion gradient) leads to a void nucleation and growth, and to interconnect opening. In this presentation we perform accelerated electromigration stress at package level on structure made of a copper damascene line ended by a copper via-last TSV of 2.3 μm diameter and 15 μm height. The interface between TSV and bottom metal level (MBOT) is fully characterized through TEM analysis. To achieve a comprehensive picture of the electromigration void nucleation and growth kinetic, 3D FIB SEM is performed on samples at beginning of stress and after failure. In this case, high resolution Scanning Electron Imaging is performed during cross section Focused Ion Beam (FIB) process. It enables to acquire several SEM image slices a few nanometer thick. Finally reconstructed 3D images, reveal that the electromigration void, less than 100 nm thick after 4 hours at 300 °C and 25 mA, growth right under the TSV. Question: Concerning 3D-IC reliability, failure analyses are necessary to understand completely the wear-out mechanism. Very large volume of matter have to be etched to enable high quality SEM or TEM pictures, but they are highly time consuming. Are 12

they today solutions to reduce analysis time? Is it even possible to get rid of etching by using non destructive and high resolution analyses? [1] T. Frank, et al., IEEE-EPTC, 2010, p. 321-324 [2] T. Frank, et al., IEEE-IRPS, 2011, p. 3F.4.1-3F.4.6 3-3 "Sample preparation, tests and coupling of experimental and simulation results for the extraction of reliability's parameters of an interface of packages" Diane Weidmann1, Michael Hertl1, Xavier Chauffleur2, Guillaume Dubois2 1 Insidix, 24 rue du Drac, 38130 Seyssins, France 2 Epsilon, Technoparc 10 – 10 rue Jean Bart, 31674 Labège France Works on predictive reliability of packages of electronic components are mostly dedicated on the failure of solder joints as structural material. The failure of interfaces, as links between two materials, is often neglected in the process of the failure or is confused with failure of material. Indeed, modelling is more and more difficult in electronics because of the number of materials, the geometry of all components, unknown manufacturing steps, not wellknown material parameters, etc. Additionally, in most cases, simulation does not take into account the mechanical stresses induced during the manufacturing process, although measurements show that electronic components are not flat after fabrication. Inside Pidea Full Control project, one subject was to find out a way to improve the accuracy of modelling to have more realistic prediction of electronic assemblies lifetime behaviour. We have worked on this subject and set up a methodology that can be used at early stages of product development and qualification process. The paper will present the work done. The first step consists of thermo-mechanical simulations to define needed samples. Once samples are selected and prepared, measurements are realized at several states of stresses of the samples:  Scanning Acoustic Microscopy for evaluation of interface delamination,  Topography and Deformation Measurements for deformed shapes at different temperatures (up to 260°C in that case). Dynamic Mechanical Analyses are also realized to determine classical material parameters. The advantage of the proposed approach is that unknown parameters like polymer shrinkage due to polymerization or strength of interface can be adjusted by matching experimental and modelling results. Another main advantage of our approach is that it can be applied not only to samples built in laboratories but also to commercial components coming from massive manufacturing. 3-4 "Wear out Analysis in Vertical DMOS Under Repetitive Short Circuit Testing" J. Rhayem, L. Vander Voorde, A. Wieers, M. Heer*, D. Pogany* ON Semiconductor Belgium BVBA, Westerring 15, B-9700 Oudenaarde, Belgium *Institute for Solid State Electronics, Vienna University of Technology, Floragasse 7, 1040 Vienna, Austria The objective of this contribution is to present analysis of a wear out problem due to hotspots during repetitive short circuit test [1] detected on the output drivers using 13

integrated vertical high voltage DMOS transistors [2]. The driver has three levels of thin metal and one level of thick top metal. A cross section and layout view of the DMOS device and the driver are presented in Fig. 1. The driver is a high side output that drives LEDs or incandescent bulbs (up to 10W). The chip is packaged SSOP-36 and mounted on PCBs, see Fig. 3a. During the in-rush current of the lamp, a peak power of 42W is dissipated in the driver (current is limited at 3A and the supply voltage is at 14V). The driver is activated for 300ms (one stress-cycle) and the builtin current limitation turns the output on and off with a frequency of 1.7kHz and a duty cycle of 25%. After each stress-cycle the driver cools for 8s. Some of the tested devices fail during 100K cycles of short circuit reliability testing. Cracks and deformation of the third metalization layer have been observed, see Fig. 2. The failure is attributed to the high temperature-cycling and according shear force in the metalization layers of the chip. The IR thermography of the silicon substrate shows inhomogeneous temperature distribution over the driver due to the mirrored thermal heat at the edge die-package, see Fig. 3b. In order to check the internal substrate temperature in the driver with high lateral resolution the transient interferometric mapping (TIM) method is used [4]. Fig. 4a identifies accurately the location of the weakest point in the driver where the cracks have been observed during the reliability tests. To verify the current distribution over the DMOS blocks and along their fingers, the dissipated power is evaluated from the TIM data. Fig. 4c shows slightly lower power dissipation at the hotter DMOS blocks on the right side. This confirms the (safe) operation of the DMOS transistors above the temperature compensation point (higher temperature leads to less local current and therefore less local power). Therefore, the reliability problem seems to be related only to the metal layers and not to the silicon side of the DMOS blocks. In order to predict the formation of hotspots with electro-thermal simulations, the driver has been segmented into unit cells which allow to model the nonhomogeneous power and temperature distributions. 3D Transient electro thermal simulation, using the methodology presented in [3], has been performed and is presented in Fig. 4d. The simulated peak temperature is obtained close to the observed damage. 4-1 "Application of Micro CT for Non Destructive FA", M. Cason, ST Morgan Cason, STMicroelectronics, Via C. Olivetti, 2 - 20864 Agrate - Italy Acceleration of innovation in the semiconductor industry is nearing the limits of CMOS scaling and can no longer keep pace with the rate of Moore’s Law. To continue meeting consumer demand for smaller, faster devices with low power requirements, the industry has turned to innovating with 3D packaging architecture. Hence, there has been a recent trend of new complex packaging architectures. Additionally, the introduction of new semiconductor package materials, such as leadfree solder, has resulted in new types of failure mechanisms. All these factors together have increased the difficulty of solving failures through conventional 14

techniques. This paper describes applying Micro CT as a solution for improving the efficiency of Failure Analysis. Several solutions currently exist on the market for non-destructive semiconductor failure analysis. Methods such as thermal imaging, acoustic imaging, and electrical testing have proven to be invaluable tools for the Fault Isolation steps in the FA flow. However, the push toward more layers in 3D integration and reduced feature sizes reduces the capability of each. Thermal diffusion will limit thermal imaging’s ability to observe faults farther below the surface. In both acoustic imaging and electrical testing, layers can cause the reflection of signals and generate noise to reduce their ability to accurately isolate failures. Fault isolation Physical Analysis can also be performed destructively by focused ion beam (FIB)-enabled scanning electron microscopes (SEMs). This FIB/SEM technique first uses FIB to destructively remove layers of material, cross-section the area of interest identified by Fault Isolation, and then use SEM to image the remaining area. Due to the extremely long sample preparation times, the Fault Isolation must be as accurate as possible in order to maximize the efficiency of the work flow. Without more accurate localization of the failures, Fault Analysts risk wasting valuable time searching for the failure. Moreover, critical failure information could be lost through the destruction of the sample. Several of the critical drawbacks to existing techniques, including the low resolution of non-destructive techniques and the destructiveness and slow speed of FIB/SEM, can be resolved by using microCT as a complementary technique. In this the paper, we describe examples of the use of MicroCT following TDR as non-destructive technique to isolate solderability and bump void failure mechanisms. Also, use of MicroCT for package construction analysis will be described. 4-2 "Failure analysis with X-ray micro computed tomography: state-of-the-art, limitations and future developments” Philipp Schuetz , Iwan Jerjen, Peter Jacob Empa, Swiss Federal Laboratories for Materials Science and Technology, Ueberlandstrasse 129,CH-8600 Duebendorf, Switzerland X-ray micro computed tomography (micro CT) is a powerful tool for investigating failures in micro electronics: A spatial resolution of about one micrometer allows visualizing small structures, like bond wires, ball grid arrays and vias. Failures like cracks, voids, missing or bad connections and alignment errors can easily be detected. However, the quality of micro CT images of microelectronics is severely compromised by artefacts caused by gold wires, soldering joints and other metallic components. Furthermore, non-destructive testing of structures made of Si, SiO2, Al and plastics is limited due to the weak contrast between light materials. By means of a case study, we will show which failure types can be investigated with a state-of-the-art micro CT instrument. Then, we will explain the fundamental limitations of micro CT and illustrate it with some examples. Finally, we will give an outlook about future developments in micro CT, e.g. differential phase contrast (DPC) micro CT and nano CT. DPC micro CT increases the contrast of light materials in CT images of microelectronic components by measuring the refractive index. Dark-field imaging with a DPC CT setup as well as nano CT by means of compact refractive lenses will enable to inspect failures at nanometer scale. 15

What should be the specifications of an ideal tool for investigating three-dimensional integrated circuits?" 4-3 "Contactless high resolution characterization of 3D current path in advanced SIP packages" Fulvio Infante1, Philippe Perdu2 1 INTRASPEC TECHNOLOGIES, 2CNES INTRASPEC TECHNOLOGIES, 29, Rue Jeanne Marvig – 31400 Toulouse, France INTRODUCTION The packaging technologies for the microelectronics industry have been greatly developed during the last decades: new solutions were searched in order to develop the structures along the three geometrical axes, making the new components fully three-dimensional [1]. At the beginning of this century, we noticed that it can already be seen a shift in the research from a System on Chip (SoC) approach to a System in Package (SiP) one [2]: the difference is substantially the presence of a full system on a single die (SoC), or the cohabitation of more dies, with different types of functions, in the same package (SiP). When we look at Moore's law, we can see that the physical limits are approaching very fast, and the up-to-date needs of the technology industry, mostly targeting the portable devices, are not met by the "standard" devices[3][4]. The new trend, which has been called "More than Moore", in contraposition to the "More Moore" line of development which tends to follow Moore's law, is expected to increase in the share of market very soon, due to the use of electronics in a wider and wider range of applications[5]. The new electronic objects are therefore more and more complex. With the increase of the packaging complexity, the number of possible defects at assembly level has increased exponentially. More and more often, the bigger reliability issue is due to the presence of assembly defects. A full analysis of these is therefore often requested, but there is almost no technique available on the market which is able to precisely localize defects for these objects in a non-destructive way. MAGNETIC MICROSCOPY In this paper we will present the new developments of the Magnetic Microscopy technique for failure localization[6]. The localization is performed in a non destructive way thanks to the use of the property of the magnetic fields which are not blocked by standard packaging materials. In addition, thanks to the implementation of a certain number of post-treatment tools, such as simulations[7], it is possible to precisely localize the defects at package level even on the up-to-date packaging technologies. The development of 3D techniques can be divided into two different axes, taking into large and small components packages. The standard SiP, in fact, is developed in a way where the dimensions of the final package are usually bigger than those of standard ones. In this case, the challenge for the failure localization is to acquire information from a long ”working distance”, as the defects might be deeply buried inside the package. However, the new trends are for the stacking of more dies inside the same package, as in the Through Silicon Vias (TSV) technologies. In this case, the working distance is not necessarily very high; however, an higher localization resolution is needed, as the dies are very close to each other. We will show how we contributed to the advances through the solution of the challenges related to these two axes: they can in fact be linked to each other by the 16

use of a simulation model which is scalable, and which can therefore be applicable for both cases. The results obtained on a certain number of case studies, together with the perspective of future developments will then be shown. REFERENCES [1] Al-sarawi SF, Abbott D, Franzon PD. “A Review of 3-D Packaging Technology”, IEEE Transactions on Components, Packaging and Manufacturing Technologies, February 1998; part B, vol. 2, no.1, p. 2-14. [2] Goldstein, H. “Packages go vertical”. IEEE Spectrum, August 2001; p.46-51. [3] Tummala RR, Swaminathan M, Tentzeris MM, Laskar J, Chang GK, Sitaraman S, et al. “The SOP for Miniaturized, Mixed-Signal Computing, Communication, and Consumer Systems of the Next Decade”. Transactions on advanced packaging, IEEE, vol. 27, no. 2, May 2004; p.250-267. [4] Tummala RR. “Moore's law meets its match”. IEEE Spectrum, June 2006; p.4449. [5] Zhang GQ, Graef M, van Roosmalen F. “The Rationale and Paradigm of "More than Moore"”. Proceedings of 56th Electronic Components and Technology Conference, IEEE, 2006; p.151-157. [6] Knauss LA, Cawthorne AB, Lettsome N, Kelly S, Chatrephorn S, Fleet EF, et al. “Scanning SQUID Microscopy for Current Imaging”. Microelectronics Reliability no. 41, February 2001; p.1211-1229. [7] Infante F, Perdu P, Petremont S, Lewis D. “A new methodology for short circuit localization on Integrated Circuits using Magnetic Microscopy Techniques coupled with simulations”. Proceedings of 16th IPFA, 2009 4-4 "3D Current Path in Stacked Devices" Katherine KOR, School of Materials & Engineering, Nanyang Technological University N4.1-B4-09, 50 Nanyang Avenue, Singapore 639798 “More than Moore” trend has triggered a lot of vertical integration for heterogeneous technologies such as System in Packages (SiPs), passive components embedded in printed circuit boards (PCBs), 3D stacked die/package technologies, through Silicon vias (TSVs) etc.. These new technologies are important in microelectronics in terms of their reliability and performance. However, the introduction of these new technologies presents new challenges in fault isolation and failure analysis. Main issues in defect localization could comprise short circuits, open circuits or intermittent failure. Several non-destructive techniques that are able to overcome some of the issues described above and are of increasing interest in the research are magnetic current imaging (MCI), 3D X-ray computed tomography (CT) and time domain reflectometry (TDR). Although magnetic current imaging (MCI) is useful in fault isolation of devices with 2D current distributions, MCI alone cannot give the exact information of current paths in complex 3D stacked devices. Previous work has demonstrated the ability of a simulation approach to find a short circuit in 3D geometry. This approach has been challenged in the case of dense and complex 3D current paths. In this project, the aim is to demonstrate how we can overcome this issue by using a new simulation approach instead of the previous segment by segment approach. The new approach has been validated on a complex chip with daisy chains vertically connected by vias. From the study of the simulation of three hypothesized current paths of various 17

current lines of interest, excluding and including the interactions with neighbouring current lines (both locally and globally), it was found that interactions of a current line with its global neighbours have very important effects, compared to no interactions or only interactions with local neighbours. By simulating all the currents, it was possible to minimize the error given by the presence of several current lines in a small volume. 5-1 "Advanced techniques for non destructive characterization of MEMS devices and packaging - case studies" Jeremie Dhennin, Djemel Lellouchi NOVA MEMS, 10, avenue de l’Europe, 31520 Ramonville Saint-Agne The author’s contribution will be focused on the new challenges which stem from the particular domain of MEMS devices characterization. Two different parts will be developed in the presentation, the first one being a collection of case studies dealing with the benefits of 3D X-ray tomography for failure analysis and characterization of those devices. A particular attention will be paid to highlight the high level information provided by this technique on the sensitive parts of the components. The sealing ring homogeneity, vias filling, correct release of the suspended parts, failure analysis for stiction can be studied easily and in a non destructive way thanks to X-ray tomography. The second part of the talk will be dedicated to the presentation of hermeticity issues on MEMS devices, and to the different approaches that have been developed to characterize this parameter. When the standard helium leak test shows its limit for ultra small packages (less than few mm3), new techniques have demonstrated a high relevance level and high accuracy. Optical detection thanks to membrane deflection is one of the most interesting method, that can be well complemented by other less known techniques such as Infra-red spectroscopy. 5-2 "Improved Inspection of Miniaturised Interconnections by Digital X-ray Inspection and Computed Tomography" Jens Lübbehüsen3, Thomas Hemberger1, Holger Roth2, Tobias Neubrand3 and Thomas Mayer3 1 GE Inspection Technologies SCS, 68 Chemin des Ormeaux, 69578 Limonest Cedex, France, Tel.: +33 472 179 249, Fax: +33 478 475 698, [email protected] 2 GE Sensing & Inspection Technologies GmbH, Kranstr. 8, 70499 Stuttgart, Germany, Tel.: +49 711 88 79 61 23, Fax: +49 711 88 79 61 29, [email protected] 3 GE Sensing & Inspection Technologies GmbH, Niels-Bohr-Str. 7, 31515 Wunstorf, Germany Tel.: +49 5031 172 133, Fax: +49 5031 172 299, [email protected] Microfocus X-ray inspection of classical package features such bond wires, die bonds, mouldings and seals is a proven tool for spot checks and production control. Package miniaturisation lead to higher density and smaller size of internal structures such as microvias and FlipChip interconnections, demanding for resolution in the sub-micron range at extremely high magnification as provided by nanofocus tube technology. 18

Currently further miniaturisation in electronics beyond Moore’s law demands for higher package complexity, i.e. system integration, leading to 3D-integrated devices including stacked or multiple dies with corresponding miniaturized interconnections, interposers, etc. The conventional 2D X-ray inspection of such devices frequently will be affected by confusingly overlapping structures, if they can be imaged at all. This is to say, 3D integrated devices or systems require non-destructive inspection slice by slice or in 3D visualisations as provided by computed tomography (CT). However, until recently, many laboratory CT systems are using X-ray tubes of some microns focal spot size and maximum tube voltages around 100 kV. Since electronic devices contain very fine structures and strongly absorbing materials like gold or copper this results in unsatisfying image resolution and strong image artifacts, respectively. Nanofocus and microfocus CT have been successfully applied to copper bond wires, microvias and flip chip interconnections. In our presentation we will show results for the 50-60 µm microvias of an defective embedded chip package. The microvias were inspected non-destructively by both highly resolving microfocus computed tomography and improved digital X-ray imaging. Voids were found within the via fills and open interconnections between vias and pads were detected by the X-ray inspections. These defects could be verified and visualised in three dimensions by nanofocus CT. Further, Trough Silicon Vias (TSV, about 100 µm in diameter) as used in 3D integrated electronic packages were inspected non-destructively by highly resolving nanofocus computed tomography (nanoCT). In particular, voids in the TSVs plating were visualised and quantitatively evaluated by numerical processing of the resulting volumetric data. The nanoCT technology is outlined and further applications such as interposers etc. are considered. 5-3 "Novel Non-Destructive Characterization of Metal to Metal Bonding Interface Methodology for 3D-IC" Riko I MADE, Chee Lip GAN School of Materials Science & Engineering, Nanyang Technological University (NTU) Advanced Materials for Micro- and Nano-Systems, Singapore MIT Alliance (SMA) Mechanical testing to assess the bond quality of bonded processed wafers can be very costly, particularly on production wafers which have multilayer devices designed in the chips. A new non-destructive characterization method based on measured resonance frequency is proposed. Capacitive and resistive characteristics of the contact interface are amplified and utilized with a designed external circuit that consists of an inductor and a resistor. This new measurement technique shows an improvement in sensitivity as compared to contact resistance measurement, as well as eliminates stray resistance effect from line resistance and probing contact resistance. 5-4 "SAM failure analysis using scanning acoustic microscopy for diagnostics of electronic devices and 3D system integration technologies" Peter Czurratis2), Frank Altmann1), Sebastian Brand1), Matthias Petzold1) Peter Hoffrogge2) 1 ) Fraunhofer Institute for Mechanics of Materials IWM Walter-Hülse-Straße 1, 06120 Halle (Saale), Germany 19

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) PVA Tepla Analytical Systems GmbH, Deutschordenstrasse 38, 73463 Westhausen, Germany New semiconductor chip technologies and technologies for 3D integration require information’s of packaging and interface defects in 3 dimensions, that means the lateral dimension of the defect and the location inside the device or package must be defined. In this paper, new methodical approaches for non destructive failure analysis on 3D integrated TSV samples are introduced. The concepts combine improved scanning acoustic microscopy (SAM) imaging hardware with unique software solutions for defect identification and quantitative analysis of mechanical properties using scanning acoustic investigations. In case of MEMS 3D integration, e.g. based on direct bonding, related interface defects must be investigated by SAM. With respect to 3D integration applications, the potential of recent SAM improvements applying specifically adapted hardware and custom-made signal processing algorithms will be discussed. Examples of SAM-based failure detection techniques for the application in 3D integration are demonstrated. New technologies are shown to improve the through put of fully wafer scanning using scanning acoustic microscopy. To improve the defect resolution, a new transducer design was developed to increase defect resolution and signal to noise for interface characterisation.

6-1 "3D Defect localization on System in Packages using Lock-in Thermographie" Christian Schmidt, Fraunhofer Institute for Mechanics of Materials Walter-Hülse-Str.1, 06120 Halle, Germany Localization and target preparation of defects inside of fully packaged and complex multichip devices are extremely challenging. Due to the opaque mould compound (MC) and the three dimensional built up of modern multichip devices standard IC level localization methods like OBIRCH, emission microscopy or liquid crystal thermography can not be applied. As already shown in literature, Lock-in Thermography (LIT) is a new tool for thermal based defect localization giving access also to inner electrical defects with a spatial of a few µm and sensitivity in µW range. By utilisation of the acquired phase signal, this method has also the potential to determine the defect depth which enables an nondestructive 3D defect localization. Within this talk, the basic theory of Lock-in Thermography and the operational principle for 3D defect localization will be presented. It will be shown which different influences, like defect geometry, geometrical thickness, thermal parameters, have to be regarded in order to enable a quantitative phase shift analysis. The talk will present some case studies of the successful application of LIT for defect localization in stacked die devices. 6-2 "Extension of Lock in thermography for thermal conductivity characterization and localisation of defects in depth" Arnaud Procher, Xavier Chauffleur Epsilon, Technoparc 10 – 10 rue Jean Bart, 31674 Labège France 20

Characterization of the thermal material properties is a first critical step in the reliability analysis of a system. The characterization in the time domain of a material could be relevant of information that could not be reached with static method. That is what has been developed in Epsilon to achieve a thermal properties characterization of material. This is inspired from the Lock In Thermography which is usually dealing with pulsed thermal excitation of samples. Here is developed a method based on the measurement of the propagation speed of a sinusoidal thermal signal through the material to extract thermal conductivity with very low dependency of the environment. First results on various structures and natures of material have shown good results in agreement with already known conductivity values. This characterization development has been coupled with the development of a method of failure analysis based on the same principle. The phase shifting of the thermal signal could be observed through the thickness of samples revealing structural defects deep in the material. Some improvements on different measurement technologies are performed nowadays mainly in order to expand the range of material that could be characterized by this method. One of the objectives is to reach smaller dimension to work for example in thin film characterization. 6-3 "Use of Lock-In Thermography for non-destructive 3D Defect Localization on System in Package and Stacked-Die Technology" Antoine Reverdy, Sector Technologies, 2 Avenue de Vignate, 38610 Gières, France With the growing variety, complexity and market share of 3D packaged devices, package level FA is also facing new challenges and higher demand. This paper presents Lock-In Thermography (LIT) for fully non-destructive 3D defect localization of electrical active defects. After a short introduction of the basic LIT theory, two slightly different approaches of LIT based 3D localization will be discussed based on two case studies. The first approach relies on package internal reference heat sources (e.g. I/O-diodes) on different die levels. The second approach makes use of calibrated 3D simulation software to yield the differentiation between die levels in 8 die μSD technology. 6-4 "3D Localization by Lock-in Thermography" Arnaud Loubaresse, ST-Ericsson Quality, Grenoble Failure Analysis Laboratory 12 rue Jules Horowitz, 38019 Grenoble, France With continuous increase of functionalities in mobile phone, package design is moving to System In Package (SIP). It means that several dices can be stacked inside the package. Most common failure analysis tools give a 2D localization meaning X/Y axes only, while the third axis Z have to be also known. Now the new challenge is to have 3D localization for the defect, so the aim of the presentation is to show some experiments done with lock-in thermography for checking Z localization capability.

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7-1 "Electrical test challenges for 3D" Erik Jan Marinissen and Ingrid De Wolf Imec, Kapeldreef 75, 3001-Heverlee Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) have many attractive benefits and hence are quickly gaining ground. Testing such products for manufacturing defects is still fraught with many challenges. This paper provides an overview of those challenges and their emerging solutions, categorized in the areas of (1) test flows, (2) test contents, and (3) test access. 7-2 "New methodology to characterize packaging with acoustic microscopy" Yves Ousten, Bruno Levrier, Laurent Bechou IMS UMR5218 Université Bordeaux Talence 33405 Cedex France Since 1985, when Quate 1 creates the first ultrasonic microscope, acoustic microscopy has been modified. The evolution of acoustic was helped by the evolution of the computer for the signal processing and the new possibility of storage (disk closed to the Tera byte 2). Packaging was also subjected to a deep change in terms number 3 of I/O (more than 200 I/O) and in terms of thickness (minus than 1mm). In this paper we make an overview of the different bring forward 4 in the domain of acoustic applied to packaging characterization. And we discuss about the acoustic microscopy weaknesses and the scientific opportunities to develop improvement for such packaging analysis. 7-3 "Current Induced Failure Analysis of Ni-based Microinsert Interconnections for Flip Chip Die on Wafer Attachment." V. Mandrillon(a), A. Reverdy(b), D. Arias(b), G.Tartavel(a), H.Boutry(a) (a): CEA-LETI, (b): Sector Technologies Reliability study have been performed on Ni-based Microinsert Interconnection for Flip Chip. Results analysis is enabling identification of different failures of a current induced stress test. Failure analysis have been performed on the first failing TSV structures using Lock-in Thermography. Technology used have demonstrated performance in detecting the smallest resistive fault. 8-1 "3D failures: Identify and meet the challenge of the third axis" Fabien Battistella, Sébastien Annereau, Suzel Lavagne, Emmanuel Doche THALES COMMUNICATION AND SECURITY 18 avenue Edouard Belin, 31401 TOULOUSE CEDEX Third axis is a new challenge for failure analysis. Our laboratory is in charge of failure analyse on classic components, plastic or ceramic package, in CNES Lab but 3D objects constitute, since a few years, a new axis of development. The classic flow based on external visualisation, X-rays inspection and internal visual inspection can not be applicable directly on 3D objects. like on the classic components, several defects can affect either the packaging or the die but the superimposition of levels reduces the efficiency of the methods of inspections and limits the access to the defect. 22

New methods must be developed in terms of defect localisation or sample preparation in order to find physical defects on 3D objects. The main studies performed in our lab and presented in this paper on 3D items, concern Industrial memory stack, from 3D plus manufacturer. The need is always the same: an electrical failure is detected and the aim of the analysis is to identify the physical defect associated. These modules can contain up to 8 levels of dies or packaged devices. “2D” technique limitations will be presented: X-rays radiography in most cases does not allow to detect open wires or internal defect due to the high density of the modules. In the same way, internal visual inspection can be performed only when the failed level memory is clearly identified by an appropriate method. In these conditions, the first step is to locale the incriminated level. Laser ablation is a fundamental tool to disconnect electrically each level and re test the module to validate or not the level disconnected. Moreover a non invasive technique for defect localisation that can be applied is Magnetic Microscopy 1 to observe leakage currents. Two cases studies are presented from electrical test to physical defect, explaining the approach chosen and describing the encountered difficulties. Reference: 1: Infante F, Perdu P, Petremont S, Lewis D. “A new methodology for short circuit localization on Integrated Circuits using Magnetic Microscopy Techniques coupled with simulations”. Proceedings of 16th IPFA, 2009 8-2 "Failure Analysis for eWLB-Packages - Strategy, Fail Mechanisms" Florian Felux, Bernd Krueger, Infineon Technologies AG, Am Campeon 1-12, 85579 Neubiberg, Germany Various Analysis methods were adapted and applied to so called eWLB BGA packages and results are shown in case studies. For this package type the schematic concept is presented. The components are manufactured jointly together, in a layer by layer process using an artificial wafer. On selected case studies, the capability of scanning acoustic microscopy (SAM), emission microscopy (EMMI), laser induced voltage alteration (TIVA) and thermography tools (LIT) will be shown for eWLB package analysis. The package type enables the possibility of localization from both sides. The distinction between silicon- and package related issues can well be made. Methods therefore, for top down- and cross sectioning- preparation will be presented. Wet- and dry chemistry processes and mechanical grinding and polishing techniques were applied. Damages due to electrical and mechanical overstress are shown. Images thereof were taken with optical microscopy and scanning electron microscopy (SEM). 8-3 "High throughput cross sectioning by plasma FIB and combined laser ablation" L. Kwakman1, R, Routh2, R. Young2, M. Straw2 1 FEI Company, Building AAE, PO Box 80066, 5600 KA Eindhoven, the Netherlands 2 FEI Company, 5350 NE Dawson Creek Drive, Hillsboro, OR 97124, USA A focused ion beam system utilizing an inductively coupled plasma (ICP) Xenon ion source will be introduced as a new sample preparation tool. The beam current range 23

of the plasma FIB is approximately two orders of magnitude larger than that of a classical Gallium LMIS FIB which makes the plasma FIB a very attractive tool for the analysis of relatively large features such as 3D stacked devices including TSV’s or MEMS. The Xe beam can be used to deposit protective layers, to mill a cross section in the order of 200 x 200 um2 and to image the regions of interest with ~ 20nm resolution. In addition, XeF2 gas assisted etching can be used for Si trenching. The new plasma FIB capabilities will be demonstrated with a variety of practical use case examples. The new plasma-FIB system yields removal rates of ~ 20000 m3/min which allows removing a volume of e.g. 200x200x100 m3 in approximately 3 hours, typical for e.g. TSV or BGA analysis. However, for use cases where still much larger volumes of material have to be removed to access the regions of interest -chip access with package removal being a most important use case example- even the plasma FIB is too slow and the long mill times become prohibitive. Alternative techniques with still higher material removal rates such as laser ablation are needed; laser ablation rates can be as high as ~ 10 7 - 108 m3/min which leads to a removal of 1 mm3 of material in ~ 1 hour. Laser ablation is widely used for depackaging and chip access but it cannot be used to do a complete sample preparation for failure analysis or device characterization as the damage induced by this thermal process can extend several microns into the sample (bottom of crater, cross section surface) and thus will alter the structures and materials that need to be studied. For the analysis of large features, removal of the heat affected zone (HAZ) is required: this is not practical with a standard Ga FIB (200 x 200 x 10 m3 would take 8 hours or more) but with a plasma-FIB such a combined laser – FIB workflow becomes within reach as the plasma FIB removal of the heat affected zone takes only 10-30 minutes. Hence, for packaged device failure analysis, the use of a (ns/ps/fs) laser in conjunction with a plasma FIB provides a unique new sample preparation capability not available before. Laser-plasma FIB workflows will be reviewed (stand-alone or integrated) and some interesting “Slice and View” results obtained with an integrated fs laser-SEM system will be presented.

Figure 1: plasma-FIB analysis of TSV (l), integrated laser set-up (m), fs-laser ablated 0.75 mm3 hole in epoxy (r) A part of the work has been performed in the project JEMSiP-3D, which is funded by the Public Authorities in France, Germany, Hungary, the Netherlands, Norway and Sweden, as well as by the ENIAC Joint Undertaking.

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8-4 "Laser chip access in 3D ICs" Matthew J. Lefevre, Frédéric Beauquis, Michael Obein Digit Concept, Secqueville en Bessin, France Die access by LASER has become more and more common in electronic packages. This approach has proven extremely fast and accurate, with valuable results especially on plastic packages. The LASER technique allows ultra low temperature wet chemical end opening and reduced time for dry chemical end opening. The technique is beginning to be used as a “Swiss knife” in many labs and many openings start with a LASER step today. This presentation will review several cases where a LASER was useful for 3D integrated circuits; including stacked die, SIP, and MEMS. Limitations and future possibilities of LASER access will also be discussed.

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Technical sponsors

EUFANET, the European Failure Analysis NETwork (www.eufanet.org) National Centre for Space Studies (CNES) CCT MCE, the CNES Technical Competence Center on MEMS and Electronic Components (cct/cct15/sommaire.htm) TOLSA the Toulouse Open Laboratory for Semiconductor Analysis (www.tolsa.org) Investigation on Defect Localization Techniques for Three-Dimensional (3D) Interconnects Merlion program (http://www.ambafrance-sg.org/Call-for-Projects-forthe-MERLION) Intraspec Technologies, (www.intraspectechnologies.com) IMAPS France (france.imapseurope.org)

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Buffet sponsors At the end of the first day, we will be happy to welcome you for a buffet (on site) to move forward in a warm and friendly atmosphere. This buffet is fully sponsored by

Digit Concept (www.digit-concept.com),

FEI (www.fei.com), Hamamatsu (www.hamamatsu.com),

IntraspecTechnologies (www.intraspectechnologies.com/en)

PVA Tepla Analytical Systems (www.pva-analyticalsystems.com)

Presto Engineering (www.presto-eng.com)

Sector Technologies (www.sector-technologies.com)

Novamems (www.novamems.com)

Thales Communication and Security (www2.thalesgroup.com/blogs/tcs/en) Please visit their web site. Descriptions of their activities are in the following pages

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Companies briefs

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Attendee list Company

Fraunhofer Institute Sector CNES Ipdia LAAS-CNRS 3D+ LAAS-CNRS Continental Auxitrol Esterline Sensor Group ST Microelectronics ST Microelectronics AMS C Square LAAS-CNRS Epsilon

Surname

Altmann Arias Bascoul Bellenger Boukabache Boulay Bourrier Bousquet Brida Brocard Cason Cassidy Chaptal Charlot Chauffleur Chopin Continental Costes Freescale Crepel Tepla Czurratis Sofradir Dantas de morais Onera-DESP David Imec De Wolf CNES Desplats Novamems Dhennin Freescale Dupuy IAS Orsay Eng TAS France Espana Matra Electronique Fagot Lfoundry Forli CNES Francis ST Frank FEI Franz NTU Gan Presto Engineering Gautier LAAS-CNRS Ghannam TU Berlin Glowaki RoodMicrotec Gruber Continental Guys Observatoire de Paris-Meudon-LESIA Hello CEA-Leti Henry

Name

Frank Daniel Guillaume Stephane Ali Nadia David Thierry Sebastiano Mélanie Morgan Cathal Jean-Louis Samuel Xavier Jean-Marie Olivier Olivier Peter Lionel Jean-Pierre Ingrid Romain Jeremie Philippe Pascal Béatrice Olivier Lionel Pressecq Thomas German Chee Lip Christian Ayad Arek Jurgen Dominique Yann David 37

NTU Intraspec CNES EMPA Digit Concept CNES NTU Infineon FEI Xradia Novamems Thales EADS Astrium Thales Digit Concept Serma Technologies Eurelnet-ADERA Continental DSO National Laboratories HIREX Engineering GE - Phoenix FEI Infineon IMEC Presto Engineering CNES CEA-Leti HIREX Engineering Austrian Institute of Technology 3D+ Digit Concept NTU Texas Instruments IMS Actia Texas Instruments CNES Airbus Epsilon Xradia ISAE-SUPAERO Sector Onsemi Serma Technologies Serma Technologies Hamamatsu

I Made Infante Jamin Jerjen Kerisit Kiryukhina Kor Krueger Kwakman Lander Lataste Lavagne Le Helloco Lebosse Lefevre Leveque Levrier Lewandowski Lim Chin Siong Lohier Lübbehüsen Mace Mack Marinissen Mayor Mialhe Moreau Morin Mutinati Noiray Obein Oktarini Otte Ousten Ozier Pauli Perdu Pons Procher Raleigh Raymundo Reverdy Rhayem Rimbault Roseng Roux

Riko Fulvio Thierry Iwan Francois Kiryukhina Katherine Bernd Laurens Peter Clovis Suzel Julien Pierre Matthew Maxence Bruno Pierre Desmond David Jens Herve Walter Erik Jan Cedric Florie Stephane Jean-Michel Giorgio Jerome Michael Kadek Ratih Dwi Michael Yves Valerie Martin Philippe Philippe Arnaud Estrada Fernando Antoine Joseph Stephen Alexandre Jean 38

Sector Serma Technologies CNES ST Microelectronics ST Fraunhofer Institute Observatoire de Paris-Meudon-LESIA EMPA Freescale Intraspec Infineon 3D+ Presto Engineering EM Microelectronic Marin Insidix Thales Hamamatsu Photonics Freescale

Roux Salome Sanchez Saulnier Savoia Schmidt Schmidt Schuetz Sienkiewicz Spezzigu Touzel Val Villemain von Gunten Weidmann Wislez Yokoyama Zirilli

Jean-Philippe Pascal Kevin Quentin Claudio Christian Regis Philipp Magdalena Piero Jerome Christian Michel Philippe Diane Alain Yoshiyuki Thomas

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