1 Databook
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Local Bus VU Graphies Controller OTt-G87
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OTI-087X Addendum
to the Databook 1
1
1 1
This Addendum describes changes to the OTI-087 February 1993 databook for OTI-087X parts. The OTI-087X currently does not support the RAS only refresh DRAM, 260'8 type DRAM and integrated feature connector support. ~
1
i
l
8
Disregard CASOn, CAS1n, CAS2n and CAS3n signaIs on the Operational Block Diagram.
13
This MD interface is not supported with this OTI-087 revision.
16
Disregard CASOn, CAS1n, CAS2n and CAS3n signaIs on the Memory Mapping Configuration.
25
EPDATA should be DCn under the OU-087 (LB386/486) co1urnn. ,
28
Pin 99 on OTI-087 (LB 386/486) should be DCn.
37
Extended Register 8, bits 6, 1,0 should be as below. AIso, pin 99 does not apply.
i
1
Description Disregard the reference to RAS only refresh in the feature liste This is currently not supported.
60
Bits 6, 1. 0 101 110
Pin 19 EPCLK EPCLK
Bit 7
Reserved.
Pin 20
EPDATA EPDATA
See attached for new Local Bus Schematics.
-
r---'
,-(--'
3/11/94
OTI-087 Drivers List ution
s ~RS:
x x
~AD2.62
x
~AD
9/10111112 ;hadc 1.0/2.0 mce4.0/4.1
x
x x
x
=wode III '33.1 1232.0x ,1232.2 , 123 3.0/3.1
x
x x x x x x x
x x
~odeII
x x
x
x x x x x x x x
ua 2.0 lCAD6.0 lCADl386 6.0
x x x
~TSR
lPerfect S.O lPerfect S.1 lowa3.1 lowaNf 3.1
x
x
x
x
x
x
x
x
x
x 132x25,43,60 132x25,43,60
x
x
x
x x
x x x
x x
x x x
x x x
x
x
x
x
x
132x25,43 132x25,43,60 resolution dependent
x
x
x
D4.S ua 1.l
x x
x
14.0
2.1
x
x
x
x
x x x x
x
x x x
132x25,43,60,8Ox60
x
x x
x
x x
132x25,43,60
x x
x x
x
=se resolutioDS are oDly IUpported by 0'0-087 due to the requirement of 2Mbytes ofvideo memory.
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Prefa~e
The information eontained in this document has been carefully checked and is be1ieved to 'be reliable. However, Oak Technology, Inc.makes no guarantee or warranty conceming the saidinformationand shaH not be responsible for any 10ss or damage of whatever nature resulting from the use of. or relianee upon it. Oak Teehnology, Ine. does not guarantee that the use of any information eontained herein will not infringe upon the patent or other rights of third parties, and no patent or other Iicense is implied hereby. This document does not in any way extend Oak Technology. Ine.'s warranty on any produet beyond that set forth in its standard terms and conditions of sale. Oak Technology, Ine. reserves the rightto make changes in the produets or specifications or both presented in this publication at any time and without notice. Life Support Applications Oak Technology. Ine. produets are not intended for use as critical eomponents in life support appliances, deviees, or systems in which the failure of an Oak Technology, Ine. product to perform eould reasonably he expeeted to result in personal injury.
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February 1993
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Table of Contents Description •......................•.......•••.•.••.•.............••..•••..•.•........•....••......••.....••..•.......•....•.••..•..•..••.•......•.•............•.........•.. 1
Supported Screen Formats Software Driver Support. Interface Descriptions Feature Descriptions
,
2 2 3 5
;
Block Diagrams and Features •.•...••.••••••••.•••.•••.•••.•.••.••..••••••••..••...•...••••.••.••..••••..•...........•..................••.................... 7
System Black Diagram 011-087 Operational Blod Diagram 011-087 on 486 Local Bus 011-087 on 386DX Local Bus Memory Interface Diagrams Memory Mapping Configuration
7 8 9 10 11 16
Pin Descriptions •..•••..•.•...•..••..••.•...•.•..••.........••....•................•..••••.....•.•.•....•.•.•......•.......••••.....•.........•.•...•...•....•...•..• 11
AT-Bus Interface...........•.....••.•.••....•.•.•••••..•....••.•..•..•.•••.•••.••••••...••••...•.....••...••..•...........................................17
Local Bus Interface 19 Clock Interface 20 CRT and Color Palette Interface 21 Video Memory Interface 22 EEPROM Interface 23 Power & Ground 23 Pin Out Cross Reference for OTI-087 in Different COnfigurations 24 Pin Diagrams 26 OTI-087 Register Definitions ..•••........•....••..•.••..•.....•.......••••.•...•..••.....•..........•.•...•....•..•..............••.••.•...•................ 29
Configuration Registers On-087 Extended Regïsters OTI-08? AC Timing and DC ·Parameters
29 31
_ _
Video Memory Cycle Timing _ Video ROM Cycle Timing. Video Pixel Timing Video DAC Timing _ Video VO Access Timing _ _••_ Local Bus Interface Timing. _ DUM Interface Timing & Mem.ory Refresh TImîng...•••....•...••._ _.•.•...•.......••._ OC Specification _ _ _
va
47 47 48 49 51 _...........•..•..52 .53 55 _••. ~•.; 51
.,' ~ ...... -t .:..•.
Package Oudines Example Schematics
VR5A I..ocal Bus ISA Bus
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60 66
60
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• 1
OTI-087 LOCAL BUS
VGA CONTROLLER
Description The OTI-087 is a highly integrated, single chip Local Bus VGA Controller compatible with the mM VGA standard. The On-087 offers a low-eost implementation for 24-bit color at a resolution of 640x480 while being capable of high resolutions inc1uding 1024x768 non-interlaced with 256 colors and 1280x1024 interlaced with 256 colors. The OU-087 is complete1y compatible with the mM VGA standard and implements aU registers and data paths while providing improved performance and additional functionality. Especial1y attractive for motherboard applications, the OTI-087 supports high speed local bus implementations for cost-effective high performance graphies.
Features
• IBM VGA compatible graphies controller with resolutions up to:
1024x768, 256 colors Non-Interlaced
1280x1024, 256 colors Interlaced
640x480, 16.8 million colors (24-bit)
• 100% Hardware and BIOS compatible with IBM's VGA • Supports up to 2 MBytes of memory:
2, 4 or 8 64K X 16 DRAMs
2, 4, 8 or 16. 256K X 4 DRAMs
2 or 4 256K X 16 DRAMs
2 or 4 S12KX 8
DRAMs
• Hardware cursor (64x64 2 bits/pixel) • Integrated feature connector support • Write cache for high speed local bus implementation • Read cache optimizes memory bandwidth usage • Integrated zero wait state AT bus performance • Supports 8. 16. or 32-bit memory interface with fast page operation • Supports CAS before RAS and RAS only refresh • Supports VESA-standard high vertical refresh rates of 72 Hz for fiicker-free displays • Up to 80 MHz maximum video dock rate • Complete linear addressability in protected mode • Packed pixel format for 256 color modes • Foreground/background color expansion registers for fast tat output • 16-bit graphies latch for truc 16-bit operations in pIanu modes • Special 256 color pattern and fi11 modes incrcase performance • Supports 132 column tat • Integratcd bus interface for PC(YJ/AT and local bus implcmentations • Supports portrait monitors • Truc 16-bit 1/0 read/writc operations • EEPROM support provides switchless contigurations
Supported Screen Formats
(
The OTI-087. not onir supports aU standard IBM VGA modes, but the fol1owing extended modes as well. Mmk lzh' 12h 4Eh' 4Fh'
SOho 51h' 52h" 52h 52h 53h" 53h 54h' S4h 54h 55h 55h' S5h 55h S6h 56h' 56h 56h 57h 57h' 58h" 59h Z 59h" 59h' S9h ' 5M"Z SM' SBh' 5Ch' z SCh' SDh" SEh' 5Th" 60h" 61h"
Resolution 640 x 480 640x 480 80x60 132 x 60 132 x 25 132 x 43 800 x 600 800 x 600 800 x 600 640 x 480 640 x 480 800 x 600 800 x 600 800 x 600 1024 x 768 1024 x 768 . 1024 x 768 1024 x 768 1024 x 768 1024 x 768 1024 x 768 1024 x 768 768 x 1024 768 x 1024 1280 x 1024 1024 x 768 1024 x 768 1024 x 768 1024 x 768 640 x 480 640x 480 640x 400 640x 480 640 X 480 800 x 600 1280 x 1024 640 x 480 800 %600 640 %400
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16 16 16 16 16 16 16 16 16 256 256 256 256 256 4 4 4 4 16 16 16 16 16 16 16 256 256 256 256 64K 64K 32K/64K 32K. 32K 32K 256 16.8M 64K 256
8x 16 8x 16 8x8 8x8 8x 14 8x8 8 x 16 8x 16 8x 16 8x 16 8x 16 8 x 16 8 x 16 8 x 16 8 x 16 8 x 16 8 x 16 8x 16 8x 16 8x 16 8 x 16 8x 16 8x 16 8x 16 8x 16 8x 16 8 x 16 8x 16 8 x 16 8x 16 8x 16 8x 16 8x 16 8x 16 8x 16 8x 16 8x 16 8% 16 8x 16
Alpha Format pot Clk(Mfkl 80x30 2S.175 80x30 80x 60 132x60 132 x25 132x 43 100 x 37.5 100 x 37.5'· 100 x 37.5 : 80x 30 80x 3If" 100 x 37.5 100 %37.5 100 x 37.5 128 x 48 128 x 48 128x 48 128 x 48 128 x 48 128 x 48 128 x 48 128 x 48 96x 64 96x 64 160x 64 128 x 48 128 x 48 128 x 48 128 x 48 80x 30 80x 30 80x 2S 80x 30 80x 30 100 x 37.5 160 x 64 80x 30 100 %37.5 80x25
.
31.500
25.175 40.000 40.000 40.000 36.000 40.000 50.000 25.175 31.500 36.000 40.000 50.000 44.900 65.000 78.000 78.000 44.900 65.000 78.000 78.000 44.900 65.000 78.000 44.900 65.000 78.000 78.000 50.000 63.000 50.000 50.000 63.000 78.000 78.000 78.000 78.000 25.175
H-frçg(KHz) V-fuq(Rz) 31.50 37.86 31.50 31.50 31.50 31.50 35.16 37.88 48.08 31.50 37.86 35.16 37.88 48.08 35.52 48.36 56.69 58.04 35.52 48.36 56.69 58.04 46.n
59.74 48.75 35.52 48.36 56.69 58.04 31.50 37.86 31.50 31.50 37.86 37.50 48.75 31.55 37.50 31.50
60 72 60 60 70 70 56 60 72 60 72 56 60 72
87 60 70 72
87 60 70 72
87 55 87 87 60 70 72
60 72 70 60 72 60 87 60 60 70
NonVideo Intçrlac.ed Msmmx Y« 256K. Yel 2561
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Data
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SDHOEn 50[15:81
A
OEn
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BUFFEIlE
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SI.l231 DAC
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DA DACRD
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DIPSWlTOl puu.-uPjDOW!'-
RDn 0\7~1
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r- - ----, ----- 1 llASn r91
-----
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RASn CASn "l8:O]
RASHn
RASHn
1 1 1 1
r81 rO
DQ[3:O] CASn "l8:O] WEn
WEAn
MD[jS:O]
MD[31:16] 1
1
1
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------..., RASn
)f------- --, 1 RASn r t3
DQ[3:O]
r5
RASn
CASn AlS:O] WEn
OEn MAP3
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MD Interface for 512Kx 8 DRAMs
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MDIII :8,3:0) ' RASLn' CASAn MAO 1I8:01.MA9 "" WEAn ,
OTI..Q87
f MAI9].MAOII8:0] MA(9).MA2318:0)
MDI23:16] "'" RASLn" CASAn
MA01[8:01.MA9 '-0.: WECn"
RASLn CASAn
DQ[7:O] RASn
CASn A{9:0)
Wfn
M0I1S:12.7:41 "'"
WEDn
RASLn " CASAn MA2318:01.MA9 " WEBn"
MD[31:O)
DQ[7:O] RASn CASn
Page 12
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A{9:0)
Wfn
DQ[7:O] RASn CASn
MAP!
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A{9:0)
Wfn
. - OEn
MD{31:24) RASLn CASAn MA2318:01.MA9 WEOn
MAPO
OEn
. - OEn
WEAn
WEBn
WECn
10
DQ[7:O) RASn CASn
MAP2
r3
'"' A[9:0] ' ,.... Wfn
.-
OEIl
MAP3
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1 OTl-087 Block Dlagrams
MD ~nterface (260) for 256K x 16 DRAMs
1
1 1 1
1 1
MD[23:16.11 :8.3:01", RASln' WEn MAOt 8:0]",
OTI~87
MA01{8:0) MA23[8:O)
RASI.n RASHn WEn CASOn
CAS1n CAS2n CAS3n
MD[31:0)
J 1 1 1
1
1 1 1
l 1
CASOn' CAS2n
.-
MD[23:16.11:8.3:O]", RASHn' WEn MAO t (8:0] '" CASOn' CAS2n
.-
MD[31:24.15:12.7:4J"", IlASln' WEn MA23fS,01''' CASt n ' CAS3n
.-
MD(3 t ,24.15:12.7:4J"", RASHn' WEn MA23 8:01..... CASt n ' CAS3n
.f"
OQ[t5:0) rO RASn WEn A[8:0) CASln CASHn OEn MAPO.l
OQ[15:0) r1 RASn WEn A[8:0] CAS!.n CASHn OEn MAPO.l
r.
OQ[1S:0] RASn WEn A[8:0] CAS!.n CASHn OEn MAP2.3
DQ[15:0] r3 ltASn WEn A[8:0] CAS!.n CASHn MAP2.3 OEn
- •. _. '.'..'~ ........~~ ..'.,.....,.....•.:-.. •.• .." .....
~.""
-* ~-' •. ,.' .....'""T.l'"7'-'", ........
.. .
.......
.....,,,;~
.....,- _. . .
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MD Interface (270) for 256K x 16 DRAMs
MD[7.3:16.11:8,3:O), "
RASln , CASAn MAOl [8:0] "
WEAn' wren
.-
OTI-087 MA01[8:O)
MA2318:0]
MD{7.3:16.11 :8.3:0] ......
RASHn ,., CASAn MA0118:01"
RASLn RASHn
WEAn ,. wren
CASAn
WEAn
WEBn
WEen
WEDn
.f MD{31 :24.15:12.7:4] "
RASln ,. CASAn MA7.3 8:0 "
WEBn ,. WEOn
MDI31:0]
.-
MD{31 :24.15:12.7:4] "
RASHn ,. CASAn MA7.3[8:O] "
WEBn' WEDn
.f
Page 14··
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DQlIS:O] RASn
rO
CASn Al8:0]
WELn WEHn OEn MAPO.l
DQllS:0] llASn
r1
CASn AI8:0]
WELn WEHn OEn MA PO. 1
DQl15:0] llASn
rt
CASn AI8:0]
WELn WEHn OEn MAP2.3
DQl15:0] llASn
r3
CASn Al8:0]
WELn WEHn OEn MAP2,3
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1 OTI.()87 Block Dlagrams
MD lnterface for 64K x 16 DRAMs
1 1 1
1
CASBn
OTl~87
RASLn CASAn MAOHS:l1 WEAn WEBn
MAO 118: 1]
MA2318:1]
1
1
WEAn
WEBn
~OI31:24.15:12,7:41 RASLn CASAn MA23IS:11 WEAn WEBn
1
1
1
, 1
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DQU5:0J RASn CASn A[7:O]
rO
WEIn
WEHn OEn MAPO.l
..... ~
..... ~
OQrt5:0] RASn CASn A[7:OJ
rI
--. r31
1 1 1
1
1 1 1
1 1 1
WEln WEHn
.OEn
MAP2,3
-_ ...
CAS!!!.__ ~ëASn----
WECn
Mor23:16.11:8.3:OJ RASHn
WWn
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OTI-G87 Reglster Definitions
1
7-4
These bits define the starting address range for the On-087.
Bits 7-4 , Sta'rt address
0000 000000 - only VGA memory mapping (AOOO(}'BFFFF).
.' 0001 100000
-.:
1 1
For 2 Mbyte aperture, the starting address has to be multiple of 2 Mbyte. Default: 0
1
3DF
1 l,
1
-.
1 1 1
1 1 1 1
iiii
FO~OÔO
Index = 6
ClockSeIect Reglster'
Illi
RfW
Description Video Clock Select. The state of these 4 bits are reflected in the pins CSEL[3:0]. Bits 1-0 of this register are the images of bits 3-2 of register 3C2. Bit 2 of this register is the image of bit 5 of extended register D. See frequency table for more details. This frequency table refleets On-068 only. Future Oak dock chips may have different frequencies.
3-0
Frequency Table for OTI-068 CSEL3
o o
o
o o o o o 1
CSEL2
CSEl1
CSELO
o o o o
0 0 1 1
0 1 0 1
1
0
0
1
0
1
1 1
o
1 1 0
0 1 0
o
0
1
1 1 1
o
1
0
o
1
1
1
1
0
0
1 1
1 1 1
0 1 1
1 0 1
1
ClOCK (MHz)
7-4 Reserved. Software reset must be executed each rime this register is updated. Default: 0
25.2
28.3 65.0 44.9 28.3 36.0 40.0
36.0 25.2 28.3 78.0 65.0 63.0 72.0 40.0 50.0
,
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3DF Configuration Reglster 1
Index = 7
R
(
llli
DescriptiQn BIOS path width selectiQn.
llit..Q Description
o 8-bit BIOS (1 ROM) 1 16-bit BIOS (2 ROM's) 2-1 Bus Modes. These bits define the bus configuration Qf the cQntroller. FQr different types of lQcal bus configurations, see ConfiguratiQn Register 2, bits 1 and O. Bits 2.1 Bus MQdes 00 Local bus MQtherboard. When this mode is selected, the On-087 must be enabled through pQrt 94/102 and 3C3. This mQde also disables ROM decoding at COOOO. 01 Local bus Add-on. When this mQde is selected, the On-087 must be enabled through pQrt 46E8/102 and enables ROM decoding at COOOO. 10 Motherboard, AT-bus configuration. In this cQnfiguration. the on-087 is enabled through 94/102 and either 3C3 Qr ENVGA and dQes not respond to COOOO. 11 Add-on card, AT-bus configuratiQn. In this configuration, the On-087 is enabled through 46E8/102 and responds to COOOO. 4-3 DRAM type. These bits define the type of DRAM used. Bits 4,3 DRAM Type 00 64K:x16 01 Reserved. 10 256~ 11 512Kx8. 5 ConfiguratiQn for pin 92 when in lQcal bus configuration (bit 2 of this register - 0). Bit.j DescriptiQn o pin 92=MASTERn 1 pin 92=HLDA 6 IIO write sampling dock speed. IOWn frQm the AT-bus is internally sampled with MCLK. thus it is important to indicate tQ the IIO controller the MCLK speed. lfu.j Description o MCLK >- 44 MHz
1 MCLK < 44 MHz.
7 CPU Clock select.
Bit1 Description
o Normal system dock; lX dock: for 386, IX dock for 486. VL-Bus CPU dock; IX dock for 386. 1 Bit 2 and bit 7 of this register in combination with bits 1,0 of Configuration Register 2 are used to enable the EEPROM function for capable 386/4861ocal bus configurations. Inder-7 Index-8 Bit Z 2 Bit 1 0 fln..1Z Description x 0 0 0 BD[Z] Oak Local Bus o 0 x x CPURFSET 386/486 Local Bus o 1 x x BD [7] AT-Bus 1 0 x x EEPCSn 386/486 Local Bus The contents of this register are loaded from MD[Z:O] during hardware reset.
o
Page 36
(,
1 ('
OTI-087 Reglster Definitions
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àI
3DF Configuration Reglster 2
Bit
,l'
1-0
1 1
19)
1 1·
5-4 6
i1' 1 1
7
1
DescriptiQn
Local bus interface select bits - These bits define IQcal bus type. These bits Qnly have effect when bits 2 and 1 Qf ConfiguratiQn Register 1 are 00. Bits 1.0 Bus Type 00 Oak local bus. 01 80386 local bus interface. 10 80486 local bus interface. Il Reserved. CQlOl Palette interface select bits.
Bits 3,2 . CoIQr Palette Type
00 Type 0: BT476, SC11487,1MSGI74 or equivalent.
01 Type 1: MU9C1715 Qr equivalent.
Type 2: BT484 or equivalent.
11 Reserved.
For Type 0, PCLK is passed through. For Types 1 and 2, PCLK is divided by two when in Hi-eolor mode and divided by three when in true CQlor mode. AIso, for Types 1 and 2, MUXCLK is generated te Iatch pixel data. For Type 2, BLANKn is delayed by 1 divided PCLK lleserved. Enable Feature Connector for select local bus configurations. Bits 0, l, and 6 of this register determine the function of pins 19 and 20. Bit 6 can only be enabled when GAlO and SllDYi are not needed. Bits 6, 1. 0 Pin 19 :fin.1Q Pin 99 o0 0 GAlO N,C. DCn o0 1 GAlO SRDYi DCn o10 GAlO SRDYi DCn 011 1 0 0 EPCLK EPDATA DCn 1 0 1 EPCLK SllDYi EPDATA 1 1 0 EPCLK SllDYi EPDATA 111 DllAM support bit. This bit determines whether pins 116-119 and pin 123 is a write enable Qr CAS pin for different DllAM types. The contents of this register are Ioaded from MD[15:8] during hardware reset. Bit Pin 123 Pin 118 Pin 119 Pin 116 Pin 117 o CASAn WEAn WEBn WECn WEDn 1 WEn CASAn CASBn CASCn GASDn
3DF
Suatcb Reglsters Bit Description
7-0
Index
=9, A, B
R/W
8 scratch bits.
These scratch pads are defined and reserved for internal use. Application softwar.e and device drivers should not use them.
1
R
®
1
1 1 1
Index =8
3DF
CRr Control Reglster
Bit 7"()
3DF
Index
=C
DescriptiQn NQt used.
Oak Mlsc.ellaneous Register llit DescriptiQn
Index = D
2.()
FIFO depth CQntrol. A minimum memQry FIFO depth is filled with display data befQre CPU read/write request is allQwed tQ process. These bits are the image Qf index register 20 bits 2..(). 4-3 Extended graphies mode selectiQn. These twQ bits are the image Qf extended register 21 bits 3-2. MQde SelectiQn Bits 4.3 VGA mQdes Qr Oak planar mQdes. 00 01 Oak packed pixel mQdes. Used for 256, 32K, 64K and 16M cQIQr mQdes.
10 Reserved.
11 Reserved.
CIQck select bit 2 (CSEU). Used witll bits 2 and 3 ofMiscellaneQus register in the 5 general registers area to select different dock frequencies.. Up to eight different dock inputs can be se1ected. This bit is the image Qf extended register 6 bit 2. Refer tQ extended register 6 fQr dock table. 7-6 . Reserved. This register is for compatibility purposes only. New software devdopment should use ex:tended registers 6, 20 & 21. Software rcset must he executed earo time this register is updated. Default: 0
3Df Backward CompatlblÛty Reglster 1fu DescriptiQn 7'()
NQt used.
Index = F
3Df NMI Data Cache Reglster Bit DescriptiQn 7'()
3Df
Not used.
Index = 10
Dlp Swltc.h Resister
Bit 7'()
R
DescriptiQn Dip switch status register. The contents Qf this register are loaded from 5D[7:0] during hardware reset.
Index == 11
3DF Segment Reglster Bit DescriptiQn M 7-4
Index =E
Read segment fQr CFU memQry read. Write segment fQr CPU memQry write.
Page 38
R/W
.
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1 . 011"087 liéglster Definitions
{ ~
1 1
1 1 1.
These two ~bit segment registers are used to extend the CPUaddress for videomemory sizes greater than 256 Kbytes. Bits 3-0 are used to address the video memory read operation. Bits 7-4 are used to address the video memory for write mode operations. Bits 3-0 are the image of index register 23 bits 3 O. Bits 7-4 are the image of index register 24 bits 3-0.
CPUADDR[19:16]"" NRll.[3:0] for read.
CPUADDR[19:16] ... NRll.[7:4] for write.
This register is provided for compatibility purposes only. New software devdopment should use registers 23_ 24 Be 25.
Default: 0
3DF
Bit 7-0
3DF
J
1 1 1 1 1
1 1 ',:
rr
'.
L
Description Not used.
Index = 13
Bus Control Reglster llit Description
2-0 3
1
Index = 12
Configuration Reglster
4
S
6
7
Reserved.
AT-bus Zero-Wait-State enable.
Bit 3 Description o Disable zero wait state AT-bus operation.
1 Enable zero wait state AT-bus operation.
BIOS ROM bus width selection. JTh...1 Description o Enable 8-bit video BIOS ROM interface. 1 Enable 16-bit video BIOS ROM interface. BIOS ROM address selection. Ifu..ï Description o Enable video BIOS ROM access at COOOO. 1 Disable video BIOS ROM access at COOOO. 1/0 access bus width selection. BiL6 Description o 8-bit IIO access. 1 16-bit 1/0 access. Video memory bus width selection. llli.1 Description o 8-bit memory access. ~ l 0 1 16-bit memory access.
Dcfault: 0 -
,3DF
Index =14
Oak. Overflow Reglster
1lli
o 1
2 3 64
Description Vertical Total Bit 10 Vertical Blank Start Bit 10 Vertical Retrace Start Bit 10
High Order Stan Address Bit 8
Reservcd.
1 Pue 39
RfW
a
'0 c:::3
7
Enable interlaced display. lliLZ DescriptiQn o nQn-interlaced display. 1 interlaced display.
(~,
,1
DefauIt: 0
NQte: The High Order Start Address Bit 8 (bit 3 of this register) can aIso be updated with register
index = 17. bit O.
3DF
HSYNC Dlvlded byTwo Start Reglster Bit 7-0
3DF
7-0
Index = 16
DescriptiQn NQt used.
3DF Extended CRrC Reglster Bit 2-0 7-3
R/W
DescriptiQn This 7 bit value indicates when the vertical retrace will start in every Qdd frame during interlaced mode. The unit of this value is in the character PQsition.
Oak Overflow Reglster 2
Bit
Index = 15
Index = 17
R/W
Description
High Order Start Address Bit 10-8.
Reserved.
Note: The High Order Start Address Bit 8 (bit 0 of this register) can also be updated using register index = 14. bit 3. 3DF
EEPROM Control Reglster
Bit
o
1 2
'3
7-4 DèfauIt: 0
Index = 18
R/W
DescriptiQn EEPROM Data. This bit is the data Hne between the seriaI EEPROM and the VGA controUer. When reading this bit, data cornes from CSEL(O]. When writing te this bit. data is sent to CSEL[1]. At the board level. CSEL(O] and CSEL(1] are connected to the EEPROM data out and the EEPROM data in pins respeetively. EEPROM CS. This bit is used as the chip select cQntrol fQr the EEPROM. It should be set to 1 for the VGA controUer to access the EEPROM. EEPROM Function Enable. This bit selects the funetion of the CSEL bus. When this bit is l, CSEL[2:0] are used to interface with the EEPROM. When this bit is 0, the CSEL[2:0) function as dock select signaIs. EEPROM Clock(SK). The value of this bit, which acts as the shift dock for the seriaI . EEPROM, is ref1eeted on CSEL[2]. To program the EEPROM, this bit is programmed to toggIe between 1 and 0 every 4us. Reserved.
".... Page40 .
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1 . OTI-oS7 Register Definitions
1 \
.....
3DF
1 1 1
1 1. 1 1 1
1 1 1
1 1 1
Cotor Palette Range Reglster Jfu pescription 3-0
74 Default: 4
3DF
Index
=19
R/W
Color Palette range. This register. in addition to the IBM VGA Color Palette address range 3C6-3C9. defines the VO address range for the Color Palette. The Color Palette read and Color Palette write lines of the On-087 are activated when the programmable address range 3xO-3xF is accessed. Here x is defined by bits 3-0 of this register. The valid value for this register is 0 to E. A programmed value of F disables the Color Palette range function. Reserved.
Index = 20
FIFO Depth Reglster
RfW
Jfu
Description
3-0
FIFO depth control. This register defines what minimum level the display FIFO must be filled to for a CPU read/write request to be processed. Bits 2-0 of this register are a mirror image of bits 2-0 of extended register D.
7-4
Reserved.
Default: 1
Index =21
3DF . Mode Select Reglster
llli
Description Enable Hi-eolor: This bit is used to select the On-087 for Hi-eolor operation. o When this bit is enabled. aIl horizontal CRT parameters are multiplied by two. Enable True Color: This bit is used to select the On-087 for True Color operation. 1 When this bit is enabled. aIl horizontal CRT parameters are multiplied by three. Extended graphies mode selection. 3-2 Bits 3.2 Mode Selection
00 VGA modes or Oak planar modes.
01 Oak packed pixel modes. Used for 256. 321
l'S
1
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03
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