Jan 2, 1995 - File under Integrated Circuits, IC04. January 1995 ... For a complete data sheet, please also download: ⢠The IC04 LOCMOS HE4000B Logic.
DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
Quadruple exclusive-OR gate DESCRIPTION The HEF4030B provides the positive quadruple exclusive-OR function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance.
Fig.2 Pinning diagram.
HEF4030BP(N):
14-lead DIL; plastic (SOT27-1)
HEF4030BD(F):
14-lead DIL; ceramic (cerdip)
HEF4030BT(D):
14-lead SO; plastic
(SOT73) (SOT108-1) ( ): Package Designator North America Fig.1 Functional diagram.
Fig.2 Logic diagram (one gate).
TRUTH TABLE
FAMILY DATA, IDD LIMITS category GATES
I1
I2
O1
L
L
L
H
L
H
L
H
H
H
H
L
See Family Specifications
Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage)
January 1995
2
Philips Semiconductors
Product specification
HEF4030B gates
Quadruple exclusive-OR gate
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V
SYMBOL
TYPICAL EXTRAPOLATION FORMULA
TYP.
MAX.
85
175
ns
57 ns + (0,55 ns/pF) CL
Propagation delays In → On HIGH to LOW
LOW to HIGH Output transition times HIGH to LOW
LOW to HIGH
5
35
75
ns
24 ns + (0,23 ns/pF) CL
15
30
55
ns
22 ns + (0,16 ns/pF) CL
5
75
150
ns
47 ns + (0,55 ns/pF) CL
10
30
65
ns
19 ns + (0,23 ns/pF) CL
15
25
50
ns
17 ns + (0,16 ns/pF) CL
5
60
120
ns
10 ns + (1,0 ns/pF) CL
10
30
60
ns
9 ns + (0,42 ns/pF) CL
20
40
ns
6 ns + (0,28 ns/pF) CL
5
60
120
ns
30
60
ns
9 ns + (0,42 ns/pF) CL
20
40
ns
6 ns + (0,28 ns/pF) CL
10
10
VDD V dissipation per package (P)
tPLH
15
15
Dynamic power
tPHL
tTHL
tTLH
10 ns + (1,0 ns/pF) CL
TYPICAL FORMULA FOR P (µW)
5
1 100 fi + ∑(fo CL) × VDD2
where
10
4 900 fi + ∑(fo CL) × VDD2
fi = input freq. (MHz)
15
14 400 fi + ∑(fo CL) × VDD
2
fo = output freq. (MHz) CL = load capacitance (pF) ∑(foCL) = sum of outputs VDD = supply voltage (V)
prévus à cet effet, puis insérer les onglets jusqu'à enclenchement. 2 Déployer les deux ... Contenu de la boîte. • Base du chargeur. • Coussinets du support (2).
characterized for operation from 0°C to 70°C. ... Products conform to specifications per the terms of Texas Instruments ..... Test Circuit and Voltage Waveforms ...
security camera screen monitoring speaker (loud speaker). Make a simple sentence explaining how the sliding gate operates. You can explain part of the.
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D Internal ESD Protection. D Thermal Shutdown. D High-Noise-Immunity Inputs. D Functional Replacements for SGS L293 and. SGS L293D. D Output Current 1 ...
typical temperature coefficient for all VDD = 0.3%/°C values, all input rise and fall ... 2.54. 0.100 e3. 17.78. 0.700. F. 7.1. 0.280. I. 5.1. 0.201. L. 3.3. 0.130. Z. 1.27.
SPECIFICATIONS FOR DESCRIPTION OF âBâ ... the device at these orany other conditions above those indicated in the operational sections of this specification.
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Typical temperature coefficent for all VDD value is 0.3 %/°C. Symbol ... 2.54. 0.100 e3. 15.24. 0.600. F. 7.1. 0.280. I. 5.1. 0.201. L. 3.3. 0.130. Z. 1.27. 2.54. 0.050.
POST OFFICE BOX 655303 â¢DALLAS, TEXAS 75265 ... testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in ... Package thermal impedance, θJA (see Note 2): D package.
Jul 11, 2015 - Pb-Free. (RoHS). CU NIPDAU. N / A for Pkg Type. 0 to 70 .... Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip ...