Proceedings 2005 International Conference on Field Programmable Logic and Applications (FPL)

Tampere Hall Tampere, Finland August 24–26, 2005

Organised by Tampere University of Technology

Technical Co-Sponsor: The IEEE Circuits and Systems Society

Sponsored by: The IEEE Finland Section Academy of Finland

2005 International Conference on Field Programmable Logic and Applications

Copyright and Reprint Permission: Abstracting is permitted with credit to the source. Libraries are permitted to photocopy beyond the limit of U.S. copyright law for private use of patrons those articles in this volume that carry a code at the bottom of the first page, provided the per-copy fee indicated in the code is paid through Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923. For other copying, reprint or republication permission, write to IEEE Copyrights Manager, IEEE Operations Center, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 08855-1331. All rights reserved. Copyc 2005 by the Institute of Electrical and Electronics Engineers, Inc. right IEEE Catalog Number: ISBN: Library of Congress:

05EX1155 0-7803-9362-7 2005928516

c City of Tampere. Printed by Juvenes Print, Tampere, Finland. Cover photograph

Preface This book contains the papers presented at the 2005 International Conference on Field Programmable Logic and Applications (FPL) held on August 24–26, 2005, in Tampere, Finland. Field-programmable logic has grown to become a mainstream technology for implementing large systems and accelerating applications. No longer are these devices used simply as vehicles for prototyping digital circuits; modern programmable devices contain embedded memories, processors, arithmetic blocks, complex clocking structures, and advanced I/O interfaces. These features have opened the door to much larger systems, and have allowed them to form the heart of very complex reconfigurable computers. This tremendous growth in the capabilities of programmable logic can bee seen in the papers of this year’s conference. This year, we received 280 submissions, from which the program committee selected 82 full papers and 46 poster papers. In addition, we continue successful tradition of the Ph.D. forum, in which 20 Ph.D. students from 65 submissions have been selected to present their research work. The selected papers and posters come from 24 different countries: USA 28 Finland 5 The Netherlands 4 Hungary 1 UK 21 France 5 China 3 Ireland 1 Germany 19 Australia 4 Czech Republic 3 Italy 1 Spain 14 Belgium 4 India 2 Poland 1 Japan 12 Greece 4 Sweden 2 Singapore 1 Canada 7 Portugal 4 Brazil 1 Turkey 1 We would like to thank all of the authors for submitting their papers. We also gratefully acknowledge the tremendous reviewing work done by the Program Committee members and many additional reviewers who contributed their time and expertise. We are extremely pleased that of the 1035 reviews looked for, 1027 (99.2%) were completed. We would also like to thank the members of the Organising and Steering Committees for their hard work over the past year. The members of the Program, Organisation, and Steering Committees are listed on the following pages. We would also like to thank our Gold sponsors, Nokia and the Academy of Finland, and our Bronze sponsors, Altera, Synplicity and Xilinx. We would also like to thank IEEE Circuits and Systems Society for its technical co-sponsorship, and Celoxica for sponsoring the FPL Portal. Tero Rissa Program Co-Chair Steve Wilton, Program Co-Chair Philip Leong, PhD Forum Chair

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Organisation Committee General Chair Jari Nurmi

Tampere University of Technology, Finland

Program Co-Chairs Steve Wilton University of British Columbia, Canada Tero Rissa Imperial College London, UK PhD Forum Chair Philip Leong Imperial College London, UK Finance Chair Jarmo Takala

Tampere University of Technology, Finland

Sponsor and Exhibition Chair Timo Rintakoski Tampere University of Technology, Finland Local Arrangements Chair Riku Uusikartano Tampere University of Technology, Finland Publicity Chair Reiner Hartenstein

University of Kaiserslautern, Germany

Web Chair Heikki Orsila

Tampere University of Technology, Finland

Equipment Chair Tero Sihvo Tampere University of Technology, Finland Conference Secretary Irmeli Lehto Tampere University of Technology, Finland

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Program Committee Jason H. Anderson Jeff Arnold Jürgen Becker Neil Bergmann Vaughn Betz Dinesh Bhatia Eduardo Boemo Eli Bozorgzadeh Gordon Brebner Stephen D. Brown Klaus Buchenrieder João M.P. Cardoso Mark Chang Peter Y.K. Cheung Paul Chow Katherine Compton Jason Cong George Constantinides Martin Danˇek José T. de Sousa Carl Ebeling William Fornaciari Fernando Gonçalves Herbert Grünbacher Steven Guccione Reiner Hartenstein Scott Hauck Oliver Héron Mike Hutton Mahmut Kandemir Sinan Kaptanoglu

Xilinx, Canada Stretch, USA University of Karlsruhe, Germany Queensland University of Technology, Australia Altera, Canada University of Texas, USA University of Madrid, Spain University of California at Irvine, USA Xilinx, USA Altera, Canada Infineon Technologies AG, Germany University of Algarve, Portugal Olin College of Engineering, USA Imperial College London, UK University of Toronto, Canada University of Wisconsin-Madison, USA UCLA, USA Imperial College London, UK Czech Technical University in Prague, Czech Republic Technical University of Lisbon, Portugal University of Washington, USA Politecnico di Milano, Italy Technical University of Lisbon, Portugal Carinthia Technical Institute, Austria Cmpware, USA University of Kaiserslautern, Germany University of Washington, USA University of Montpellier II, France Altera, USA Pennsylvania State University, USA Actel, USA

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Tom Kean Andrew Kennings Andreas Koch Dominique Lavenier Dong-U Lee Guy Lemieux Philip Leong John Lockwood Wayne Luk Patrick Lysaght Bingfeng Mei Oskar Mencer Paul Metzgen Brent Nelson Horácio Neto Jari Nikara Juanjo Noguera Jari Nurmi Seda Ogrenci Memik Sebastien Pillement Marco Platzner Viktor Prasanna Steven Quigley Tero Rissa Jonathan Rose Zoran Salcic Sergej Sawitzki Hartmut Schmeck Satnam Singh Subarna Sinha Gerard Smit Rainer Spallek Jürgen Teich Russell Tessier Lothar Thiele Lionel Torres Stephen Trimberger Timo Yli-Pietilä Milan Vasilko Stamatis Vassiliadis

Algotronix Consulting, UK University of Waterloo, Canada University of Braunschweig, Germany IRISA / CNRS, Rennes, France UCLA, USA University of British Columbia, Canada Imperial College London, UK Washington University, USA Imperial College London, UK Xilinx, USA IMEC, Belgium Imperial College London, UK Altera, UK Brigham Young University, USA Technical University of Lisbon, Portugal Nokia Research Centre, Finland HP, Spain Tampere University of Technology, Finland Northwestern University, USA University of Rennes I, France ETH Zürich, Switzerland University of Southern California, USA University of Birmingham, UK Imperial College London, UK University of Toronto, Canada University of Auckland, New Zealand Philips Research, The Netherlands University of Karlsruhe, Germany Microsoft, USA Synopsys, USA University of Twente, The Netherlands Dresden University of Technology, Germany University of Erlangen-Nuremberg, Germany University of Massachusetts Amherst, USA ETH Zürich, Switzerland University of Montpellier II, France Xilinx, USA Nokia Research Center, Finland Bournemouth University, UK Delft University of Technology, The Netherlands

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Serge Vernalde IMEC, Belgium Markus Weinhardt PACT, Germany John Williams University of Queensland, Australia Steve Wilton University of British Columbia, Canada Weng Fai Wong National University of Singapore, Singapore Roger Woods Queen’s University of Belfast, UK

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Steering Committee Chairman Patrick Lysaght

Xilinx, USA

Members Peter Y.K. Cheung José T. de Sousa Manfred Glesner John Gray Herbert Grünbacher Reiner Hartenstein Andres Keevallik Wayne Luk Lionel Torres Serge Vernalde Roger Woods

Imperial College London, UK Technical University of Lisbon, Portugal Darmstadt University of Technology, Germany Independent Consultant, UK Carinthia Technical Institute, Austria University of Kaiserslautern, Germany Tallinn Technical University, Estonia Imperial College London, UK University of Montpellier II, France IMEC, Belgium Queen’s University of Belfast, UK

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Additional Reviewers Ali Ahmadinia Su-Shin Ang Sutjipto Arifin Talal Arnaout Michael Attig Prabhat Avasare Zachary Baker Sudarshan Banerjee Michael Beauchamp Jens Becker Tobias Becker Olav Beckman Marcus Bednara P. Benoit Olivier Berder Rajarshee Bharadwaj Abbas Bigdeli Morteza Biglari-Abhari William Bishop Ivan Blunno Christophe Bobda Vanderlei Bonato Christos-Savvas Bouganis Jacob Bower Carlo Brandolese Nick Campregher Bryan Catanzaro Deming Chen Guangyu Chen Guilin Chen

Ray Cheung Charles Chiang Daniel Chillet Jonathan Clarke Paul Coene Ben Cope Gabriel de Figueiredo Coutinho G. Adam Covington Kris Croes Miro Cupak Kristof Denolf Dirk Desmet Robert Dimond Pedro Diniz Adam Donlin Filipa Duarte Ken Eguro Mehrdad Eslami Brian Van Essen Chun Te Ewe Suhaib Fahmy Joachim Falk Yiping Fan Cary Feldstein Marcio Merino Fernandes Andreas Fidjeland Blair Fort Altaf Abdul Gaffar Carlo Galuzzi Aman Gayasen

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Zhiguo Ge Mathieu Giraud Gokul Govindu Flavius Gruian David Guevorkian Leo Han Michael Haselman Laurence Hey Clint Hilton Mark Holland M. Huebner Jae Young Hur Tuomas Järvinen Phillip Jones Edward Joon Sim Christopher Kachris Chip Kastner Joachim Keinert Nathalie Chan King Choy Dirk Koch R. Koenig Lih Wen Koh Andre Kokkeler Thorsten Köster Georgi Kuzmanov Aditya Kwatra Vesa Lahtinen Andy Lambrechts Jooheung Lee Anthony Leroy Hock-Beng Lim Andrew C. Ling Greg M. Link Jing Lu Jianfeng Luo Usama Malik Valavan Manohararajah Theodore Marescaux Eduardo Marques

Kostas Masselos Philippe Maurine John McAllister Paul McHardy Wim Melis Anca Molnos Carlos Morra Gareth Morris James Moscola Elena Moscu Panainte Kathy Nguyen Dang Vincent Nollet Shane O’Neill Shobana Padmanabhan Joseph Palmer Robert Pasko K. Paulsson Luca Pizzamiglio Franjo Plavec Christian Plessl Todd Polk Kara Poon Brad Quinton Praveen Raghavan Jukka Reunamäki Urban Richter Abdel Rigumye Pasko Robert Fabio Salice Perttu Salmela Bernd Scheuermann Thomas Schlichter Martin Schoeberl Ronald Scrofano Pete Sedcole Asadollah Shahbahrami Akshay Sharma Nalin Sidahao Love Singhal

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Alastair Smith Haoyu Song Ioannis Sourdis Todd Sproull Richard Stahl Christos Strydis Qing Su Zhenxin Sun Theocharis Theocharides A. Thomas David Thomas Tim Todman Richard H. Turner M. Ullmann Tom Vander Aa Peter Waldeck Benjamin Ylvisaker Zhiru Zhang Winson Zhu Ling Zhuo Daniel Ziener

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Table of Contents 1.A: Embedded Soft Processors CUSTARD – A Customisable Threaded FPGA Soft Processor and Tools R. Dimond, O. Mencer, and W. Luk

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A Reconfigurable Instruction Memory Hierarchy for Embedded Systems Z. Ge, H.B. Lim, and W.F. Wong

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Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor M. Lanuzza, S. Perri, M. Margala, and P. Corsonello

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1.B: Logic Synthesis FPGA PLB Evaluation using Quantified Boolean Satisfiability A.C. Ling, D.P. Singh, and S.D. Brown FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations C. Morra, J. Becker, M. Ayala-Rincon, and R. Hartenstein Post-Placement BDD-Based Decomposition for FPGAs V. Manohararajah, D.P. Singh, and S.D. Brown

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1.C: Networking Applications 1 Hashing + Memory = Low Cost, Exact Pattern Matching G. Papadopoulos and D. Pnevmatikatos

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High-speed and Memory Efficient TCP Stream Scanning using FPGA Y. Sugawara, M. Inaba, and K. Hiraki

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Mutable Codesign for Embedded Protocol Processing T. Sproull, G. Brebner, and C. Neely

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2.A: Chip Communication Architectures Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor C.-W. Wang, N.P. Carter, R.B. Kujoth, J.J. Cook, and D.B. Gottlieb Applying the Small-World Network to Routing Structure of FPGAs H. Tsukiashi, M. Iida, and T. Sueyoshi

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2.B: CAD for Coarse-Grained Logic MILP-based Placement and Routing for Dataflow Architecture M. Healy, M. Ekpanyapong, and S.K. Lim

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Using DSP Blocks for ROM Replacement: A Novel Synthesis Flow G.W. Morris, G.A. Constantinides, and P.Y.K. Cheung

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2.C: SAT Solvers and Neural Networks An FPGA Solver for WSAT Algorithms K. Kanazawa and T. Maruyama

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An Efficient and Scalable Architecture for Neural Networks with Backpropagation Learning P.O. Domingos, F.M. Silva, and H.C. Neto

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3.A: Chip Architectures Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC M. Holland and S. Hauck A 11 GHz FPGA with Test Applications C. You, J.-R. Guo, M. Chu, K. Zhou, R.P. Kraft, J.F. McDonald, and B. Goda Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes F.-J. Veredas, M. Scheppler, W. Moffat, and B. Mei

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3.B: Arithmetic Power and Area Optimization for Multiple Restricted Multiplication N. Sidahao, G.A. Constantinides, and P.Y.K. Cheung

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Programmable Numerical Function Generators: Architectures and Synthesis Method T. Sasao, S. Nagayama, and J.T. Butler

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Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic C.T. Ewe, P.Y.K. Cheung, and G.A. Constantinides

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3.C: Video Processing Applications 1 Real-Time Handel-C Based Implementation of DV Decoder M. Gorgo´n, S. Cicho´n, and M. Pac

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Address Generation for FPGA RAMs for Efficient Implementation of Real-Time Video Processing Systems N. Lawal, B. Thörnberg, and M. O’Nils

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Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing S.A. Fahmy, P.Y.K. Cheung, and W. Luk

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4.A: Run-Time Reconfigurable Architectures and Applications A Dynamically Reconfigurable Bluetooth Base Band Unit J. Esquiagola, G. Ozari, M. Teruya, M. Strum, and W. Chau DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices C. Bobda, A. Ahmadinia, M. Majer, J. Teich, S. Fekete, and J. van der Veen

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4.B: Routing Characterization Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks A. Ye and J. Rose Timing Aware Interconnect Prediction Models for FPGAs S. Balachandran and D. Bhatia

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4.C: Multidimensional Processing Multidimensional Dynamic Programming for Homology Search S. Masuno, T. Maruyama, Y. Yamaguchi, and A. Konagaya

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Real-Time Generation of Three-Dimensional Motion Fields H. Niitsuma and T. Maruyama

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Evaluation of Ray Casting on Processor-Like Reconfigurable Architectures T. Oppold, T. Schweizer, T. Kuhn, W. Rosenstiel, U. Kanus, and W. Straßer

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5.A: Network on Chip Architectures A Flexible Circuit-Switched NOC for FPGA-Based Systems C. Hilton and B. Nelson

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Energy-Efficient NoC for Best-Effort Communication P.T. Wolkotte, G.J.M. Smit, and J.E. Becker

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Fault-Tolerant XGFT Network-on-Chip for Multi-Processor System-on-Chip Circuits H. Kariniemi and J. Nurmi

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5.B: Tools and Methods for Run-Time Reconfiguration Modular Partial Reconfiguration in Virtex FPGAs P. Sedcole, B. Blodget, T. Becker, J. Anderson, and P. Lysaght

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Configuration Merging for Adaptive Computer Applications N. Kasprzyk, J.C. van der Veen, and A. Koch

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Context Saving and Restoring for Multitasking in Reconfigurable Systems H. Kalte and M. Porrmann

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5.C: Implementation Techniques An FPGA Application with High Speed Serial Transceiver Running at Sub-nominal Rate D. Šuvakovi´c and I. Hadži´c

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FPGA-Based Implementation and Comparison of Recursive and Iterative Algorithms V. Sklyarov, I. Skliarova, and B. Pimentel

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Configurable Hardware/Software Architecture for Data Acquisition: Implementation on FPGA M. Bautista-Palacios, L. Baldez, J. Sempere-Agulló, A. Herms-Berenguer, F. Cardells-Tormo, and P.-L. Molinet

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6.A: Defect Tolerance Defect Tolerance in Multiple-FPGA Systems Z. Hyder and J. Wawrzynek Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement A.J. Yu and G.G.F. Lemieux

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6.B: Compilation Methods 1 Heterogeneity Exploration for Multiple 2D Filter Designs C.-S. Bouganis, P.Y.K. Cheung, and G.A. Constantinides Highly Automated FPGA Synthesis of Application-Specific Protocol Processors S. Virtanen, D. Truscan, J. Paakkulainen, J. Isoaho, and J. Lilius

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6.C: Cryptography Applications Ziggurat-based Hardware Gaussian Random Number Generator G. Zhang, P.H.W. Leong, D.-U Lee, J.D. Villasenor, R.C.C. Cheung, and W. Luk

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Snow 2.0 IP Core for Trusted Hardware W.H. Fang, T. Johansson, and L. Spaanenburg

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7.A: Asynchronous Architectures A Novel Asynchronous FPGA Architecture Design and its Performance Evaluation X. Jia and R. Vemuri A Programmable Logic Architecture for Prototyping Clockless Circuits L. Fesquet and M. Renaudin GALS Systems Prototyping using Multiclock FPGAs and Asynchronous Network-on-Chips J. Quartana, S. Renane, A. Baixas, L. Fesquet, and M. Renaudin

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7.B: Compilation Methods 2 A Verilog RTL Synthesis Tool for Heterogeneous FPGAs P. Jamieson and J. Rose

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Compilation and Management of Phase-Optimized Reconfigurable Systems H. Styles and W. Luk

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Trident: An FPGA Compiler Framework for Floating-Point Algorithms J.L. Tripp, K.D. Peterson, C. Ahrens, J.D. Poznanovic, and M. Gokhale

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7.C: Bio-Inspired Computing FPGA-Accelerated Bayesian Learning for Reconstruction of Gene Regulatory Networks I. Pournara, C.-S. Bouganis, and G.A. Constantinides

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Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata P. Zipf, O. Soffke, A. Schumacher, R. Dogaru, and M. Glesner

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A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata P. Zipf, O. Soffke, A. Schumacher, C. Schlachta, R. Dogaru, and M. Glesner

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8.A: System Architecture Exploration and Evaluation Generation and Exploration of Reconfigurable Architectures using Mathematical Programming A.M. Smith, G.A. Constantinides, and P.Y.K. Cheung

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An I/O mechanism on a Dynamically Reconfigurable Processor – Which should be moved: Data or Configuration? H. Amano, S. Abe, K. Deguchi, and Y. Hasegawa

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Cluster Architecture for Reconfigurable Signal Processing Engine for Wireless Communication M. Saito, H. Fujisawa, N. Ujiie, and H. Yoshizawa

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8.B: Communication Synthesis and High Level Design Communication Synthesis in a Multiprocessor Environment C. Zissulescu, B. Kienhuis, and E. Deprettere

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PGR : A Software Package for Reconfigurable Super-Computing T. Hamada and N. Nakasato

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On-Chip Communication Topology Synthesis for Shared Multi-Bus Based Architecture S. Pandey, M. Glesner, and M. Mühlhäuser

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8.C: MPEG Applications A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC O. Lehtoranta, E. Salminen, A. Kulmala, M. Hännikäinen, and T.D. Hämäläinen Configurable Hardware Implementation of a Conceptual Decoder for a Real-Time MPEG-2 Analysis M. Janiaut, C. Tanougast, H. Rabah, Y. Berviller, C. Mannino, and S. Weber Memory Efficient Design of an MPEG-4 Video Encoder for FPGAs K. Denolf, A. Chirila-Rus, R. Turney, P. Schumacher, and K. Vissers

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9.A: Fault Tolerant Architectures and Systems An Autonomous FPGA-based Emulation System for Fast Fault Tolerant Evaluation C. López-Ongil, M. García-Valderas, M. Portela-García, and L. Entrena-Arrontes On the Reliability Evaluation of SRAM-Based FPGA Designs O. Héron, T. Arnaout, and H.-J. Wunderlich Yield Modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes N. Campregher, P.Y.K. Cheung, G.A. Constantinides, and M. Vasilko

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9.B: Placement Fast FPGA Placement using Space-filling Curve P. Banerjee, S. Bhattacharjee, S. Sur-Kolay, S. Das, and S.C. Nandy

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Hierarchical Placement for Large-scale FPAA I.F. Baskaya, S. Reddy, S.K. Lim, and D. Anderson

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Architecture-Adaptive Routability-Driven Placement for FPGAs A. Sharma, C. Ebeling, and S. Hauck

427

9.C: Security Attacks and Detection Generalizing Square Attack using Side-Channels of an AES Implementation on an FPGA V. Carlier, H. Chabanne, E. Dottax, and H. Pelletier

433

Real-Time Feature Extraction for High Speed Networks D. Nguyen, G. Memik, S. Ogrenci Memik, and A. Choudhary

438

Bitwise Optimised CAM for Network Intrusion Detection Systems S. Yusuf and W. Luk

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10.A: Video Processing Architectures and Systems High Speed / Low Power Architectures for the Finite Radon Transform S. Chandrasekaran and A. Amira

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Towards a Reconfigurable Tracking System S. Wong, M. Jasiunas, and D. Kearney

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High Performance Stereo Computation Architecture J. Díaz, E. Ros, S. Mota, E.M. Ortigosa, and B. del Pino

463

10.B: Emulation and Simulation An Emulation Model for Sequential ATPG-Based Bounded Model Checking Q. Qiang, D.G. Saab, F. Kocan, and J.A. Abraham

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Accelerating Molecular Dynamics Simulations with Configurable Circuits Y. Gu, T. VanCourt, and M.C. Herbordt

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A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits V. Gonçalves, J.T. de Sousa, and F. Gonçalves

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10.C: Networking Applications 2 An FPGA-based Soft Multiprocessor System for IPv4 Packet Forwarding K. Ravindran, N. Satish, Y. Jin, and K. Keutzer

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Snort Offloader: A Reconfigurable Hardware NIDS Filter H. Song, T. Sproull, M. Attig, and J. Lockwood

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HAIL: A Hardware-Accelerated Algorithm for Language Identification C.M. Kastner, G.A. Covington, A.A. Levine, and J.W. Lockwood

499

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Poster Session 1 A Run-Time Reconfigurable Hardware Infrastructure for IP-Core Evaluation and Test R. Siripokarpirom

505

A High Performance Hardware Architecture for an SAD Reuse based Hierarchical Motion Estimation Algorithm for H.264 Video Coding S. Yalcin, H.F. Ates, and I. Hamzaoglu

509

Statistical Power Estimation for FPGAs E. Todorovich, F. Angarita, J. Valls, and E. Boemo

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CPU-independent Assembler in an FPGA G. Acher, R. Buchty, and C. Trinitis

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Design and Test Methodology for a Reconfigurable PEM Data Acquisition Electronics System C. Leong, P. Bento, P. Rodrigues, A. Trindade, J.C. Silva, P. Lousã, J. Rego, J. Nobre, J. Varela, J.P. Teixeira, and I.C. Teixeira

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Dynamic Reconfiguration with Hardwired Networks-on-Chip on Future FPGAs R. Hecht, S. Kubisch, A. Herrholtz, and D. Timmermann

527

Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks A. García, J. Ramírez, U. Meyer-Baese, E. Castillo, and A. Lloris

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Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates F. Angarita, A. Perez-Pascual, T. Sansaloni, and J. Valls

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Efficient Hardware Architectures for Modular Multiplication on FPGAs D.N. Amanor, V. Bunimov, C. Paar, J. Pelzl, and M. Schimmler Energy Management in Battery-Powered Sensor Networks with Reconfigurable Computing Nodes J. Khan and R. Vemuri

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FPGA Implementation of an Area-Time Efficient FIR Filter Core using a Self-Clocked Approach J.J. Martínez, F.J. Toledo, F.J. Garrigós, and J.M. Ferrández

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Optimization of Start-Up Time and Quiescent Power Consumption of FPGAs A. Schiefer and U. Kebschull

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QPF: Efficient Quadratic Placement for FPGAs Y. Xu and M.A.S. Khalid

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Safe PLD-based Programmable Controllers J. Alvarez, J. Marcos, and S. Fernandez

559

Performance and Energy Analysis of Task-Level Graph Transformation Techniques for Dynamically Reconfigurable Architectures J. Noguera and R.M. Badia

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Poster Session 2 A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware K. Danne and M. Platzner A Framework for ODE-Based Multimodel Biochemical Simulations on an FPGA Y. Osana, Y. Iwaoka, T. Fukushima, M. Yoshimi, A. Funahashi, N. Hiroi, Y. Shibata, N. Iwanaga, H. Kitano, and H. Amano Area-Efficient 2-D Shift-Variant Convolvers for FPGA-based Digital Image Processing F. Cardells-Tormo, P.-L. Molinet, J. Sempere-Agulló, L. Baldez, and M. Bautista-Palacios Design and FPGA Implementation of an Embedded Real-Time Biologically Plausible Spiking Neural Network Processor M.J. Pearson, C. Melhuish, A.G. Pipe, M. Nibouche, I. Gilhesphy, K. Gurney, and B. Mitchinson Evaluation Strategies for Coarse Grained Reconfigurable Architectures H. Lange and H. Schröder

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Figaro – An Automatic Tool Flow for Designs with Dynamic Reconfiguration K. Nasi, M. Danˇek, T. Karoubalis, and Z. Pohl FPGA Implementation of a GF (24M ) Multiplier for use in Pairing Based Cryptosystems M. Keller, T. Kerins, and W. Marnane FPGA’s Middleware for Software Defined Radio Applications X. Revés, V. Marojevic, R. Ferrús, and A. Gelonch Implementation of Ranking Filters on General Purpose and Reconfigurable Architecture Based on High Density FPGA Devices D. Milojevic Integration of a NoC-Based Multimedia Processing Platform T. Ahonen and J. Nurmi

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LAMP: A Tool Suite for Families of FPGA-Based Computational Accelerators T. VanCourt and M.C. Herbordt

612

Low Power Domain-Specific Reconfigurable Array for Discrete Wavelet Transforms Targeting Multimedia Applications S. Baloch, I. Ahmed, T. Arslan, and A. Stoica

618

Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture B. Mei, F.-J. Veredas, and B. Masschelein

622

Parameterized Logic Power Consumption Models for FPGA based Arithmetic J.A. Clarke, A.A. Gaffar, and G.A. Constantinides

626

Performance Improvements using Coarse-Grain Reconfigurable Logic in Embedded SoCs G. Dimitroulakos, M.D. Galanis, and C.E. Goutis

630

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Poster Session 3 A Configuration Memory Architecture for Fast Run-Time Reconfiguration of FPGAs U. Malik and O. Diessel

636

A Novel Toolset for the Development of FPGA-like Reconfigurable Logic A. Danilin, M. Bennebroek, and S. Sawitzki

640

A Reconfigurable Perfect-Hashing Scheme for Packet Inspection I. Sourdis, D. Pnevmatikatos, S. Wong, and S. Vassiliadis

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An Efficient Approach to Hide the Run-Time Reconfiguration from SW Applications Y. Qu, J.-P. Soininen, and J. Nurmi An FPGA Network Architecture for Accelerating 3DES – CBC C.M. Wee, P.R. Sutton, and N.W. Bergmann An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform K. Siozios, K. Tatas, G. Koutroumpezis, D. Soudris, and A. Thanailakis Coping with Uncertainty in FPGA Architecture Design B. Ratchev, M. Hutton, and D. Mendel Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel Biochemical Simulation on an FPGA N. Iwanaga, Y. Shibata, M. Yoshimi, Y. Osana, Y. Iwaoka, T. Fukushima, H. Amano, A. Funahashi, N. Hiroi, H. Kitano, and K. Oguri

648

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Finite Field Division Implementation J.-P. Deschamps and G. Sutter

670

FPGA-Aware Garbage Collection in Java P. Faes, M. Christiaens, D. Buytaert, and D. Stroobandt

675

High-Throughput Reconfigurable Computing: Design and Implementation of an IDEA Encryption Cryptosystem on the SRC-6E Reconfigurable Computer A. Michalski, K. Gaj, and D. Buell

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Magnetic Remanent Memory Structures for Dynamically Reconfigurable FPGA N. Bruchon, G. Cambon, L. Torres, and G. Sassatelli

687

Mullet – A Parallel Multiplier Generator K.H. Tsoi and P.H.W. Leong

691

NetFlow Probe Intended for High-Speed Networks M. Žádník, T. Peˇcenka, and J. Koˇrenek

695

Performance Tuning of Iterative Algorithms in Signal Processing Z. Pohl, P. Š˚ucha, J. Kadlec, and Z. Hanzálek

699

Run-Time Scheduling for Random Multi-Tasking in Reconfigurable Coprocessors P. Benoit, J. Becker, M. Robert, L. Torres, G. Sassatelli, and G. Cambon

703

PhD Forum A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow Konstantinos Siozios, D. Soudris, and A. Thanailakis

707

A Power-Performance Scalable FPGA using Configurable Voltage Domains and Design Mapping Tool Frank Honoré and A. Chandrakasan

709

An Approach to Scalable Molecular Dynamics Simulation using Supercomputing Adaptive Processing Elements Luis E. Cordova and D.A Buell

711

Computer Arithmetic Synthesis Technologies on Reconfigurable Platforms Kuen Hung Tsoi Dual FiXed-point: An Efficient Alternative to Floating-point Computation for DSP applications Chun Te Ewe Efficient Execution on Reconfigurable Devices using Concepts of Pipelining Florian Dittmann xxx

713

715

717

Exploration of Heterogeneous Reconfigurable Architectures A.M. Smith

719

FPGA Finite Difference Time Domain Solver for Thermal Simulation Fernando Pardo, P. López, D. Cabello, and M. Balsi

721

FPGA Implementation of an Augmented Reality Application for Visually Impaired People F. Javier Toledo, J.J. Martínez, F.J. Garrigós, and J.M. Ferrández

723

725

FPGA Interconnect Fault Tolerance Nicola Campregher Hardware Emulation of a Network on Chip Architecture based on a Clockwork Routed Manhattan Street Network Kurian Oommen and D. Harle

727

Instruction Set Extension using Microblaze Processor János Lazányi

729

Leveraging Reconfigurability in the Design Process Lesley Shannon

731

MechanoProcessor: Modelling the Rodent Whisker Sensory System using FPGA Martin J. Pearson

733

Next Generation Architectures and CAD for Power Aware Programmable Fabrics Rajarshee P. Bharadwaj

735

PAHLS: Towards Run-Time Synthesis for FPGAs Renqiu Huang and R. Vemuri

739

Reconfigurable Architectures for Real-Time Network Anomaly Detection David Nguyen

741

Requested-QoS Driven Runtime Reconfiguration Of Mobile Devices Hiren Joshi, S.S. Verma, and G.K. Sharma

743

xxxi

Design of a Dynamic Reconfigurable Multi-Grained Hardware Architecture with Adaptive Runtime Routing Alexander Thomas

745

Testing Superscalar Processors in Functional Mode Virendra Singh, M. Inoue, K.K. Saluja, and H. Fujiwara

747

Author Index

751

xxxii