Design of a CMOS Low-Power Low-Frequency Oscillator
Kumamoto University 12th June 2006 – 5th September 2006
Academic advisor at ENSEIRB : Mr Yann DEVAL Academic advisor at Kumamoto University : Pr Takahiro INOUE Student Name : Nicolas LAFITTE Department : Electronics
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TABLE OF CONTENTS THANKS ...........................................................................................................................................................3 PART 1.
INTRODUCTION ........................................................................................................................4
PART 2.
KUMAMOTO UNIVERSITY GRADUATE SCHOOL OF SCIENCE AND TECHNOLOGY ...5
2.1 2.2 2.3 2.4 PART 3. 3.1 3.2 PART 4.
GENERAL INFORMATIONS ...................................................................................................................5 RESEARCH DEPARTMENTS .................................................................................................................5 DEPARTMENT OF ELECTRICAL AND COMPUTER SCIENCE ..................................................................6 DIVISION OF ELECTRONIC AND COMMUNICATION SYSTEMS .............................................................6 GOAL AND REQUIRED SPECIFICATIONS .........................................................................7 GOAL...................................................................................................................................................7 REQUIRED SPECIFICATIONS ................................................................................................................8 PROJECT REALIZATION ........................................................................................................9
4.1 PROJECT SPECIFICATION ANALYSIS ...................................................................................................9 4.3 DETAILED DESIGN ............................................................................................................................11 4.3.1 Current Source Circuit.............................................................................................................11 4.3.2 Current Control Circuit ...........................................................................................................11 4.3.3 Level Control Circuit ...............................................................................................................11 4.4 SIMULATION RESULTS ......................................................................................................................13 4.5 RESULTS ...........................................................................................................................................17 PART 5.
CONCLUSION ...........................................................................................................................18
PART 6.
BIBLIOGRAPHY ......................................................................................................................19
PART 7.
APPENDICES.............................................................................................................................20
TABLE OF FIGURES Fig. 1 Block diagram of the ultrasonic distance measurement system..............................................................7 Fig. 2 Proposed circuit (1)...............................................................................................................................10 Fig. 3 Proposed circuit (2)...............................................................................................................................10 Fig. 4 NMOS OTA ............................................................................................................................................12 Fig. 5 PMOS OTA ............................................................................................................................................12 Fig. 6 Schmitt trigger circuit............................................................................................................................12 Fig. 7 Sawtooth output and Power consumption at 25°C................................................................................13 Fig. 8 Slope linearity at 25°C ..........................................................................................................................13 Fig. 9 Sawtooth output and Power consumption at -20°C..............................................................................14 Fig. 10 Slope linearity at -20°C ......................................................................................................................14 Fig. 11 Sawtooth output and Power consumption at 60°C.............................................................................15 Fig. 12 Slope linearity at 60°C .......................................................................................................................15 Fig. 13 Power consumption (1)........................................................................................................................16 Fig. 14 Power consumption (2)........................................................................................................................16 Fig. 15 Schmitt trigger simulations results ......................................................................................................17
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Thanks
•
To Professor Inoue who has welcome me in his laboratory. I thank him for the moments spent together and for all his advices.
•
To Felix Timischl who has welcome me in his project. I thank him for his welcome and his availability for me
•
To all laboratory students for their welcome and for all the unforgettable moments spent together.
•
To Mr Deval, my ENSEIRB advisor, for his availability and his effective assistance when I needed for it.
•
To Mr Azzopardi who made this experience possible.
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PART 1. INTRODUCTION Thanks to the relations of the school, I could carry out my second year internship in Japan in the University of Kumamoto. It was important for me to find an internship in a foreign country. To see another working methods. To see another culture. To see my abilities of adaptation especially. It was a chance for me to integrate a laboratory into Japan. Culturally, it was amazing and unforgettable. Scientifically, I was in one of the best countries to learn still more in electronics and microelectronics. In this second year of study, I planned to choose “Integrated circuits and systems” courses to carry on with my formation. That’s why I chose a design project which deals with microelectronics in the laboratory of Professor Inoue. I was integrated in the project led by Felix Timischl. He is working on the design of a CMOS low-voltage low-power circuit for an integrated pulsed ultrasonic distance measurement system. He proposes an ultrasonic distance measurement system for obstacle detection. The circuit is completely realized with CMOS hardware components. The whole circuit must work at a power supply of 0.9 V and must not dissipate more power than existing systems. The majority of systems available uses microcontrollers. It implies a worse power consumption and integrability. For the moment, the system does not dissipate more than 267 µW, but around 98% are dissipated by the low-frequency oscillator.
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PART 2. KUMAMOTO UNIVERSITY GRADUATE SCHOOL OF SCIENCE AND TECHNOLOGY 2.1
General Informations
The new Graduate School of Science and Technology was initiated in its present form in April 1988 as one of the eight graduate schools at Kumamoto University. It is an independent graduate school of advanced study and research offering two years of Master's program and three years of Doctoral program in natural science, engineering and related fields. The Kumamoto University Graduate School of Science and Technology, based on the foundations of Faculty of Science (1949) and Faculty of Engineering (1887), was established in 1988 and restructured in 2000 under a new concept of professional education and research. The aim of the Graduate School is to foster breadth and depth of knowledge, creativity, flexibility of judgment, and leadership among those with science and engineering backgrounds so as to effectively meet the challenges of a fast-paced and rapidly changing society.
2.2
Research Departments
There are eight departments for Master program and four for Doctoral program. Each department comprises two to eight divisions, and each division consists of three to six areas of instruction and research. Master Course Departments: Department of Science and Technology for Chemistry and Physics Department of Materials Science and Technology Department of Mechanical Engineering Department of Mathematics and Computer Science Department of Electrical and Computer Science Department of Systems in Natural Environment Department of Civil and Environmental Engineering Department of Architecture Doctoral Course Departments: Department of Industrial Science Department of Systems and Information Department of Environmental Science Department of Materials and Life Science Nicolas LAFITTE
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Department of Electrical and Computer Science
This department consists of three divisions and one endowed division: Electrical Energy Systems, Electronic and Communication Systems, Advanced Technology of Electrical and Computer Systems, and Advanced Technology for Electrical Energy (endowed division). This department provides a wide scope of education and research on electrical engineering, electronics, and communication systems. The education and research programs of this department treat the above areas synthetically and systematically, extending from the fundamentals to the advanced technologies. Recent developments in scientific technology have been supported in large part by the giant strides taken in electrical engineering. This department offers fundamental and state-of-the-art studies for future high-level engineers and pioneers in the dynamic field of electrical engineering.
2.4
Division of Electronic and Communication Systems
This division consists of four education and research areas: Electronic Devices, Intelligent Circuits and Systems, Optoelectronics, and Information Measurement and Processing. This division provides education and research programs covering the fundamentals and applications of a wide scope of the following fields: Acoustic and Image Signal Processing; Analog and Digital Circuits Design and Its Application for Intelligent Systems and Signal Processors; Theory, Design, and Development of Superconductivity and Semiconductor Devices; and Optoelectronics and Sensing/Imaging. Staff Professors Prof. K. Miyahara Prof. T. Inoue Prof. M. Nishimoto Prof. K. Sugitani Associate Professors Assoc. Prof. A. Tsuneda Assoc. Prof. T. Fujiyoshi Assoc. Prof. K. Ogata Subdivisions • Electronic Devices Elemental functions and applications of electronic devices are lectured based on solid state physics. • Intelligent Circuits and Systems Design, development, and application of analog/digital circuits and systems, intelligent circuits and systems, and chaos systems are lectured. • Optoelectronics Applied electromagnetics; optical and microwave communication systems; optical and microwave sensing and imaging technology. • Information Measurement and Processing Education and research on digital processing of signal (time series or one-dimensional) and image (multi-dimensional) and measuring technology of various physical quantity (information) in the engineering. Nicolas LAFITTE
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PART 3. GOAL AND REQUIRED SPECIFICATIONS 3.1
Goal
A design of a CMOS Low Frequency Oscillator has to be proposed. The proposed design should be used in an ultrasonic distance measurement system. Obstacle detection is based on the principle of reflection of ultrasonic waves on the obstacle. One of the ultrasonic waves employing methods is the Time-of-Flight method. Basically, the Time-ofFlight method measures the time delay between emission and reception of a pulse of ultrasonic waves.
Fig. 1 Block diagram of the ultrasonic distance measurement system The high-frequency oscillator generates a 40 kHz signal, VHFOUT, which is ASK modulated by a low-frequency signal, VLFOUT, of around 40 Hz driving an ultrasonic emitter circuit. The PLL and the lock-in detector form a frequency-selective stage performing a frequency comparison between the emitted and received ultrasonic signal. Nicolas LAFITTE
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The lockin-detector outputs a spike VSPIKE in case of PLL’s lock-in to the emitter frequency, switching through the instantaneous value of low-frequency oscillator’s ramp signal VR to the sample-hold circuit. The output VTOF of the sample-hold circuit is directly proportional to the TOF and namely, to the distance [Timischl] (Appendix 3).
3.2
Required Specifications
The proposed circuit must provide a rectangular signal (VLFOUT) and a sawtooth signal (VR) at 40Hz. The rectangular signal can be used to control an ASK circuit, when the sawtooth signal can measure time and therefore distance. Knowing the time between emission and reception, the distance can be deduced. Consequently a perfect linear signal (depending with time) is required. Therefore the two outputs should be synchronous. No delay derivation between signals are allowed to ensure distance measurements. Otherwise, the precision on the frequency and the duty cycle is not required. 40Hz is an indication. The frequency can be included between 35 Hz and 45 Hz without problem on distance measurements. 2d = v
T 2
(1)
Assuming v = 340 m/s and T = 40 Hz, one obtains d = 2.125 m as the maximum detectable distance, which is sufficient for the use as a subsidiary orientation system for disabled people in a building or outdoor. The ASK modulation signal duty cycle should be small, to improve the system power consumption, included between 10% and 20%. On the other hand, the linear ramp must be the same in spite of the conditions. To ensure a consistent distance measurement, the sawtooth signal should not depend on the temperature and supply variations. Finally, the proposed circuit must work at 0.9V supply voltage. The power dissipation must be lower than 40µW. And the occupied chip area must be optimized.
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PART 4. PROJECT REALIZATION 4.1
Project Specification Analysis
An oscillator is one of the important basic building blocks in a system. There are many implementations of oscillators. • LC Oscillators For this frequency, big L and C element values are required. In order to optimize chip area, it is only allowed capacitor values lower than 20 pF. This kind of oscillators is not a suitable solution. • RC Oscillators In this case, the circuit can theoretically provide a rectangular and a sawtooth signal. In order to obtain the required frequency, current and capacitor value have to be well chosen. Problems will come from the capacitor implementation (< 20 pF) and the power consumption of the circuit. • Ring Oscillators Ring oscillators are often used in CMOS implementation. They can provide a width range of frequencies. In this case, the design has to increase the delay between inverter stages in order to obtain a total delay of 25 ms.
4.2
General Design
Currently, the low-frequency oscillator is an astable multivibrator [Timischl06]. But the power consumption is too high and represents 98% of the system power consumption. A new circuit is proposed. A current source charges a low capacitance, and a voltage level control circuit control the charge or the discharge of the capacitance. Then a current control circuit is designed to ensure a supply and temperature independency.
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Fig. 2 Proposed circuit (1) The two outputs required are on the input and the output of the Schmitt trigger. The sawtooth signal can be found on capacitor terminals. And the pulse signal is given by the level control circuit.
Fig. 3 Proposed circuit (2) HSPICE simulations were performed for each of the circuits described using the level-49 device model under the assumption that a standard 0.35 µm 2-poly 4-metal CMOS process is used. All simulations are performed at 0.9 V supply voltage.
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Detailed Design
4.3.1 Current Source Circuit The main stage of the circuit is a simple PMOS current mirror. The current source circuit charge a capacitor with a constant current. The current is about 200 pA. A perfect constant current allows a linear signal on capacitor terminals. Nevertheless, when the capacitor voltage increases, the drain to source M3 voltage decreases. When this voltage approaches 0.3 V, M3 becomes saturated and the drain current depends on other parameters. The output signal is no more perfectly linear. The sawtooth signal maximum excursion is maximum 0.6 V. The current mirror is composed of two PMOS transistors M2 and M3 which have the same dimensions W = 6 µm and L = 4 µm. Therefore, the current gain is 1. A NMOS transistor M1 is used as a current source. The current is controlled by the gate voltage.
4.3.2 Current Control Circuit A current control circuit is necessary to ensure the same linear slope, independently of the conditions. Distance measurements should be consistent, independently of the ambient and the working temperature. A preliminary research on the current source circuit gives the characteristics of the necessary feed back. The common point of the current mirror gives an image of the temperature. Knowing the temperature, the slope can be controlled by the current, and therefore by M1. The current control circuit, formed by Mc1 and Mc2, is designed to reduce the current when the temperature increases. The dimensions of the MOS transistors and Vbias are designed to ensure preliminary research characteristics. Vbias is about 750 mV.
4.3.3 Level Control Circuit The level control circuit is composed by a Schmitt Trigger ordering a transistor of discharge. The discharge transistor is a simple NMOS transistor, which is, often OFF, and during a short time ON, allowing a quick discharge of the capacitance. On the first simulations, the Schmitt Trigger was simulated by a 40 Hz square signal. The trigger was simulated alone. Its design became complicated. The aim was to ensure the better dynamic capabilities, i.e. it would be able to compare the input signal with reference voltages included between 0 and 0.6 V. The main circuit of the trigger is an Operational Transconductance Amplifier [Deval] (Appendix 4). NMOS and PMOS Differential Pair have, respectively, dynamic capabilities included in high and low voltages of the 0.9 supply voltage.
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Fig. 5 PMOS OTA
Fig. 4 NMOS OTA
A NMOS and PMOS OTA (Fig. 4 and 5) will respectively be used to compare the input with the high and the low reference voltages (about 0.6 V and 0 V).
Fig. 6 Schmitt trigger circuit According to the output, the trigger compares the input with the NMOS or the PMOS differential pair.
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Simulation Results
Simulations were done in two steps: all the circuit without the Schmitt trigger and the Schmitt trigger alone. The whole circuit was simulated at three different temperatures (-20 °C, 25 °C and 60 °C). Fig. 7, 8, 9, 10, 11 and 12 shows the simulation results of the circuit without the trigger.
Fig. 7 Sawtooth output and Power consumption at 25°C
Fig. 8 Slope linearity at 25°C Fig. 7 and 8 shows the simulation results at 25°C. Output amplitude, output slope linearity and power dissipation are satisfactory. The rising slope of the sawtooth signal is 20.8 V/s. I.e. for an output amplitude of 500 mV, the output frequency will be 41.6 Hz.
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Fig. 9 Sawtooth output and Power consumption at -20°C
Fig. 10 Slope linearity at -20°C Fig. 9 and 10 shows the simulation results at -20°C. Output amplitude, output slope linearity and power dissipation are, also, satisfactory. The rising slope of the sawtooth signal is 18.7 V/s. I.e for an output amplitude of 500 mV, the output frequency will be 37.4 Hz.
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Fig. 11 Sawtooth output and Power consumption at 60°C
Fig. 12 Slope linearity at 60°C Fig. 11 and 12 shows the simulation results at 60°C. Output amplitude, output slope linearity and power dissipation are, also, satisfactory. The rising slope of the sawtooth signal is 22.4 V/s. I.e for an output amplitude of 500 mV, the output frequency will be 44.8 Hz. Consequently the temperature dependency on the output frequency is 0.0925 Hz/°C. During the different simulations, power consumption peaks have been seen. They are caused during the discharge of energy stored in the capacitor (Fig. 13).
p (t ) = ( Pmax − Pmin )e
−
t
τ
+ Pmin
(2)
It is necessary to know how large and high peaks are.
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Fig. 13 Power consumption (1) A fine simulation (Fig. 14) makes possible to characterize the power function. The time is deduced by two points P1 and P2 : τ = 71.229 ns.
Fig. 14 Power consumption (2) Then Pmax is deduced: Pmax = 8.622 µW. On the other hand, we can see the peak is not larger than 200 ns. Therefore the average power can be deduced.
P=
Nicolas LAFITTE
200 ns ⋅9 µW 2
+ 25ms ⋅ 2.25 µW ≈ 2.25 µW 25ms
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Then the design of the Schmitt trigger was simulated alone.
Fig. 15 Schmitt trigger simulations results Fig. 15 shows inputs (Vin1 and Vin2) and output (Vout) of the trigger, and also two internals signals. Vnmos and Vpmos depend on the output level. They select the required OTA output for this voltage level of comparison. The power consumption is satisfactory. It is no more than 13 µW. On the simulations, some glitches appear. They occur when the PMOS differential pair is selected.
4.5
Results
The first part of the design works according to the required specifications. Nevertheless, the level control circuit is not finished. The Schmitt trigger does not fulfil the specifications. Its functioning is not correct and the design is complicated. On the contrary, the estimated consumption, of the whole circuit, is no more than 20 µW. The glitches can be deleted modifying some elements of the Schmitt trigger circuit. The modifications done, simulations look satisfactory. The positive input must be connected to the reference voltage. Some voltage values between 0.35 V and 0.45 V engender glitches, because of the bad dynamic capabilities of the PMOS differential pair. Two solutions are possible. The Schmitt trigger must be used with references between 0 and 0.35 V, and between 0.45 V and 0.9 V. But this solution is uncertain and dangerous. Or it is better to modify the design of the logic gates, in order to change the threshold voltage from 0.45 V to 0.35 V. The PMOS differential pair will be selected for voltages under 0.35 V.
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PART 5. CONCLUSION
The design of a CMOS low-power low-frequency oscillator is not finished. On the one hand, it is not sure that the two blocks, simulated together, will fulfil all the specifications: on functioning and on consumption. On the other hand, after that, Monte-Carlo simulations have to be done to validate the design and the layout has to be finished. Finally, improvements can be added to improve temperature and, especially, supply independency. Unfortunately, all the design work is not finished. Nevertheless, this internship stays an interesting experience. Firstly, the internship subject is what I was waiting for. The microelectronic design corresponds with what I would like to do in the future. The work did not disappoint me. I could realize what it was, what I knew, and what I had to learn. Then, my wish to work in a foreign country was realized. I wanted to live great human experience, and to be confronted with new working methods. Without doubt, it is the best thing it happened. I discovered a new culture, spoke different languages, took part in weekly seminars, met many persons, lived new experiences … But, above all, I had to adapt to a new social and working environment. I think this aspect is a real success. I did not meet any problems to live, to work and to enjoy, during my stay.
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PART 6. BIBLIOGRAPHY [Timischl]
F. Timischl, T. Inoue, “Design of a CMOS Low-Voltage Low-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement System”, 2006.
[Deval]
Y. Deval, “Operational Amplifier Models”, 2006.
[1]
Paul R. Gray and Robert G. Meyer, “Analysis and Design of Analog Integrated Circuits”, Wiley.
[2]
Phillip E. Allen and Douglas R. Holberg, “CMOS Analog Circuit Design (Second Edition)”, Oxford.
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PART 7. APPENDICES 1. French Report Summary. N. Lafitte, 2006.
2. Presentation “Design of a CMOS Low-Power Low-Frequency Oscillator”. N. Lafitte, Kumamoto University, 4th August 2006.
3. “Design of a CMOS Low-Voltage Low-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement System”. F. Timischl, T. Inoue, Kumamoto University, 2006.
4. Operational Amplifier Models. Y. Deval, 2006.
5. SPICE Simulation Files, Main Circuit N. Lafitte, 2006. 6. SPICE Simulation Files, Schmitt Trigger Circuit N. Lafitte, 2006.
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Appendix 1 French Report Summary, N. Lafitte, 2006.
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Conception Microélectronique d’un Oscillateur faible fréquence faible alimentation
Université de Kumamoto 12 Juin 2006 – 5 Septembre 2006
Nom du tuteur : Mr Yann DEVAL Nom du maître de stage : Pr Takahiro INOUE Nom de l’étudiant : Nicolas LAFITTE Département : Electronique Nicolas LAFITTE
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TABLE DES MATIERES
REMERCIEMENTS.......................................................................................................................................... PARTIE N°1.
INTRODUCTION................................................................................................................
PARTIE N°2.
UNIVERSITÉ DE KUMAMOTO GRADUATE SCHOOL OF SCIENCE AND TECHNOLOGY……..
2.1 2.2 2.3 2.4
INFORMATIONS GENERALES ............................................................................................................... DEPARTEMENTS DE RECHERCHE......................................................................................................... DEPARTEMENT GENIE ELECTRIQUE ET INFORMATIQUE ..................................................................... DIVISION SYSTEMES ELECTRONIQUES ET DE COMMUNICATIONS ......................................................
PARTIE N°3. 3.1 3.2
SUJET DE STAGE .................................................................................................................................. CAHIER DES CHARGES .........................................................................................................................
PARTIE N°4. 4.1 4.2 4.2.1 4.2.2 4.2.3 4.3 4.4
OBJECTIFS DE LA MISSION TECHNIQUE.................................................................
REALISATION DU PROJET ............................................................................................
CONCEPTION GENERALE ..................................................................................................................... CONCEPTION DETAILLEE ..................................................................................................................... Source de Courant ...................................................................................................................... Control de Courant ..................................................................................................................... Control de Tension ..................................................................................................................... RESULTATS DE SIMULATIONS ............................................................................................................. RESULTATS ..........................................................................................................................................
PARTIE N°5.
CONCLUSION.....................................................................................................................
TABLE DES FIGURES Fig. 1 Diagramme fonctionnel du système de mesure de distance par ultrasons ................................................................. Fig. 2 Circuit proposé........................................................................................................................................................... Fig. 3 Schmitt Trigger........................................................................................................................................................... Fig. 4 Signal en dent de scie et Consommation à température ambiante ............................................................................. Fig. 5 Consommation de puissance du circuit...................................................................................................................... Fig. 6 Résultats de simulation du Trigger de Schmitt...........................................................................................................
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Remerciements •
Au Professeur Inoue qui m’a accueilli dans son laboratoire. Je le remercie pour tous les moments passés ensemble et tous ses conseils avisés.
•
A Mr Felix Timischl qui m’a accueilli dans son projet. Je le remercie de son accueil et de sa disponibilité à mon égard.
•
Tous les étudiants du laboratoire pour leur accueil et tous les moments inoubliables vécus ensemble.
•
A Mr Deval, mon tuteur, pour sa disponibilité et son aide efficace lorsque j’en ai eu besoin.
•
A Mr Azzopardi qui a rendu cette expérience possible.
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PARTIE N°1. INTRODUCTION
Grâce aux relations de l’école, j’ai pu réaliser mon stage de seconde année au Japon, dans l’Université de Kumamoto. Il était important pour moi de trouver un stage dans un pays étranger. Pour expérimenter de nouvelles méthodes de travail. Pour côtoyer une culture différente. Pour connaître mes aptitudes d’adaptation surtout. Ce fut une chance pour moi d’intégrer un laboratoire au Japon. Culturellement, ce fut une expérience incroyable et inoubliable. Scientifiquement, le Japon fut un des meilleurs pays pour continuer mon apprentissage de l’électronique et de la microélectronique. Durant cette deuxième année d’études à l’ENSEIRB, je prévoyais d’intégrer le cursus « Circuits et Systèmes Intégrés » pour poursuivre ma formation. C’est pourquoi j’ai choisi un projet de conception traitant de microélectronique dans le laboratoire du Professeur Inoue. Je fus accueilli dans le projet mené par Felix Timischl. Il travaille sur la conception, en technologie CMOS, d’un système de mesure de distance par impulsions d’ultrasons. Il propose un système, totalement intégré, de détection d’obstacles. Le circuit est complètement réalisé en technologie CMOS. Tout le circuit doit fonctionner avec une alimentation de 0.9 V et ne doit pas consommer plus que les modèles existants. La plupart des systèmes disponibles utilise des microcontrôleurs ou DSPs, impliquant de plus mauvaises consommation et intégrabilité. Pour le moment, le système ne dissipe pas plus de 267 µW, mais approximativement 98% est dissipé par l’oscillateur de faible fréquence.
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PARTIE N°2. UNIVERSITÉ DE KUMAMOTO GRADUATE SCHOOL OF SCIENCE AND TECHNOLOGY 2.1
Informations Générales
La nouvelle Graduate School of Science and Technology fut inaugurée dans la présente forme en Avril 1988 comme une des huit Ecoles de l’Université de Kumamoto. C’est une école indépendante d’études et de recherches universitaires, offrant deux années de Master et trois années de Doctorat dans les champs relatifs aux sciences naturelles et l’ingénierie. L’Ecole des Sciences et Technologies de l’Université de Kumamoto, basée sur les fondations de la Faculté de Sciences et de la Faculté d’Ingénierie, fut inaugurée en 1988 et restructurée en 2000 à partir d’un nouveau concept d’éducation et de recherche professionnelle. Le but de l’Ecole est d’impulser un nouvel élan et d’approfondir les connaissances, la créativité, la flexibilité et le leadership sur les domaines relatifs aux sciences et à l’ingénierie, afin de confronter efficacement les nouveaux challenges et les rapides changements de la société.
2.2
Départements de Recherche
L’Ecole est composée de huit départements de programmes de Master et de quatre de programmes de Doctorat, comprenant deux à huit divisions. Chaque division contient trois à six champs d’instructions et de recherches.
2.3
Département Génie Electrique et Informatique
Ce département contient trois divisions dont l’une dotée d’une division : Systèmes d’Energie Electrique, Systèmes Electronique et de Communications, Systèmes de Technologie Electrique Avancée et Informatiques et Technologie Avancée pour l’Energie Electrique. Ce département fournit de nombreuses possibilités de formations et de recherches en ingénierie électrique, électronique et des télécommunications. Les programmes d’éducation et de recherches traitent ces champs à partir des fondements jusqu’aux technologies actuelles.
2.4
Division Systèmes Electronique et de Communications
Cette division contient quatre aires d’éducation et de recherches : Circuits Electroniques, Systèmes et Circuits Intelligents, Optoélectronique et, Acquisition et Traitement d’Informations. Cette division fournit des programmes de formations et de recherches couvrant les fondements et les applications des nombreux champs suivants : Traitement du Signal (Image et Acoustique) ; Conception de Circuits Analogiques et Numériques et ses applications pour les Systèmes Intelligents ; Théorie, Conception, et Développement des Systèmes Semiconducteurs et Superconducteurs ; et Optoélectronique et Capteurs.
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PARTIE N°3. OBJECTIFS DE LA MISSION TECHNIQUE 3.1
Sujet de stage
La conception d’un oscillateur de faible fréquence en technologie CMOS doit être proposée. Le circuit proposé doit être utilisé dans un système de mesure de distance par ultrasons. La détection d’obstacles est basée sur le principe de réflexion des ondes ultrasons sur l’obstacle. Une des méthodes employée est la méthode Time-Of-Flight (TOF) ou « Temps de Vol ». Cette méthode mesure le temps entre l’émission et la réception d’une impulsion d’ondes.
Fig. 1 Diagramme fonctionnel du système de mesure de distance par ultrasons
3.2
Cahier des charges
Le circuit proposé doit fournir un signal carré (VLFOUT) et un signal en dent de scie (VR) de 40 Hz. Le signal carré est utilisé pour moduler en impulsions (ASK) le signal d’émission, alors que la rampe du signal en dent de scie permet la mesure du temps, et donc, de la distance. Connaissant le retard entre l’émission et la réception, la distance peut être déduite. Un signal parfaitement linéaire est nécessaire. Par conséquent, les deux sorties doivent être synchrones. Aucun retard entre les signaux n’est toléré pour assurer une bonne mesure. La précision sur la fréquence et sur le rapport cyclique des signaux n’est pas requise. Le rapport cyclique, contrôlant la modulation ASK et l’émission, doit néanmoins être petit (entre 10% et 20%) pour améliorer la consommation. D’autre part, la pente du signal VR doit être la même quelque soient les conditions. Pour assurer une mesure cohérente, la linéarité du signal ne doit pas dépendre de facteurs extérieurs. Enfin, le circuit proposé doit fonctionner avec une alimentation de 0.9 V. La consommation doit être inférieure à 40µW, et le layout optimisé. Nicolas LAFITTE
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PARTIE N°4. REALISATION DU PROJET 4.1
Conception générale
Actuellement, l’oscillateur faible fréquence est un multivibrateur astable. Mais sa consommation représente 98% de la consommation générale du système. Un nouveau circuit doit être proposé. Une source de courant charge une capacité de faible valeur, et un circuit comparateur contrôle la charge et la décharge de la capacité. Ensuite, un circuit contrôlant le courant assure l’indépendance vis-à-vis de la température et de l’alimentation.
Fig. 2 Circuit proposé Les deux signaux requis peuvent être pris à l’entrée et à la sortie du Trigger de Schmitt. Le signal en dent de scie se trouve aux bornes de la capacité. Le signal impulsionnel est donné par le circuit contrôlant le niveau de tension aux bornes de la capacité.
4.2
Conception détaillée
4.2.1 Source de Courant Le principal étage du circuit est un simple miroir de courant PMOS. La source de courant charge une capacité avec un courant constant. Le courant est à peu près de 200 pA. Un courant parfaitement constant assurerait un signal linéaire aux bornes de la capacité. Néanmoins, quand la tension aux bornes de la capacité augmente, la tension drain source de M3 diminue. Quand cette tension approche 0.3 V, M3 fonctionne en mode saturé. Alors le courant de drain dépend d’autres paramètres. La charge de la capacité n’est plus parfaitement linéaire. L’excursion maximum du signal est de 0.6 V. Un transistor NMOS M1 est utilisé comme source de courant. Le courant est contrôlé par la tension de grille. Nicolas LAFITTE
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4.2.2 Control de Courant Un circuit de contrôle de courant est nécessaire pour assurer la même pente du signal en dent de scie, quelque soient les conditions. La mesure de distance doit être consistante quelque soient la température ambiante et la température de travail. Une étude préliminaire sur le circuit source de courant donne les caractéristiques nécessaires pour la compensation. Le point commun du miroir de courant évolue avec la température. Connaissant celle-ci, la pente peut être contrôlée par le courant, et donc, par M1 et sa tension de grille. Le circuit, formé par Mc1 et Mc2, est conçu pour réduire le courant quand la température augmente. Les dimensions des transistors et la tension Vbias sont conçus pour assurer les caractéristiques de l’étude préliminaire. 4.2.3 Control de Tension Le circuit de contrôle de tension est composé d’un Trigger de Schmitt commandant un transistor de décharge. Le transistor de décharge est un simple transistor NMOS, souvent bloqué et durant une courte durée passant, autorisant la décharge rapide de la capacité. Durant les premières simulations, le Trigger de Schmitt fut simulé par un simple signal carré à 40 Hz. Ensuite le Trigger fut simulé seul. Sa conception est devenue compliquée. Le but était d’assurer la meilleure excursion possible, c'està-dire qu’il puisse comparer l’entrée avec des références comprises entre 0 et 0.6 V au moins. La principale partie du circuit est un amplificateur opérationnel transconductance (OTA) (Appendice 4). Une paire différentielle NMOS et PMOS ont, respectivement, des capacités dynamiques comprenant les hautes et les basses tensions de l’alimentation. Par conséquent, un OTA NMOS et un PMOS sont respectivement utilisés pour comparer l’entrée avec la référence haute et la référence basse (environ 0.6 V et 0 V).
Fig. 3 Schmitt Trigger Selon la sortie, le Trigger compare l’entrée avec la paire différentielle NMOS ou PMOS.
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Résultats de Simulations
Les simulations ont été réalisées en deux parties. D’une part, tout le circuit sans le Trigger de Schmitt fut simulé, et d’autre part, le Trigger fut simulé seul. La première simulation fut effectuée à trois températures différentes (-20 °C, 25 °C et 60 °C).
Fig. 4 Signal en dent de scie et Consommation à température ambiante La Fig. 4 montre les résultats de simulation à 25 °C. L’amplitude, la pente de la sortie et la dissipation de puissance sont satisfaisantes. La pente de la rampe est de 20.8 V/s. C'est-à-dire pour une amplitude de 500 mV, la fréquence de sortie serait de 41.6 Hz. Ensuite les simulations, réalisées à -20°C et 60°C, se sont avérées également satisfaisantes. La pente à -20°C est de 18.7 V/s. C'est-à-dire pour une amplitude de 500 mV, la fréquence de sortie serait de 37.4 Hz. La pente à 60°C est de 22.4 V/s. C'est-à-dire pour une amplitude de 500 mV, la fréquence de sortie serait de 44.8 Hz. Par conséquent, la dépendance à la température de la fréquence est de 0.0925 Hz/°C. Durant les différentes simulations, des piques de consommation sont aperçues. Elles sont causées durant la décharge de la capacité. Il est nécessaire de connaître leur durée et leur valeur maximale.
Fig. 5 Consommation de puissance du circuit Nicolas LAFITTE
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Grâce à une simulation plus fine, on déduit Pmax : Pmax = 8.622 µW. On remarque d’autre part que la durée d’un pique n’est pas plus grande que 200 ns. On peut alors déduire la consommation moyenne du circuit : P = 2.25 µW. Ensuite, le Trigger de Schmitt fut simulé seul.
Fig. 6 Résultats de simulation du Trigger de Schmitt La Fig. 6 montre les entrées (Vin1 et Vin2) et la sortie (Vout), ainsi que deux signaux internes du circuit. Vnmos et Vpmos dépendent du niveau de tension de la sortie. Ils permettent de sélectionner la sortie d’OTA adéquate pour ce niveau de tension de comparaison. La consommation de puissance est satisfaisante. Elle reste inférieure à 13 µW. Sur les résultats de simulation, on remarque quelques glitches. Ils ont lieu quand la paire différentielle PMOS est sélectionnée.
4.4
Résultats
La première partie de la conception donne entière satisfaction respectant les différentes charges. Néanmoins, le circuit de contrôle de tension, et plus spécifiquement le Trigger de Schmitt, ne sont pas terminés. Le Trigger de Schmitt ne remplit pas les spécifications. Son fonctionnement n’est pas correct et sa conception est compliquée. Par contre, la consommation prévisionnelle, du circuit en entier, ne dépasserait pas 20 µW. Les glitches peuvent être supprimés en modifiant quelques éléments du circuit. Les modifications faites, les quelques simulations ont données satisfactions. La borne positive doit impérativement être connectée à une tension référence de comparaison. Quelques tensions comprises entre 0.35 V et 0.45 V engendrent des glitches, à cause de la dynamique restreinte de la paire différentielle PMOS. Deux solutions sont alors possibles. Le Trigger est utilisé avec des références comprises entre 0 V et 0.35 V, et 0.45 et 0.9 V. Cette solution reste aléatoire et dangereuse. Ou il est préférable de modifier la conception des portes logiques, pour que leur tension seuil ne soit plus 0.45 V mais 0.35 V. La paire différentielle PMOS serait alors sélectionnée pour des tensions inférieures à 0.35 V. Nicolas LAFITTE
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PARTIE N°5. CONCLUSION
La conception d’un oscillateur de faible fréquence et de faible consommation en technologie CMOS n’est pas terminée. D’une part, il n’est pas certain que les deux blocs simulés ensemble remplissent toutes les spécifications : en fonctionnement et en consommation. D’autre part, après cela, il reste à réaliser des simulations Monte-Carlo sur le circuit proposé pour finir le layout et valider le circuit. Enfin, des améliorations peuvent être apportées pour améliorer l’indépendance du montage à la température, et à l’alimentation surtout. Malheureusement, tout le travail de conception ne fut pas terminé. Néanmoins ce stage reste une expérience très intéressante. Premièrement, le sujet de stage correspondait à mes attentes. Le sujet de conception microélectronique correspond à ce que je souhaiterais faire dans mon futur métier. Le travail ne m’a pas déçu. Il m’a permis de réaliser ce qu’il était, ce que je savais et ce que je devais acquérir. Ensuite, mon souhait de travailler à l’étranger fut réalisé. Je voulais vivre une expérience humaine enrichissante et me confronter à d’autres méthodes de travail. C’est certainement là que se trouve l’aspect le plus positif. J’ai découvert une nouvelle culture, pratiqué plusieurs langues, participé à des séminaires chaque semaine, rencontré de nombreuses personnes, vécu de nouvelles expériences, … Mais avant tout, j’ai du m’adapter à un nouvel environnement social et professionnel. Je pense que ce point est une réelle réussite. Je n’ai rencontré aucune difficulté à vivre, travailler, et profiter, durant mon séjour.
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Appendix 2 “Design of a CMOS Low-Power Low-Frequency Oscillator” Presentation, N. Lafitte, Kumamoto University, 4th August 2006.
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Appendix 3 “Design of a CMOS Low-Voltage Low-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement System”, F. Timischl, T. Inoue, 2006.
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Appendix 4 “Operational Amplifier Models”, Y. Deval, 2006.
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Appendix 5 SPICE Simulation Files, Main Circuit, N. Lafitte, 2006.
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******************************************************************* ** MOS Current Source + Current Mirror + Current Control ** Nicolas Lafitte ** 2006/07/31 ******************************************************************* .op .option accurate post ingold=2 accurate numdget=7.0 .include /anacas/users/timischl/simulation/bu21n11.mdl .lib /anacas/users/timischl/simulation/bu21n11.skw NT .lib /anacas/users/timischl/simulation/bu21n11.skw PT ********************Variables************************************** .global vdd! .param VDD=0.9 .param VDD2=0.45 ********************Power Supply Voltage Source******************** VSupply vdd! 0 dc VDD ***************************** Signals ***************************** Vbias bias!2 0 DC 750mV Vcmd1 cmd! 0 PULSE(0V 0.9V 0 1u 1u 0.5m 25m)*40Hz Square Signal *Vcmd1B cmd! 0 PULSE(0V 0.9V 12510u 0 0 12.5m 25m)
**************************** Circuit ****************************** *** Current Source Control *** Mc1 vdd! bias!2 bias! 0 CMOSN L=10u W=10u Mc2 bias! 1 0 0 CMOSN L=4u W=6u *** Current Source *** M1 10 bias! 0 0 CMOSN L=40u W=7u *** Current Mirror *** M2 1 1 vdd! vdd! CMOSP L=4u W=6u M3 2 1 vdd! vdd! CMOSP L=4u W=6u *** Current Test Points *** Vi1 1 10 DC 0 Vi2 2 3 DC 0 C1 3 0 8.4p Mdischarge 3 cmd! 0 0 CMOSN L=4u W=6u ******************************Analysis***************************** *.DC VSupply 0.0 VDD 0.1 .TRAN 1u 100m .IC V(2) 0 *.probe tran Voutput=par('V(2,3)') .probe tran POWER .temp 60 ******************************************************************* .end *******************************************************************
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Appendix 6 SPICE Simulation Files, Schmitt Trigger Circuit, N. Lafitte, 2006.
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******************************************************************* ** Schmitt Trigger Circuit + Capacitor + Switch ** Nicolas Lafitte ** 2006/07/20 ******************************************************************* .op .option accurate post ingold=2 accurate numdget=7.0 .include /anacas/users/timischl/simulation/bu21n11.mdl .lib /anacas/users/timischl/simulation/bu21n11.skw NT .lib /anacas/users/timischl/simulation/bu21n11.skw PT ********************Variables************************************** .global vdd! .param VDD=0.9 .param VDD2=0.45 ********************Power Supply Voltage Source******************** VSupply vdd! 0 dc VDD ******************************************************************* ********************Input Signal*********************************** *V1 i1 O dc 800m *V2 i2 0 dc 0.7V *V1 in1 0 pulse (VDD 0 10u 20u 20u 5u 50u) *Capacitor Charge & Discharge *V2 in2 0 pulse (0.8 0.1 0 0 0 60u 120u) *Trigger Levels ******************************************************************* **************************Circuit********************************** Icharge in1 vdd! 10f C1 in1 0 0.84p M1 in1 out 0 0 cmosn L=1u W=3u
*Current Source *Capacitor *Discharge Transistor
***Schmitt Trigger*** X1 in1 in2 sP pmos_diffpair X2 in1 in2 sN nmos_diffpair
*Schmitt Trigger
xINVERTER1 in1 pPMOS inverter xINVERTER2 pPMOS pNMOS inverter xNAND1 sP pPMOS p1 NAND xNAND2 sN pNMOS p2 NAND xNAND3 p1 p2 out NAND xINVERTER3 out p5 inverter R1 p5 in2 1200k R2 in2 0 10MEG ***Schmitt Trigger*** *Schmitt Trigger End ******************************************************************* *******************PMOS Diff Pair Circuit************************** .subckt pmos_diffpair i1 i2 p2 *i1="-" & i2="+" *Diff Pair PMOS* Mp1 o1 i1 pc 0 cmosp L=1u W=3u Mp2 o2 i2 pc 0 cmosp L=1u W=3u *Current Source* Mn1 pc 0 vdd! vdd! cmosp L=1u W=3u *Load* Mn2 o1 o1 0 0 cmosn L=1u W=3u Mn3 o2 o2 0 0 cmosn L=1u W=3u Mn4 p1 o1 0 0 cmosn L=1u W=3u Mn5 p2 o2 0 0 cmosn L=1u W=3u
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Mp3 p1 p1 vdd! vdd! cmosp L=1u W=3u Mp4 p2 p1 vdd! vdd! cmosp L=1u W=3u .ends pmos_diffpair *******************NMOS Diff Pair Circuit************************** .subckt nmos_diffpair i1 i2 p2 *i1="-" & i2="+" *Diff Pair NMOS* Mn1 o1 i1 pc 0 cmosn L=1u W=3u Mn2 o2 i2 pc 0 cmosn L=1u W=3u *Current Source* Mn3 pc vdd! 0 0 cmosn L=40u W=1u *Load* Mp1 o1 o1 vdd! vdd! cmosp L=1u W=3u Mp2 o2 o2 vdd! vdd! cmosp L=1u W=3u Mp3 p1 o1 vdd! vdd! cmosp L=1u W=3u Mp4 p2 o2 vdd! vdd! cmosp L=1u W=3u Mn4 p1 p1 0 0 cmosn L=1u W=3u Mn5 p2 p1 0 0 cmosn L=1u W=3u .ends nmos_diffpair ********************Inverter Circuit******************************* .subckt inverter in out m1 out in vdd! vdd! cmosp l=0.4u w=0.6u *PMOS m2 out in 0 0 cmosn l=0.4u w=0.6u *NMOS .ends inverter ********************* NAND Circuit ******************************** .subckt NAND inA inB out m1 out inA vdd! vdd! cmosp l=0.4u w=0.6u *PMOS m2 out inB vdd! vdd! cmosp l=0.4u w=0.6u *PMOS m3 pc inA 0 0 cmosn l=0.4u w=0.6u *NMOS m4 out inB pc 0 cmosn l=0.4u w=0.6u *NMOS .ends NAND ********************* NOR Circuit ******************************** .subckt NOR inA inB out m1 pc inA vdd! vdd! cmosp l=0.4u w=0.6u *PMOS m2 out inB pc vdd! cmosp l=0.4u w=0.6u *PMOS m3 out inA 0 0 cmosn l=0.4u w=0.6u *NMOS m4 out inB 0 0 cmosn l=0.4u w=0.6u *NMOS .ends NOR ******************************Analysis***************************** *.DC V1 1 0 0.1 .TRAN 10n 100u .IC out 0 .temp 25.0 ******************************************************************* .END *******************************************************************
Nicolas LAFITTE
Design of a CMOS Low Power Low Frequency Oscillator, Kumamoto University, August 4th 2006
Design of CMOS LowLow-Voltage LowLow-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement Measurement System 04/08/2006
Kumamoto University, August 4th, 2006
Design of a CMOS Low-Power Low-Frequency Oscillator Nicolas LAFITTE Ecole Nationale Supérieure d’Electronique d’Informatique et de Radiotélécommunications de Bordeaux
lafitte@
[email protected] Nicolas LAFITTE
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Subject
: Design of a CMOS Low Power Low Frequency Oscillator
Author
: Nicolas Lafitte
Date
: August 4th, 2006
Nicolas LAFITTE -
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Design of a CMOS Low Power Low Frequency Oscillator, Kumamoto University, August 4th 2006
Design of CMOS LowLow-Voltage LowLow-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement Measurement System 04/08/2006
OUTLINE 1. 2. 3. 4.
Introduction Circuit Configuration Simulation Results Conclusion
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Outline 1 Introduction 2 Circuit Configuration 3 Simulation Results 4 Conclusion
Nicolas LAFITTE -
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Design of a CMOS Low Power Low Frequency Oscillator, Kumamoto University, August 4th 2006
Design of CMOS LowLow-Voltage LowLow-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement Measurement System 04/08/2006
-1INTRODUCTION
Nicolas LAFITTE
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Outline 1 Introduction 2 Circuit Configuration 3 Simulation Results 4 Conclusion
Nicolas LAFITTE -
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Design of a CMOS Low Power Low Frequency Oscillator, Kumamoto University, August 4th 2006
Design of CMOS LowLow-Voltage LowLow-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement Measurement System 04/08/2006
1- Introduction
Fig. 1 : Ultrasonic Orientation System Nicolas LAFITTE
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1- Introduction Abstract : A design of a CMOS Low Frequency Oscillator has to be proposed. The proposed design should be used in an ultrasonic distance measurement system. The proposed circuit provides a rectangular signal (VLFOUT) and a sawtooth signal (VR) at 40Hz. The rectangular signal can be used to control an ASK circuit, when the sawtooth signal can measure time and distance. A new design is required to improve power dissipation.
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Design of a CMOS Low Power Low Frequency Oscillator, Kumamoto University, August 4th 2006
Design of CMOS LowLow-Voltage LowLow-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement Measurement System 04/08/2006
1- Introduction : Required Specifications (1)
2 Synchronous Outputs
Rectangular Signal
(40Hz, 10% Duty Cycle)
Sawtooth Signal
(40Hz)
Low Voltage (0.9V) Low Power (40µW) Small Chip Implementation Nicolas LAFITTE
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1- Introduction The whole ultrasonic circuit system is a fully hardware-based and works at a low power supply of 0.9V. It may be appropriate for the use in portable and long lived obstacle sensor systems. The whole circuit dissipates about 270µW and 240µW is, today, lost by the Low Frequency Oscillator. A new design must improve this power dissipation, respecting the integrability on a small chip.
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Design of a CMOS Low Power Low Frequency Oscillator, Kumamoto University, August 4th 2006
Design of CMOS LowLow-Voltage LowLow-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement Measurement System 04/08/2006
1- Introduction : Required Specifications (2)
2 Synchronous Outputs
A Rectangular Signal
A Linear Sawtooth Signal
An High Precision on the Frequency and the Duty Cycle is not required
Phase Noise is not a specification but Temperature and Supply Dependencies are actually important for a consistent distance measurement
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1- Introduction The circuit should provide two outputs. A rectangular signal controls an ASK circuit, allowing the emission or not of an carrier signal. A sawtooth signal is used to measure time and distance. Knowing the time between emission and reception, the distance can be deduced. Consequently a perfect linear signal (depending with time) is required. Therefore the two outputs should be synchronous. No delay derivation between signals are allowed to ensure distance measurements. Otherwise, the precision on the frequency and the duty cycle is not required. 40Hz is an indication, the frequency can be included between 30Hz and 50Hz without problem for the distance measurement system. The duty cycle should be small to improve the system power consumption, included between 10% and 20%. On the other hand, the frequency must be the same in spite of the conditions. To ensure a consistent distance measurement, the sawtooth signal should not depend on the temperature and supply variations. Nicolas LAFITTE -
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Design of a CMOS Low Power Low Frequency Oscillator, Kumamoto University, August 4th 2006
Design of CMOS LowLow-Voltage LowLow-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement Measurement System 04/08/2006
1- Introduction : Views
Low Frequency Oscillators Views • LC Oscillators
Require big L and C values
Therefore a big implementation area is required
• RC Oscillators
Require a big constant time τ = R.C
A big capacitor value require a big implementation area Therefore a big resistor value or a small charge current is required
• Ring Oscillators should be experienced Nicolas LAFITTE
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1- Introduction A so low frequency oscillators should have a big inertia. But the problem of high frequency signal should not be taken in interest here. Because a small chip implementation area is required, L or C element value must be designed small. Therefore the low frequency oscillator is impossible to design with only L and C elements. Consequently, a big constant time is required. So a big resistor value or a small charge current is required. A ring oscillator may be a possibility. Even if they are used to obtain high frequency, it can possible to design one for a low frequency signal.
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Design of a CMOS Low Power Low Frequency Oscillator, Kumamoto University, August 4th 2006
Design of CMOS LowLow-Voltage LowLow-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement Measurement System 04/08/2006
-2CIRCUIT CONFIGURATION Nicolas LAFITTE
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Outline 1 Introduction
2 Circuit Configuration 3 Simulation Results 4 Conclusion
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Design of a CMOS Low Power Low Frequency Oscillator, Kumamoto University, August 4th 2006
Design of CMOS LowLow-Voltage LowLow-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement Measurement System 04/08/2006
2- Circuit Configuration
Fig 2 – Proposed Circuit (1) Nicolas LAFITTE
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2- Circuit Configuration A capacitor (8.4 pF) is charged by a small constant current Ic: Ic ~ 200 pF. A Level Control Circuit, composed with a Schmitt Trigger, allows the capacitor charge or the discharge (by Mdischarge N-MOSFET). A Current Control Circuit ensure a constant charge current value.
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Design of a CMOS Low Power Low Frequency Oscillator, Kumamoto University, August 4th 2006
Design of CMOS LowLow-Voltage LowLow-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement Measurement System 04/08/2006
2- Circuit Configuration
Fig 3 – Proposed Circuit (2) Nicolas LAFITTE
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2- Circuit Configuration The two outputs required are on the input and the output of the schmitt trigger. Simulations are necessary to characterize the temperature dependency of the Current Source Circuit. Then the feedback current control can be designed.
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Design of a CMOS Low Power Low Frequency Oscillator, Kumamoto University, August 4th 2006
Design of CMOS LowLow-Voltage LowLow-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement Measurement System 04/08/2006
-3SIMULATION RESULTS Nicolas LAFITTE
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Outline 1 Introduction 2 Circuit Configuration
3 Simulation Results 4 Conclusion
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Design of a CMOS Low Power Low Frequency Oscillator, Kumamoto University, August 4th 2006
Design of CMOS LowLow-Voltage LowLow-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement Measurement System 04/08/2006
3- Simulation Results : @ 25°C
Fig. 5 : Linearity Output (1)
For Vmax = 500mV: Fig. 4 : Output and Power Consumption (1) Nicolas LAFITTE
f = 41.6 Hz
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3- Simulation Results Simulations at 25°C: The output amplitude is good. The power dissipation looks good. The rising slope of the sawtooth signal is 20.8 V/s (at 25 °C) For an output amplitude of 500 mV, the output frequency will be 41.6 Hz.
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Design of a CMOS Low Power Low Frequency Oscillator, Kumamoto University, August 4th 2006
Design of CMOS LowLow-Voltage LowLow-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement Measurement System 04/08/2006
3- Simulation Results : @ -20°C
Fig. 7 : Linearity Output (2)
For Vmax = 500mV: Fig. 6 : Output and Power Consumption (2) Nicolas LAFITTE
f = 37.4 Hz
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3- Simulation Results Simulations at -20°C: The rising slope of the sawtooth signal is 18.7 V/s (at -20 °C) For an output amplitude of 500 mV, the output frequency will be 37.4 Hz.
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Design of a CMOS Low Power Low Frequency Oscillator, Kumamoto University, August 4th 2006
Design of CMOS LowLow-Voltage LowLow-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement Measurement System 04/08/2006
3- Simulation Results : @ 60°C
Fig. 9 : Linearity Output (3)
For Vmax = 500mV:
f =44.8 Hz Fig. 8 : Output and Power Consumption (3)
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Temperature Dependency:
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0.09 Hz/°C 15
3- Simulation Results Simulations at 60°C: The rising slope of the sawtooth signal is 22.4 V/s (at 60 °C) For an output amplitude of 500 mV, the output frequency will be 44.8 Hz. Consequently the temperature dependency on the output frequency is 0.0925 Hz/°C.
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Design of a CMOS Low Power Low Frequency Oscillator, Kumamoto University, August 4th 2006
Design of CMOS LowLow-Voltage LowLow-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement Measurement System 04/08/2006
3- Simulation Results : Power Dissipation .probe tran POWER
p ( t ) = ( P max − Pmin ) e
τ = 71.229
−
t
τ
+ Pmin
ns
P max = 8.622
µW
Fig. 10 : Power Consumption (1)
In the worst case, at 60°C :
p(t) < 9 µW Fig. 11 : Power Consumption (2)
P ~ 2.25 µW Nicolas LAFITTE
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3- Simulation Results : Power Dissipation During different simulations, power consumption peaks have bee seen. They are caused by the discharge of the energy stored in the capacitor.
p ( t ) = ( Pmax − Pmin ) e
−
t
τ
+ Pmin
We need to know how large and high peaks are. A fine simulation makes possible to characterize the power function. The time is deduced by two points P1 and P2 : τ = 71.229 ns. Then Pmax is deduced : Pmax = 8.622 µW. On the other hand, we can see the peak is not more large than 200 ns. Therefore the average power can be deduced.
P =
200 ns ⋅ 9 µ W 2
+ 25 ms ⋅ 2 . 25 µW 25 ms
Nicolas LAFITTE -
[email protected] -
≈ 2 . 25 µW 16
Design of a CMOS Low Power Low Frequency Oscillator, Kumamoto University, August 4th 2006
Design of CMOS LowLow-Voltage LowLow-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement Measurement System 04/08/2006
-4CONCLUSION
Nicolas LAFITTE
[email protected]
17
Outline 1 Introduction 2 Circuit Configuration 3 Simulation Results
4 Conclusion
Nicolas LAFITTE -
[email protected] -
17
Design of a CMOS Low Power Low Frequency Oscillator, Kumamoto University, August 4th 2006
Design of CMOS LowLow-Voltage LowLow-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement Measurement System 04/08/2006
4- Conclusion
This first results show that the frequency required can be possible to be obtained by this way. The proposed circuit power dissipation looks good for the moment. < 2.5 µW (in the worst case) The temperature dependency is for moment too big but has been improved. The feedback control current should be calculated and better designed. But its gain depends also on the temperature !! Nicolas LAFITTE
[email protected]
18
4- Conclusion
Nicolas LAFITTE -
[email protected] -
18
Design of a CMOS Low Power Low Frequency Oscillator, Kumamoto University, August 4th 2006
Design of CMOS LowLow-Voltage LowLow-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement Measurement System 04/08/2006
4- Conclusion : Next Steps
The Feedback Control Current should be improved The Supply Dependency should be characterized and improved I should find a solution for Vbias. The system depends too much on Vbias. I should begin the layout.
Nicolas LAFITTE
[email protected]
19
4- Conclusion
Nicolas LAFITTE -
[email protected] -
19
Design of a CMOS Low-Voltage Low-Power Circuit for an Integrated Pulsed Ultrasonic Distance Measurement System Felix Timischl*
Takahiro Inoue** and Akio Tsuneda*
*Department of Electrical and Computer Science Graduate School of Science and Technology Kumamoto University Email:
[email protected]
**Department of Electrical and Computer Engineering Faculty of Engineering Kumamoto University
Abstract— The design of a mixed-signal CMOS low-voltage low-power circuit for a compact-size pulsed ultrasonic distance measurement system for obstacle detection is proposed. The presented mixed-signal CMOS circuit is completely realized with hardware components and does not employ microcontrollers. The whole circuit system works at a power supply of 0.9 V and dissipates no more than 267 µW. SPICE simulations are performed to validate the designed performances.
I. I NTRODUCTION Attention to microelectronic devices for compensation of physical disabilities of aged and disabled people, in particular concerning sense of vision, acoustic sense and tactile sensibility, is increasing recently. Ultrasonic obstacle detection is based on the principle of reflection of ultrasonic waves by the obstacles to be detected. Basically, there are the following different methods of noncontact distance measurement employing ultrasonic waves. The ’Time-of-Flight method’ requires detection of the time delay (Time of Flight, TOF) between emission and reception of an ultrasonic ASK pulse [1] - [4]. The ’Phase-Shift method’ uses continuous waves and detects the phase difference between the emitted and received signal [5], [6]. Systems combining advantages of both the above-mentioned methods are present in the literature [7], [8]. Other systems apply the ’doppler distance measurement technique’, achieving relative distance information by measuring the change in frequency as the ultrasonic source moves with respect to the receivers and vice versa [9]. In the method we propose in this paper, we achieve absolute distance information while circumventing the problem of superimposed reflection signals applying a frequency-selective ’Time-of-Flight method’. The vast majority of comparable systems available in the literature employ microcontroller or even personal computers. The use of digital-signal-processing (DSP) units implies considerable deterioration in power dissipation and in integrability. The proposed circuit is fully hardware-based and does not rely on any kind of DSP. It works at a power supply of only 0.9 V and dissipates less than 267 µW, which makes it appropriate
0-7803-9390-2/06/$20.00 ©2006 IEEE
for the use in portable and long-lived smart obstacle sensor systems. II. P RINCIPLE OF U LTRASONIC O BSTACLE D ETECTION We adopt the ’Time-of-Flight method’ to measure the distance between an ultrasonic emitter and a wave-reflecting obstacle. Fig.1 shows a block diagram of the distance measurement system. VBias
HF- VHFOUT Osc.
LFOsc. VR
VSPIKE
S&H
Fig. 1.
VLFOUT
VASKOUT
US Em.
ASK
VPLLIN US Lock-in VCPLL PLL Rec. Detector
VTOF
Block diagram of the ultrasonic distance measurement system
The high-frequency oscillator generates a 40 kHz signal, VHF OU T , which is ASK modulated by a low-frequency signal, VLF OU T , of around 20 Hz driving an ultrasonic emitter circuit. The PLL and the lock-in detector form a frequency-selective stage performing a frequency comparison between the emitted and received ultrasonic signal. In the present design, the first wave package arriving at the receiver will lead to lock-in of the PLL, i.e. the closest obstacle will be detected. The lockin detector outputs a spike VSP IKE in case of PLL’s lock-in to the emitter frequency, switching through the instantaneous value of low-frequency oscillator’s (astable multivibrator’s) ramp signal VR to the sample-hold circuit. The output VT OF of the sample-hold circuit is directly proportional to the TOF and namely, to the distance. The sampling rate is determined by the frequency of VLF OU T , which is half of the frequency of VR . Since distance measurement only makes sense within one cycle of VR , the function of the lock-in detector is suppressed during the second half of the period of VLF OU T . Thus, the detectable range limit
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ISCAS 2006
can be obtained using (1). 2d
T (1) 2 where T is the period of VLF OU T , c is the sonic speed and d is the distance between the ultrasonic emitter and the reflecting obstacle. Assuming c = 340 m/s, one obtains d = 4.25 m as the maximum detectable distance, which is regarded as sufficient for the use as a subsidiary orientation system for disabled people in a building or outdoor where cars are kept out. = c
following parameters, C1 = C2 = C3 = 0.84 pF, the channel width W = 5.6µm and the channel length L = 0.45µm for all unit MOS transistors.
III. C IRCUIT C ONFIGURATION AND S IMULATION R ESULTS HSPICE simulations were performed for each of the circuits described below using the level-49 device model under the assumption that a standard 0.35 µm 2-poly 4-metal CMOS process is used. All simulations are performed at 0.9 V supply voltage. A. High-Frequency Oscillator Fig.2 shows a novel current-mirror based ring oscillator which is used as a high-frequency carrier signal generator for the ASK circuit and as a voltage-controlled oscillator (VCO) of the PLL. Aiming at low-power operation of the whole circuit system, we employ a ring oscillator, considering that the relatively high jitter of this kind of oscillator playes a minor role in the applications under consideration. VDD
VBias
Mp1
Mp2~11
Mp12
Mp13~22
Mp23
Fig. 3. Frequency vs. control voltage of a current-mirror based ring oscillator
In order to compare high-frequency oscillator’s control voltage VBias with PLL’s VCO control voltage VCP LL by the lock-in detector, both oscillators must have the same frequency versus control voltage characteristic, which is achieved by placing a T-FF (T-Flip Flop) at ring oscillator’s output VCM OU T as in the case of the PLL. The overall output is denoted as VHF OU T . B. Low-Frequency Oscillator The low-frequency oscillator is an astable multivibrator based on a Schmitt-trigger. Fig.4 shows a diagram of the circuit and Fig.5 the simulation results.
Mp24~33
Schmitt-Trigger 1:10 a
Mn1 VCMOUT
C1
1:10 Mn2~11
b
Mn12
C2
Vdd
1:10 Mn13~22 Mn23
Mn24~33
0.6 0.45
C3
Fig. 2.
Current-mirror based ring oscillator
The main building blocks of the VCO consist of three current mirror circuits with a current transfer ratio of 1 to 10, where each block between the nodes a and b can be regarded as a voltage inverter. Thus, the whole circuit can be treated as an inverter ring oscillator. The array of pMOS transistors in Fig.2 controls the bias current and therefore the frequency of the VCO. As a detailed analysis shows, the phase shift of each inverter is 240◦ and the frequency of the output signal f240◦ is obtained as follows under small-signal linear approximation, where C1 = C2 = C3 is assumed. √ 3 gmn + 11gdp + 11gdn (2) f240◦ = 2π C + 11Cgsn
0.6 25
0.6 0.45
Vdd
0.6 20 25 0.45
VLFOUT
T-FF
Vdd 0.6 0.45
0.6 0.45
VR
0.6 0.45
CAM
Vdd 1 0.45
0.6 0.45
Current Sources Fig. 4.
0.6 3.63
Level Shifter
Low-frequency oscillator circuit
The output of the Schmitt-trigger controls the current sources, which charge and discharge the capacitor CAM alternatively. The voltage at CAM has a sawtooth-like shape (Ramp Output VR ), which is fed back through a level shifter to the input of the Schmitt-trigger. The threshold voltages of the Schmitt-trigger are determined by Schmitt-trigger’s transistor dimensions.
In (2), gmn is the transconductance of each matched unit nMOS transistor, gdn and gdp are the output conductances of the unit nMOS and pMOS transistors, respectively. C is the capacitance of the capacitors C1 , C2 , and C3 , and Cgsn is the gate-source capacitance of each unit nMOS transistor. The VCO gain, Ko , is determined by the slope of the frequency versus control voltage characteristic shown in Fig.3. Notice here that the MOSFETs in Fig.2 are working in the weak inversion region. Simulation was performed with the
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Fig. 5.
Low-frequency oscillator output
The ramp signal VR provides a time-linear voltage for measurement of the TOF during the charging process of CAM . Applying this sawtooth-signal VR to a T-FF, one obtains a rectangular signal with half the sawtooth-frequency as an output signal VLF OU T which is used as a control-signal for the ASK-circuit. To obtain an output frequency of approximately 20 Hz, a capacitor value of CAM = 1.3 nF is required, which can be realized employing a Miller capacitance or can be built as an off-chip capacitor. C. ASK Circuit The circuit shown in Fig.6 allows ASK modulation of the 40 kHz signal. VLF OU T controls the path switch transistor Mswitch such as passing and blocking VHF OU T . A pull-down transistor Mn1 avoids floating of the input of the following buffer. VLFOUT Vdd
VHFOUT
VASKOUT Mswitch 0.6 0.45
ASK modulation circuit
D. Phase-Locked-Loop Together with the lock-in detector the PLL forms a frequency-selective stage, where the PLL is used as a frequency-to-voltage converter. It is designed to lock into the received 40 kHz signal VP LLIN and to output its VCO control voltage VCP LL which is then compared with the reference signal VBias by the lock-in detector. The standard PLL block diagram is shown in Fig.7(a). VPLLIN
Kd
F(jω) VD
Phase Detector
Loop Filter
VD
R1
VCPLL
VCPLL CLF
Ko VPLLOUT
T-FF
VCOOUT
R2
VCO
(a)
Fig. 7.
Level-Hold Block
Comparator Block
Cspike VSPIKE
Vdd
Mp1 Mn1
Mp2
Mp3
Mn4 Cstore
Mn2
VBias
Vdd
Mn5
VCPLL
Mp6
Vdd
1 Vdd
Mn3
0.45
Vdd
Mp4
Mp5
Mn9 0.6 3.51
Cas VLFOUT
Mn6
VRS
Mn7
Mn8
Reset Block
Fig. 8.
Lock-in detector circuit
0.6
Mn1 0.45
Fig. 6.
shows a diagram of the circuit and Fig.9 the output characteristic.
(b)
PLL block diagram
Since all input signals are digitalized in the present PLL design, we employed a simple exclusive OR gate as a phase detector. The loop filter parameters R1 = 490 kΩ, R2 = 120 kΩ and CLF = 20 pF (see Fig.7(b)) were chosen with the objective of realizing a small pull-in time TP at the cost of increasing the pull-in range ∆ωP [10] . With the present filter parameters, a pull-in time of TP = 33 µs and a pull-in range of ∆ωP = 570 kHz can be realized. The ring oscillator shown in Fig.2 is used as a VCO. Its input VBias is denoted as VCP LL and its output VCM OU T as V COOU T . The lock-in detector requires a high difference between PLL’s VCO control voltage VCP LL in the free-running state and in the locked state. In order to obtain these differences, a T-FF is placed at the VCO output V COOU T inside the PLL. E. Lock-in Detector The lock-in detector is the second part of the frequencyselective stage monitoring PLL’s state and providing a single high-level spike output VSP IKE in case of lock-in. Fig.8
Except Mp6 and Mn9 all MOS transistors have the dimensions W = 0.6 µm and L = 0.45 µm. The capacitors have the values Cstore = 1 pF, Cspike = 0.1 pF, and Cas = 1 pF. PLL’s VCO is exactly the same circuit as the high-frequency oscillator. Under good device matching between both, the lockin detector compares the VCO control voltage VCP LL of the PLL with the high-frequency oscillator control voltage VBias to detect lock-in to the emitter frequency. Crossing of VCP LL below the reference voltage VBias can be interpreted as a ’lock indicator’. The first stage of the proposed circuit is a differential amplifier, working as a comparator. Its output goes from logical high to logical low, if VCP LL drops below the reference voltage VBias . Since the default state of the path-switch transistor Mn4 is ON, Mp3 ’s gate voltage goes from high to low, if VCP LL drops below VBias . Instantaneously Mn4 turns off and a high level is stored at Cstore until the circuit is resetted. The following inverters and high-pass filter output a single spike VSP IKE indicating the lock-in of the PLL.
Fig. 9.
Lock-in detector output
Since Mp4 is always ON, VRS is at high state during normal operation. The periodical positive edge of the low-frequency signal VLF OU T produces a negative spike at VRS which turns both switches Mn7 and Mn4 ON, just long enough to reset the circuit, namely to switch through the comparator state (lockin information) to Cstore again. If the PLL is not locked in after the reset procedure, Mn4 stays closed, otherwise Mn4 is opened instantly and the high-level is stored in Cstore .
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The simulation results shown in Fig.9 conform to the above explanation of the circuit behavior. F. Sample & Hold Circuit The sample & hold circuit shown in Fig.10 consists of a logical circuitry, a pass-transistor, a storing capacitor, two analog buffers, and a startup-transistor to guarantee 0V output after turning-on of the power supply.
In the actual configuration, the system can give information on the distance of a reflecting obstacle. Using more than one receiver, one can obtain additional information, e.g. about the orientaion or shape of reflecting surfaces [1], [3]. Table I shows simulated power dissipation of the constituent building blocks, excepting the antenna and receiver amplifiers. TABLE I P OWER DISSIPATION OF EACH BUILDING BLOCK
VSPIKE VLFOUT VR
− 5 0.45
+
Element HF Osc. LF Osc. PLL and Lock-in det. ASK S&H Total
VTOF
+
Mswitch
Vdd
−
CSH
Fig. 10.
0.6 0.45
Sample & hold circuit
The AND-gate guarantees that the instantaneous time-linear ramp value is only switched through to the storing capacitor CSH , if the lock-in indicating spike, VSP IKE , occurs during the high-level of the LF-oscillator signal VLF OU T (see Fig.5 and Fig.11). The output of the sample & hold circuit VT OF is approximately proportional to the TOF and the distance. Fig.11 shows the simulation results of the sample & hold circuit with CSH = 4 pF.
Av. power diss. [µW] 1.92 1 3.1 2.5 1 9.52
Max. power diss. [µW] 4.67 240 10.6 6.5 5 266.77
IV. C ONCLUSION In this paper, a low-power low-voltage pulsed ultrasonic distance measurement system has been proposed. The circuit configurations as well as their functions have been described and have been confirmed by HSPICE simulations. ACKNOWLEDGMENT This work is supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Cadence Design Systems, Inc. and Synopsis, Inc. R EFERENCES
Fig. 11.
Sample & hold circuit output
G. Receiver amplifier circuit An array of simple common-source 20 dB amplifiers, each dissipating around 50 µW , can be used in the receiver-stage. The discrete amplifiers are connected with pass-switches, which are controlled by the amplitude of the received signal. H. Distance Measurement System In the present design, the proposed system can detect distances up to about 4.25 m, presuming VDD = 0.9 V, fHF OU T = 40 kHz and fLF OU T = 20 Hz. Presuming that all time-delays between different stages including the lock-in time of the PLL do not depend on the measured distance, they can be compensated by calibration. Thus, the slew-rate of the output op-amp in the S&H circuit is the main factor determing the distance-resolution of the system. A slew-rate of 0.2 V /µs leads to a resolution of 0.6 mm. The proposed system meets the requirements for the use as an indoor subsidiary orientation system for hospitalized disabled people, considering performance limiting parameters, such as the sample frequency of VLF OU T or the frequency shift resulting from movement of obstacles or the user himself.
[1] D. Marioli, E. Sardini and A. Taroni, ”Ultrasonic Distance Measurement for Linear and Angular Position Control”, IEEE Transactions on Instrumentation and Measurement, Vol.37, No.4, pp.578-581, December 1988 [2] D. Webster, ”A Pulsed Ultrasonic Distance Measurement System Based upon Phase Digitizing”, IEEE Transactions on Instrumentation and Measurement, Vol. 43, No. 4, pp.578-582, August 1994 [3] Y. Ebisawa, ”A Pilot Study on Ultrasonic Sensor-Based Measurement of Head Movement”, IEEE Transactions on Instrumentation and Measurement, Vol. 51, No.5, pp.1109-1115, October 2002 [4] K. Nakahira, T. Kodama, S. Morita and S. Okuma, ”Distance Measurement by an Ultrasonic System Based on a Digital Polarity Correlator”, IEEE Transactions on Instrumentation and Measurement, Vol.50, No.6, pp.1748-1752, December 2001 [5] M. Yang, S.L. Hill and J.O. Gray, ”A Multifrequency AM-Based Ultrasonic System for Accuracy Distance Measurement”, IEEE Transactions on Instrumentation and Measurement, Vol.43, No.6, pp.881-866, December 1994 [6] H. Mitome, T. Koda and S. Shibata, ”An Acoustic Positioning System Using Demodulated Signals of an FM Ultrasonic Wave”, IEEE Journal of Oceanic Engineering, Vol. OE-10, No. 3, pp.316-323, July 1985 [7] H. Nonaka and T. Da-te, ”Ultrasonic Position Measurement and Its Application to Human Interface”, IEEE Transactions on Instrumentation and Measurement, Vol. 44, No. 3, pp.771-774, June 1995 [8] F. E. Gueuning, M. Varlan, C. E. Eugene and P. Dupuis, ”Accurate Distance Measurement by an Autonomous Ultrasonic System Combining Time-of-Flight and Phase-Shift Methods”, IEEE Transactions on Instrumentation and Measurement, Vol. 46, No. 6, pp.1236-1239, December 1997 [9] W.T. Kuang and A.S. Morris, ”Ultrasonic Doppler distance measurement technique for robot tracking system”, Electronics Letters, Vol.35, No.11, pp.942-943, May 1999 [10] A. Blanchard, Phase-Locked Loops, p.265, Wiley 1976
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Folded cascode Op Amp Ibias
P3
i
P1 P2
i
i
i
Vbias1 i
I = gmp1(vin/2) AvDiff = - gmp1rdsp3
2i i
i Vbias2
OTA : the core amplifier
i
i i
I = gm1(vin/2) Gm = -gm1
i out
M1 M2
i
i
Much better dynamic capabilities than the simple PDiff
