Introduction to FA challenges for Future Technologies: Nanoprobing Key Role Christian Boit TUB Berlin University of Technology, Germany EUFANET Workshop 2008 Maastricht NL Oct 2, 2008 1
Extract of ITRS up to Edition 2007 Approxim. Min phys. Year of Feature Introduction Size [nm] 1998
120
Perform. Clock On Chip [GHz]
Inv. Delay (NMOS intrinsic) [ps]
2.2
12 (2.5)
Materials Device Concepts
Bulk Si 2000
90
2.5
10 (1.8)
Active
Gate
Pocket / Halo Implants
SiO2 Cu Poly
2002
65
3.0
9 (1.3)
2004
45
3.5
8 (1.0)
2006
32
4.2
7 (0.8)
2008
23
5.0
5 (0.6)
2010
18
5.8
4 (0.4)
2012
14
6.8
3.5 (0.3)
Strain SiGe SOI PD
Interconn.
Low k
Raised S/D Ge S/D
Ultra Thin Body FD
Ge / III-V Channels
Dual Gates FIN FETs
More of above
High k Diel. Metal Gates
Ultra low k
Air? 2014
11
7.9
3 (0.2)
Beyond CMOS 2
Optical Backside Circuit Analysis • GHz regime managed by most dynamic techniques • Feature Size Resolution: 2 levels of analysis – Level 1: IR + SIL to identify critical area – Level 2: Nanoprobing to verify critical node – prep circuit destructive increasing need for a high feature resolution probing tool set
Laser
Detector Photon Emission
LVP
Laser Stimulated Electrical Signal 3
Nanoprobing (AFP) of Identified Node se r La
Probe Tip
Tip
AFM Feedback
Piezo
Additonal Signals
AFP needles tungsten contacts IMD PW
bulk-Si
● Resolution < 50nm ● Parallel lapping down to contact layer ● Isolated devices ● Low ohmic contact ● Destructive to circuit
Detector
W NW bulk Silicon 4
Backside OptiFIB Circuit Edit
NW p+
STI p-Poly CoSi
IMD
W M1
FIB deposited Pt
Contacts to Silicon levels – low risk of charging & of size limitation PW n+ n-Poly
5
FIB Backside Trench Procedure ● localized FIB trench ca. 200x200µm2 Coaxial IR Column: planarity check of trench bottom to chip levels (fringes) - stopping on n-wells - stopping on STI < 400nm remaining Si up to 200x200µm2 STI
ΔZ≈130nm 6
frontside
AFP
backside ● FIB backside process
● parallel lapping down to contact layer ● isolated devices ● low ohmic contact
● devices not isolated ● creation of new circuit nodes ● Circuit fully functional
● Destructive to circuit AFP needles tungsten contacts IMD bulk-Si
PW
FIB Pt W
D
S
G
NW bulk Silicon 7
UltraThin Si - Ideal Platform for NanoAnalysis Ultra Thin Backside Technique
IR Technique
Visible or UV Laser Stimulation Nanoprobing, C-AFM E-Beam Techniques: - Voltage probing - E Beam induced photocurrent
Dyn. LS
e-
Light
STI
LVP, TRE Dyn. LS
Nano Probes
n-well ≈350nm
M1 M2 8
Nanoscale Potential Technique
Resolution
Potential
Comment
Optical through bulk Si (IR) Nanoprobing
500nm 50nm
150nm (SIL) 10nm
E Beam
100nm
20nm
Limited resolution Limited dynamics Material degradation?
Optical through ultra thin Silicon UV through ultra thin silicon
300nm
< 100nm (SIL) < 50nm
150nm
Realization complex Material degradation?
9
10
Silicon On Insulator not to scale
etc M2
M2 M1
Cu W FuSi
ILD STI STI
n+ ≅0,1µm Ge/III-V Ge/III-V BOX = Buried Oxide Layer≅0,3µm ⇒ Silicon On Insulator SOI
SiGe p+
≥ 100µm
≅1,5µm
SX SX 11
Architecture Trends
see e.g. T.Skotnicki, short course VLSI 2004 or ITRS roadmap 2003 SOI BOX SON GP DG
Silicon On Insulator, PD Partially Depleted, FD Fully Depleted Buried Oxide Silicon On Nothing Ground Plane Double Gate
3D ?
12
Ultra Thin Body UTB SOI: Partially depleted = PD
VGS = 0
Poly DepleGate ted Si
Fully Depleted FD
BOX Si
|VGS| > |VT|
Conductive Channel
Subthreshold Slope ≅ 60mV / dec FD active layer ∼ 20nm => UTB 13
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