Introducing UOC-III “ HERCules ” : “SIMPLY COMPLETE” Presented by:
E. Arnold &
P. Schepers TV System Design, ICE, Eindhoven
Start this presentation with a mouse-click & read the “Notes Pages”
© Philips Electronics N.V. 2003 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The presented information does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Diagrams in this presentation are intended to explain the functional behavior of a TV receiver with UOC-III “Hercules” concept, not necessarily in accordance with the actual IC implementation.
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Mainstream Tv Solutions - 10-2003 – UOC-III presentation 1-1
NonDisclosureAgreement
Philips Semiconductors
Contains items that require
File: Herc_1.ppt = Introduction, v1.2 29-09-2003 by E.Arnold
Hercules
” TV course, part 1:
1. Objectives of this course 2. Introduction: • Market positioning of Hercules • Sub-division of low- and mid-end TV market • Family overview 3. Block diagrams 4. Intake open questions
Philips Semiconductors
UOC-III “
Mainstream Tv Solutions - 10-2003 – UOC-III presentation 1-2
RESTRICTED, contains NDA items
Hercules
” TV course, part 2:
5.
The Guard Ring approach
6.
Application aspects: • Do’s and don’ts with TDA110xx • System Example: Global TV Receiver
7.
Answering questions
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UOC-III “
Mainstream Tv Solutions - 10-2003 – UOC-III presentation 1-3
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Hamburg
Application
IPM Nijmegen + Shanghai
IC design
Nijmegen !! $$$
Emulator Debugger
Spec & ApNote
Development Herc
!? ?
?!
TVSD ICE Eindhoven
System Architecture & Definition
Reference HW
Training
TV System architecture
I2C
GTV
PC menu I2C driver
GTV platform SW libraries
TVSD (HW) + SDCE (SW) Innovation Center Eindhoven
Philips Semiconductors
Mainstream Tv Solutions - 10-2003 – UOC-III presentation 1-5
From Idea to Product:
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IC application
RSO µP + Emulator: Hamburg
TV system, EMC
RSO
Ref. Designs, EMC: Eindhoven
Software
IPM/RSO
GTV + Business Partners: Eindhoven+Southampton
Sound DSP I.P.
RSO
Hamburg
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TV Proc. : Nijmegen
Mainstream Tv Solutions - 10-2003 – UOC-III presentation 1-6
Technical support:
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• Make information easier accessible for all levels of experience (engineers, software writers, QA) • Share I.C. & system application information • Share layout & EMC experience • STANDARD solutions
(libraries, basic cell, IP-blocks)
Philips Semiconductors’ approach for customer support aims to make our customers “self-supporting”. That is more efficient for both parties. Software has become a substantial part of the total design effort. Philips Semiconductors understands that our technical information will be used by experienced TV developers, but ALSO by “fresh” engineers. We are now adding more (basic) functional descriptions to our (detailed) technical application notes.
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• Faster design-in cycle = higher efficiency for all
Mainstream Tv Solutions - 10-2003 – UOC-III presentation 1-7
Objectives:
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New
• Technology driven (sell what we can make)
• Market driven (make what we can sell)
• Application assistance at first design
• Training before design starts (saves time)
• Technical description (how we’ve done it)
• Functional descriptions (how functions are intended)
• Description I2C-bus bits
• TV functions & algorithms
• TV know-how required
• Higher abstraction level
With this IC training course we want to present you a COMPLETE system in a short time frame. Please use the documentation of this course together with our technical Application Notes and it should be easier to: - understand how certain functions should be operated - find the link between a function and its I2C-bus control bits - prevent errors in TV chassis design In the IC’s Application Note you can find descriptions of each pin and the I2Cbus control bits. In this training course we will show how TV functions use the I2C-bus bits. The diagrams in this presentation are intended to explain the functional behavior. The actual IC implementation may be different.
Philips Semiconductors
Old
Mainstream Tv Solutions - 10-2003 – UOC-III presentation 1-8
Design-in approach:
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ü All-in-one IC, one design for Mono & Stereo ü Picture & sound enhancements ü Many I/O pins & switches, but less components ü Faster time-to-market ü Faster factory throughput
The “truly-global” TV capabilities of the UOC-III “Hercules” IC, makes it possible to cover more market with less chassis designs. The application overhead of the maximum versus the minimum version is small. Leaving out some components is often cheaper than having different PCB designs.
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ü Total integration for 50/60Hz TV chassis
Mainstream Tv Solutions - 10-2003 – UOC-III presentation 1-9
What set makers want:
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• The next step of integration: UOCIII - Less versions (keep cost effectiveness) - More features (= more pins : QFP128) • Make TV design as easy as possible • Optimal process combination (MCM of CMOS + BIMOS)
Available as I/O pins: - 4x ADC/IO - 2x Int/IO - 6x PWM/IO - 2x IO - 2x IO (no UART used) - 5x Output (no I2S used) - 1x Swo (no YUVoutput used) - 1x SwIo/Vguard (p12) = 23 lines, excluding I2C
Mainstream Tv Solutions - 10-2003 – UOC-III presentation 1-10
platform:
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The
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Old pinning (IC-top view)
“Old” face 32
65 33
package SOT-320-2
⇓ ⇓
• Same physical IC,
32
1
but legs bent the other way 128
“New” face
97
64 65
on the new “top” of the “flipped” - IC
New, reversed pinning (IC-top view) 96
• Type number printed
33
Mainstream Tv Solutions - 10-2003 – UOC-III presentation 1-11
96
Philips Semiconductors
1
64
• Existing QFP128 SMD
97
• Two variants = easier choice for PCB layout
128
“Face-down” QFP-package:
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• One IC for everything: Control, small-signal, mono/stereo, extensive Audio/Video • Upgrade with digital sound & video processing • Alignment free IF, including SECAM-L/L1 + AM • FM sound, no external filters (traps/band-pass 4.5/5.5/6.0/6.5) • Full multi-standard colour decoder • One Xtal reference for all functions (micro processor, RCP, TXT, CC, RDS, colour decoder & stereo sound processor)
Modern PLL techniques are used to eliminate alignments. The IF frequency can simply be chosen from: - 58.75 MHz (Japan), - 45.75 MHz (America), - 33.4 or 33.9 MHz (SECAM-L1 only in France), - 38.0 MHz (China) - 38.9 MHz (Europe) Mono version: The FM sound carrier is demodulated using a “Narrow-Band-PLL”, enhanced with internal band pass filters. Since the Narrow-Band-PLL is automatically calibrated, a multi-standard implementation can be made WITHOUT external switching. Stereo versions: Addition of a sound-DSP offers stereo decoding for all terrestrial stereo standards. Audio processing includes Dolby Pro-Logic, Virtual Dolby and many other features to enhance the TV sound.
Mainstream Tv Solutions - 10-2003 – UOC-III presentation 1-12
highlights:
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The
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• Only 3.3V, 10mA needed in TV-standby (PowerDown mode) • Low stress by innovative slow start/stop of HOUT • Separate adjusted colour temperature hi/low-light • Selectable I/O pin configuration: ADC / PWM / Push-Pull / Open-Drain …
• Byte-level hardware, multi-master I2C-bus: Transmit/receive up to 400kHz (Normal/Fast-mode I2C), “In-System” (re)Programming up to 2MHz (Hs-mode I2C)
All 3.3V supply pins should be permanently connected to the Standby supply. Including peripheral components, the start-up current is less than ??100mA. During standby mode the device’s power consumption can be reduced to ??12mA, by bringing the software in Power Saving mode (improved POWERDOWN and IDLE modes).
Mainstream Tv Solutions - 10-2003 – UOC-III presentation 1-13
highlights:
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The
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• Enhanced 80c51 micro processor core • (re)programmable program memory 64 .. 128KB, same type for OSD + TXT + CC character sets • High performance OSD : - Italics, Underline, Shadowing - Soft colours - Soft scroll - Reduced-intensity background - Dynamic Redefinable Characters (DRCs)
Normal 8051 core can address up to 64KB of ROM. The address space is enhanced with bank-switching. Characters can also be modified in (re)programmable-ROM, allowing customer logo’s, special characters etc. With the inclusion of Closed Captioning (American subtitling) the same attributes also become available for On Screen Display. DRCs make it possible to add dynamic animations to the OSD. They can also be used to extend the number of OSD character fonts.
Mainstream Tv Solutions - 10-2003 – UOC-III presentation 1-14
highlights:
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The
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Low
PHILIPS
PHILIPS
Mono TDA8361 + TDA4665 + PCA84C441
TDA8362 + TDA4665 + TDA8395 + PCA84C641
MidPlayback Stereo PHILIPS
TDA8842 + SAA5291 (1p TXT)
Low+
Low++
PHILIPS
PHILIPS
TDA8362 + TDA4665 + TDA8395 + SAA5244 (1p TXT) + PCA84C841
TDA8362A + TDA4665 + TDA8395 + SAA5281 (8p TXT) + P83C055 Mid+
Mid-2 Speaker Mono PHILIPS
TDA8840 + SAA5290 (uP + TXT)
TDA935x/6x/8x - FM Ultimate One Chip Mid PHILIPS
TDA8844 Stereo + SAA5296 (10p TXT)
PHILIPS
TDA8854 + SAA5497 (10p TXT)
Y PR PB
Mid++ PHILIPS
TDA9801 + TDA8376A + TDA4665 + TDA8395 + SAA5497 (10p TXT)
TDA935x/6x/8x - QSS Ultimate One Chip • TDA935x/6x/8x-FM for mono, -QSS for stereo ••UOC-III UOCIII “Hercules“ “Hercules“for forMono Monoand andStereo Stereo • TDA95xx provides both QSS & FM/AM demod.
The largest production volume is found in the Low-end segment. The UOC-III “Hercules” IC makes it possible to build a very compact TV chassis, including extensive audio/video I/O switching. The Mid-end segment is dominated by stereo sets. This is usually a larger cabinet with two speakers and a stronger power supply. The on-board stereo DSP processor adds attractive sound features to the concept.
Philips Semiconductors
Low-
Mainstream Tv Solutions - 10-2003 – UOC-III presentation 1-15
Classification of TV receivers:
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Parabola
Horizontal Parallelogram
Vert. Linearity
Upper Corner Parabola
Trapezium
Lower Corner Parabola
• Suitable for “real-flat” and 16:9 CRT displays
For 110º applications UOC-III has an East-West modulator output, suitable to handle large screen picture tubes. Especially for completely flat picture tubes, controls for Horizontal Bow, Parallelogram and Vertical Linearity are added. For more precise alignment, the corner parabola’s can be set independently for the upper and lower corners.
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Horizontal Bow
Mainstream Tv Solutions - 10-2003 – UOC-III presentation 1-16
Suitable for Small AND Big screen:
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+3V3 +5V
+VB Horizontal Drive Pulses
Hor. Driver
T D + D1
RDR LLEAK
ϕ2-loop H-flyback
Pulse
EHT LP
LH
CDIV
T DR
UOC-III Hercules
FBT CF
+8V
+VB
Linearity correction CS
Beam Curr. +8V +5V
CB
Shaper
• 1V8, 3V3STANDBY and +VB needed to start line drive • Secondary +5V and +8V can be generated by FBT LSU, MSU = NOT yet available in ≤ ES7.2D samples +5V and 1V8EXT must be ON during IC-reset ??
The IC can start generating HOUT line-drive pulses from only its 3.3V Standby supply voltage. This is called “Low voltage start-up”. The +VB for the FBT is normally well-stabilized (1%) by the SMPS (determines picture width). Secondary supplies that are scan-rectified from the FBT need NO stabilizers. Also the +5V second power supply for the IC can be generated in this way.
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SMPS
Mainstream Tv Solutions - 10-2003 – UOC-III presentation 1-17
Low voltage Start-Up:
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Full YUV-loop interface YPbPr input Tint and Peaking on peripherals (CVBS, Y/C, RGB, YPbPr) Scavem on ALL peripherals, plus independently for TXT/OSD Integrated 4H Comb filter (2D, time-discrete using digital techniques) Sound trap integration Economy histogram: ”White-Stretch" & "DC-transfer ratio" Programmable Black stretch function ("depth" and "area selection") Pseudo auto Y/C detector 3-bit Signal-to-Noise ratio measurement Integration of White Stretch capacitor
Mainstream Tv Solutions - 10-2003 – UOC-III presentation 1-18
features: Video
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New
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0,10 or 100p Txt with embedded memory Twin TXT Double window (Video/TXT - all inputs) Linear and non Linear H-Scaler (all inputs) Flash-programmable ROM Improved power down High-speed I2C Bus 64 DRCS, 32 four-colour characters Up to 16x18 font size RDS (Radio Data System) Character smoothing
Mainstream Tv Solutions - 10-2003 – UOC-III presentation 1-19
features: Micro / TXT
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New
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Global Stereo-TV processing & stereo FM radio (look TV, listen radio) BTSC with DBX noise reduction [Trademark of THAT Corporation] DDEP = Demodulator + Decoder Easy Programming ASD = Auto Standard Detection SSS = Static Standard Selection BBE = High definition BBE sound [Trademark of BBE sound, Inc] DBE = Dynamic Bass Enhancement DUB-II = Dynamic Ultrabass-2 SRS = surround + bass effects VDS = Virtual Dolby Surround (VDS422/423) Dolby Pro Logic Delay & Pseudo Hall / Matrix function I2S out for Sub-Woofer or full 5-channel DPL [Trademark of Dolby Laboratories] Smooth volume control, soft mute, loudness, bass, treble, Incredible mono / Incredible stereo Programmable beeper AV Stereo playback
Mainstream Tv Solutions - 10-2003 – UOC-III presentation 1-20
features: Sound
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New
NTSC Multi only Stereo Mono
User RAM [kB]
ROM [kB]
BBE
SRS TruSurround
SRS 3D stereo
Virtual Dolby
Dolby Pro Logic
RDS/RDBS DBX
FM radio
DW Panorama
Colour decoder
Comb filter
Mainstream Tv Solutions - 10-2003 – UOC-III presentation 1-21
256 8 128 4 Philips Semiconductors
Sound Multi BTSC Audio Mono 0 10 DSP stereo TDA110xx √ TDA120xx √ Type Number
Number of TXT pages
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type selection:
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Vref
DAC
“Cosmic”
TXT OSD CC RDS
“Picasso” UOCIII
“Hercules”
• Mixed process: BiMos + CMos = best of both worlds • Easy: “GTV” software takes care of all initialisations
Stereo Sound
Micro + Flash
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YUV
DAC
YUV
Split - screen Panorama
IF
Comb Colour Switch Filter Decoder
F
ADC
Sync
Peaking Saturation Contrast
YUV switch
Brightness RGB out
RGB switch
RGBF
Mainstream Tv Solutions - 10-2003 – UOC-III presentation 1-22
inside:
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GTV Function Function call within the GTV software Platform
In the Application Notes we are now using these naming conventions. E.G. a “TK”-bit is a bit that should typically be implemented in software as an optional bit. It can help the set maker to handle difficult problems in the field. E.g. by selecting a different compromise of time-constants for weak-signal areas. Note: Be careful with using TK-bits as they may have side-effects. Only use them in specific situations, disable them in all other situations.
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Control BIT Name, e.g: “VSW” FUNCTION Short description I/O Input = control bit, Output = status bit MACRO The device macro, where the bit is related to: - VIF&SIF Vision IF and Sound IF - Mono/stereo FM/AM demodulation & audio processing - Sync&Geo Horizontal and Vertical synchronisation & geometry - Power Power and Protection - In/Out Input / output for audio & video - Colour Colour decoder & filters - YUV Video control - RGB RGB output and control - Micro TCG Teletext, Control and Graphics FU Function class - SU Start-Up, set before switching-on from stand-by - AL Alignment, aligned during production, values set before switching on - SC Setmaker Control, controlling normal operation - UC User Control, accessible for the customer like contrast, brightness, etc. - TK Tool Kit, can help to improve performance under difficult working conditions like RF phase modulation, wrong burst/chroma ratio, etc.
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I2C-bit naming convention:
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+3.3V +5V 1.8V
EHT
24.576MHz Int PWM I/O ADC
Tuning UOC III “Hercules”
AGC
VIF & SIF
VIF
IF-PLL, AGC Lockdet, AFC Video-Amp. -Ident -Vsw Mute Groupdelay Soundtrap QSS
Osc
SIF Tuner
Mono 2nd
Sound IF AM, NBPLL-FM demodulator FM Lock Det. FmMute, AVL
Dictionary QSS, IFOUT
I2S
Power
Micro
Φ1+2 Sync
H-Osc. LV-start-up
Teletext,CC Control Graphics,OSD
H+V Geometry V divider, zoom
Geometry
H+V E/W
Stereo NICAM, A2, MPX, RDS Digital Audio Features
Audio Switch, 2x Volume
Goto
Sync
CVBS Y/C
Colour
YUV
Combfilter chroma-trap, -BP, Y-delay
Peak, Coring Saturation,Hue Scavem
PAL,NTSC,SECAM
Digital processing
Baseband-delay
Double window
In/Out
CVBS,Y/C, YUV/RGB, matrix
DVD (YPBPR) or RGB+FBL
YUV loop
SVM
RGB CRTcalibration BeamCurrent White Limit, Softclipping Stretching Brightness Contrast
RGB IBLACK IBEAM
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Mono
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Functional blocks:
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Mono
Power
Sync & Geometry
VIF & SIF
Colour
YUV
Micro
Stereo
Philips Semiconductors
RGB
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-1
Video- and sound-IF:
In/Out
File: Herc_2.ppt = Analogue part, v2.8, 30-09-2003 by E.Arnold
The diagrams in this presentation are intended to explain the functional behavior of a TV receiver with UOC-III “Hercules” concept. © Philips Electronics N.V. 2003 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The presented information does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Authors: Philips Semiconductors, BL-MTS E.C.P. Arnold Innovation Center Eindhoven, the Netherlands Stereo part: Ulf Buhse, Peter Schöning, Matthias Meyer S&A, Hamburg, Germany
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(Positive Modulation)
• Integrated IF-AGC time constant
(SW selectable)
• Integrated sound band-passes & traps
(4.5 / 5.5 / 6.0 / 6.5 MHz)
• Group delay compensation
(for “flat” multi-standard NTSC/PAL SAW filters)
• QSS versions with digital Second-Sound-IF SSIF
(AM demodulator for free)
• FM mono operation possible: Inter-Carrier or QSS
The IF frequency is calibrated, using the X-tal reference oscillator. A choice can be made for different IF frequencies. Positive and negative modulation are supported. Four different IF-AGC time constants can be chosen via I2C-bus, for optimal performance under various conditions. For positive modulation the AGC time constant is automatically adapted to a larger value. GTV Function: ptun_SetIFAGCSpeed The UOC-III family makes no difference anymore between QSS- and InterCarrier-IF, nearly all types are software-switchable between the two SAW-filter constructions.
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• Multi-Standard alignment free PLL-IF, including SECAM L / L’
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-2
IF:
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Quasi-Split Sound
DVB-hybrid AGC
BP
VIF+SIF
VIF
TV SAW
VIF TV TVSAW SIF RADIOSIFIF
Sw
10.7 MHz
SSIF
VIF
SIF S-AGC
Optional
BP
SSIF
DVB-Tuner
AGC TV SAW
Tuner
Tuner
FM Tuner
AGC TV VIF
(SIF)
TV SIF
SAW D-IF
DVBIF
(S-AGC)
AGCin
DVB add-on
(SSIF)
REFin
(INTCO)
(INTCO)
FMRO
DVBO
FM-10.7 radio
FM-Eco-radio
(mono/stereo)
(low cost add-on, re-using TV tuner) Tuner-AGC coupled to S-AGC
TV-IF modes: The cheapest IF mode is “Inter-Carrier”, using one SAW filter for both video and sound. Better separation of video and sound is achieved, using “QuasiSplit Sound”. The sound SAW is now optimised and passes > 10dB more sound carrier. This results is better sound sensitivity and higher quality video. FM-Radio modes: Adding a special FM-radio tuner plus 10.7MHz band pass gives the best result (FM tuner = optimised for phase-noise & selectivity). A QSS configuration allows double-use of the TV tuner for low-cost FM-Eco-radio implementation. The selectivity of the sound-SAW filter should be switched (FM radio = narrower than TV-FM-sound). Various mixing frequencies can be used (e.g. RIF=37.5MHz mixed with 43.008 gives 5.5MHz → FM-demodulator). Extra selectivity can be added externally, but is usually not needed. DVB mode: The IF spectrum (36MHz) is mixed-down to a “low-IF” frequency (4.5MHz) , that can be handled by an add-on DVB demodulator. If the fixed down-mix frequency does not match the DVB concept, the DVB part can deliver a reference carrier to the UOC-III.
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Inter-Carrier Sound
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-3
IF modes:
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Automatic Gain Control
Group Delay
IF-PLL loop filter IF-PLL, Xtal calibrated
Tuner
41
SAW PC
In-lockdetector & AFC
Colour Comb decoder filter VIF
Video AM demodulator
D E I IF L P M SI
Sound down mixer
39
SSIF IN SSIF-AGC
33
Sound Cross bar
Mono-FM
Mono MonoOUT + DeEmphasis
48 SVO
Sound trap
24 25 28
IF video
I/O switch
31
Stereo
NBPLL Narrow-Band-PLL FM demodulator 15K
SSIF AGC
55 CVBS2 58,59 Y/C3 51,52 Y/C4 72,70 Y/C5 64 CVBSO
49,50 56,57
AV4 AV3
34,35 36,37
AV1
53,54
AV2
62,63
HP
60,61
LS
DAC1 ADC DAC2
SSD
I2SIN/OUT 102..106
46
The embedded Comb Filter function (some UOC-III type numbers) improves the video decoding performance significantly. A single, combined video + audio SAW filter is known as “Inter carrier”. With the same UOC-III “Hercules” device, also a “QSS” construction can be made, using separate VIF (Video-IF) and SIF (Sound IF) SAW filters. Selection between QSS or IntC is done via software. Although all required traps & band-pass filters are integrated, we maintain flexibility to route the signals through external filters. This is useful for testing and/or for unforeseen field conditions (see next slide). Tuner
External trap Group Delay
Front-End out
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43 IFVO Tuner AGC
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-4
IF & sound path:
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IF-PLL loop filter 41
SAW PC
SAW
29 30
MOD
SIF QSS
SC 42
SIF-AGC
Sound AGC
AM demod.
Video Ident
Decoupling MonoOUT + DeEmphasis
INA..D,CS1A..D,SD2..0 FM radio mode uses the video mixer-path, to keep SC2..0, the Tuner-AGC operational QSS HP2..0 Sound FMA..B, L,Ext Cross MONO BPB2 bar AM Mute
SSIF IN SSIF-AGC
33 46
AM/FM
Mono FMI,FMWS Narrow-Band-PLL mono-FM demodulator FMA..E QSS AM
39
15K Mute +6dB
E2D, FMI
55 CVBS2 58,59 Y/C3 51,52 Y/C4 72,70 Y/C5 64 CVBSO
FMR
MOD 38
48 SVO/ CVBSI
GD
Colour Comb decoder YCD
BPB
VIF
Group Delay
CV2 FMA..D VSW mutes Front-End, but also connects SID tuner AGC to ground
FMR
24 25 28
Sound trap
43 IFVO SVO1/0
NBPLL
SM0/1,AM AGN FML/W L,Ext MONO
CMB2..0
SSIF AGC
49,50 56,57
AV4 AV3
34,35 36,37
AV1
53,54
AV2
62,63
HP
60,61
LS
VOL
Stereo Stereo DAC1 demodulator and ADC DAC2 DSPaudio processing Digital Digital demod+ Sound decoder Processor 5x I/O
106 105 104 103 102
I2SIN I2SOUT1 I2SOUT2 I2SCLK I2SWS
For European SCART TV sets the tuner-part must always remain active, but in Asia-Pacific the tuner can be shut-off ( bit VSW=1) when an external source is viewed. Please note that VSW also shorts the Tuner AGC output to ground. The DC-range (max. and min.) must be limited by external resistors, otherwise the Tuner AGC voltage may take very long to settle. GTV Function: pimg_SetVideoMute For flexibility you can take the Front-End signal outside the IC (IFVO, before or after the internal sound trap). An additional, external sound trap can be added in series with the signal path. Then it can be re-inserted via CVBSI or CVBS2. Doing so via CVBS2 keeps the option to have Front-End output at pin SVO. Further a 2-tuner system can be supported (e.g. one to “cable” plus another for “antenna”). The base-band-output of a secondary (PIP) tuner+IF can be crosslinked to the UOC-III : output via IFVO and input via CVBSI (or CVBS2). This avoids an antenna switch. Sound band-passes for FM mono demodulation are available at 4.5, 5.5, 6.0 and 6.5MHz. Other band-pass filters can be added outside the IC (4.72, 5.74). Frequency of internal trap/band pass is determined by FMA..FMD. GTV Function: psys_GetFMDemodulatorCentreFrequency, psnd_SetFMDemodulatorSelection FM radio IF (RIF) internally uses the part of the video mixer (FMR=1), so that the Tuner-AGC output remains operational during (Eco-) FM radio mode. GTV Function: ptun_SetTVFMMode
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-5
31
VSW
Philips Semiconductors
Tuner AGC
MOD,AGC0/1 Video AGC I/V LPF detector AGC LOCK AFC IFA..D,FFI Lock IF-PLL Det. IFS AFN
IFO2..0
swapper
VSW,TOP Gating
Mute Black-DC DVB/FMR
I/O switch
IF & sound:
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Below Reference
Above Reference Calibration tolerance 25kHz
RF too low, IF too high
RF too high, IF too low Resolution 25kHz/step (AFC7..0)
• Large AFC detection range (+/- 3.2MHz) allows fast & proportional tuning corrections (25kHz resolution) • AFC only valid when IF-PLL in-lock, practical range = -2MHz .. +500kHz (including SAW filter characteristic) • Switch AFC detection off when not needed (improves sound cross talk)
The frequency of the IF-PLL is calibrated with a tolerance of 25kHz. This same tolerance is applicable to the AFC-readout. Because the AFC read-out is very precise, it is possible to correct tuning deviations with ONE, proportional step. E.g when the transmitter is drifted away by 375kHz, it will take SW only one action to correct the tuning. We advice to keep such proportional jumps smaller than 800kHz; larger deviations can better be corrected in more than one step. When AFC indication is not needed, you can switch-off the detection mechanism via AFN=1. For critical applications this can help to improve framesynchronous cross-talk to the sound. SW can e.g. randomize reading back the AFC information. GTV Function: ptun_StartSearch / ptun_CancelSearch ptun_IsSearchActive ptun_TransmitterFound ptun_GetIdents ptun_SetAFCSwitch (Note: this sets AFN to 0)
Philips Semiconductors
FIF set by IFA/B/C
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-6
IF: AFC window:
RESTRICTED, contains NDA items
Phase modulation: Fast PLL time constant (follow carrier frequency variations)
Over modulation: Slow PLL time constant (don’t follow 180º jump)
For normal modulation, the standard loop filter is a good balance for most situations, with sufficient reserve. Phase modulation: When a high level of phase modulation (~FM modulation) of the AM carrier occurs, it helps to reduce the external filter time constant. This enables the IFPLL to follow the phase modulation faster. Over-modulation: When the modulation depth exceeds 100%, the phase of the AM carrier suddenly changes 180 degrees. The IF-PLL tries to follow this phase jump but this is NOT wanted. Performance can be improved by increasing the external filter time constant. This prevents the IF-PLL from over-reacting on these temporary phase inversions.
Philips Semiconductors
Normal modulation: Normal PLL time constant
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-7
Fast FiIter IF-PLL (FFI):
RESTRICTED, contains NDA items
Low carrier amplitude: Normal PLL time constant Better for over modulation
FFI=1 : PLL time constant automatically adapted to carrier level Better behaviour for phase modulation (FM) and over modulation
When both phase modulation and over-modulation occur, the requirements for the IF PLL loop filter are contradictory. Bit FFI adapts the time constant of the IF-PLL loop filter, depending on the IFamplitude of that moment: - Normal time constant for high modulation (= low carrier amplitude) - Fast time constant for low modulation (= high carrier amplitude) This can improve the reception performance under difficult conditions (both FM- and over-modulation of the picture carrier). When FFI is set to 1, the PLL time constant for low carrier levels is kept normal, while for higher carrier levels the PLL speed is increased. In this way, a better compromise between phase modulation and over- modulation is possible. GTV Function: ptun_SetFastFilterIFPLL Remarks: - FFI=1 has no influence on e.g. search-tuning speed - Use FFI only for negative modulation (MOD=0) - Use toolkit bit FFI=1 only if you really have to, we advice to implement it as a service-mode option
Philips Semiconductors
High carrier amplitude: Adapted PLL time constant Better for phase modulation (FM)
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-8
FFI=1: auto-adapt to level
RESTRICTED, contains NDA items
AFN FFI IFS STM
AFC Not active Fast Filter IF-PLL IF Sensitivity Search Tuning Mode
SETTING 1: IF PLL in lock C4HEX < –1.5MHz 00HEX = centre value 3CHEX > +1.5MHz 1: not active 0: normal, 1: fast 1: low sensitivity 1: less sensitive SL-bit
I / O MACRO O IF O IF
I I I I
IF IF IF Sync
FU REM SC SC 2-complement notation, resolution = 25kHz/step SC Non-IF mode TK SC SC During AutoStore
IFD IFA IFB IFC FMD FMR IF freq. selection 0 0 0 0 x 0 58.75 MHz 0 0 0 1 x 0 45.75 MHz 0 0 1 0 x 0 38.9 MHz 0 0 1 1 x 0 38.0 MHz 0 1 0 0 x 0 33.4 MHz 0 1 1 0 x 0 33.9 MHz
AREA Japan USA Europe China Secam L1 with 5.5 MHz shift Secam L1 with 5 MHz shift
1 x x x FM-Radio modes 0 x x x 0 1 0 1 0 1 1 1
FM-Radio mode (independent of VIF)
x
0
External reference Flexible DVB down-mix
1 0 0
x 1 1
10.7 MHz 43.008 MHz 49.152 MHz
Eco-FM-Radio mode
During eco-FM-radio mode the IF-PLL has no picture-carrier to lock-onto, instead it will be set to a fixed frequency (derived from Xtal). • fXTAL/4 * 7 = 24.576/4 * 7 = 43.008 MHz , or • fXTAL/4 * 8 = 24.576/4 * 8 = 49.152 MHz With a customized RIF-SAW it is also possible to use 10.7 MHz inter-carrier: • 43.008 – 10.7 = 32.308 MHz as RIF-SAW center-frequency, or • 49.152 – 10.7 = 38.452 MHz (→ check IF-frequency range of your tuner) Many other down mix possibilities are e.g. 43.008 - 37.508 = 5.5MHz. For 10.7MHz selectivity you can use a band-pass filter like e.g.: Murata “SFE 10.7 MS3 A 20 G”. - MS3=bandwidth 180kHz (needed with fully occupied FM-band), MS2=230kHz - A=accuracy center frequency is exactly 10.7 - 20=tolerance of +/-20kHz, 10=10kHz, 30=30kHz - G=flat group delay time, best for low distortion & large FM swing GTV Function: LOCK: ptun_GetIfPllLock AFC,AFN: ptun_SetAFCSwitch (Note: sets AFN to 0) FFI: ptun_SetFastFilterIFPLL IFS: ptun_SetIFSensitivity STM: ptun_SetFEIdentSensitivity
Philips Semiconductors
BITS FUNCTION LOCK IF PLL LOCK indication AFC7..0 AFC outputs
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-9
IF related bits (1):
RESTRICTED, contains NDA items
VAI VIM VSW MOD GD AGC1..0 AGC RDS
BITS TOP OIF
FUNCTION IF Lock Forced Video Signal IDent Video output signal Amplitude
SETTING I / O MACRO 1: do not calibrate I IF 1: video identified O IF 00: no correction I IF 10: –5% 11: +5% Video output Amplitude system I 1: +12% I IF Video Ident Mode, input selection for 0: CVBS1INT input, I IF SID-circuit 1: output source switch Video mute SWitch 1: mute I IF MODulation standard 1: positive I IF Group Delay correction 1: on I IF AGC time constant, 00: 0.7x, 01: normal I IF 10: 3x , 11: 6x normal sets the IF-AGC speed AGC readout 1: tuner AGC active O IF Demodulated Audio to RDS decoder 0: not active I IF
FUNCTION AGC Take-Over-Point Offset IF-PLL
STEPS 63 63
RANGE 0.4..80 mV Small DC-offset
MACRO IF IF
FU AL AL
FU REM SC For high modulation SC SC Level-out amplitude differences due to filtering or standard SC SC SC SC SC SC
Tuner AGC also off French SECAM-L/L1
For IF signal 20x slower when MOD=1 SC AGC below TOP SC
REM 20 H = neutral
• IF-PLL offset does NOT change calibrated centre-value (a slight offset can improve e.g. S/N ratio for QSS-sound or SECAM weak-signal performance)
IFLF=1 prevent the IF oscillator from being re-calibrated. This is useful only in European TV sets, where the Scart plug definition requires continuous tunerCVBS output. Normally IF calibration is vertically synchronised. But when external video is selected, the vertical is no longer synchronous to the tunerCVBS. If e.g. by over modulation the IF-PLL accidentally gets out of lock (LOCK=0), there is no need for a re-calibration, that might be visible in the tuner CVBS output signal. Keep IFLF=0 during channel-change & at start-up; the rest of the time it can be set to IFLF=1. GTV Function → IFLF: sys_SetCalibrationIFPLLDemodulator With OIF the IF-PLL can be given a small offset, for improved PLL behavior under noisy signal conditions. This depends on tuner + SAW filter, so OIF can best be a factory alignment (or set to 20HEX for no offset). Bit SID is an independent line-frequency detector, indicating valid CVBS signal. SID can be connected to CVBS1-internal (tuner signal), to improve catch / hold performance of the Front-End (see bits: SD2..0, VID, VDXEN, VDX). GTV Function → SID: ptun_GetIdents, ptun_GetVideoIdent, psys_GetVideoInputSignalIdent TV & VCR-combi: It is possible to keep the IF-part functional, while the H&V deflection is put into standby (STB=0). Simply maintain the +5V and set IFLF=1. In this situation the indication IFL (IF in-Lock) is less reliable, so please use SID instead (coupled to CVBS1-front-end).
Philips Semiconductors
BITS IFLF SID VA1..0
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-10
IF related bits (2):
RESTRICTED, contains NDA items
SSIF QSS VDXEN, VDX
FUNCTION AM or QSS/FM selection AM LOWer amplitude MONO FM demodulator on/off QSS amplifier connects FM demod. Internal (mono or stereo) External Second Sound IF input Output connection of QSS amplifier
SETTING I / O MACRO 0: QSS/FM, 1: AM I Sound 1: reduce with 6dB I Sound 1: NB-PLL active I Sound 0: to QSS-output I Sound 1: to demod. 1: from external input I Sound 0: not active I Sound 1: to QSSO / FM demod Coupling of gating functions between 0x: coupled if INA..D=0001 I IF 10: coupled VIF and synchronisation circuit 11: not coupled
IFO2..0 Pin 43 function
FU SC SC SC SC
REM AM-mono
Save power For test or external demod. SC See I/O switching SC Sound via VIF sound via SIF SC Improves performance
Pin 44 function
Remark
Mute Mute
High Ohmic output Without Sound Trap or Group Delay
000 001
Mute IFOUT
010 011 110
IFOUT after SndTrap Mute Including GD for flat SAW filter FMROUT / DVBOUT,P FMROUT / DVBOUT,N FM radio-IF Balanced DVB output when bit FMROUT / DVBOUT,SE Mute Single ended DVB FMR=1 Mute FMR / DVB
111
Black DC
100
OUT
Black DC
OUT,SE
Black-level-DC = mute without DC jump
??ES7.2D: IF-AGC set at 6x (max) can be too fast (see below)
Bit AM=1 also selects between AM and FM mono Front-End-sound (AM is used only in France). ??Temporary for ES7.2D: When IF-AGC is set at 6x speed, it can get stuck when sync fails. SW can solve this by checking for IVWF & reduce IF-AGC speed to 4x when IVWF=0.
GTV Function: AM: psnd_SetQssAm, psys_SetQssAmOutSelect AMLOW: psnd_SetAMDemodulatorGain MONO: psys_SetActivateFMmonoDemodulator FMI: psnd_SetQSSAmplifierOutputSelection, psys_SetConnectionOutputQSSAmplifier SSIF: psys_SetCombFilterControl QSS: psnd_SetQSSAmplifierMode, psys_SetQSSAmpMode VDXEN: psys_SetEnableVDX VDX: psys_GetModeIFSyncInterface
Philips Semiconductors
BITS AM AMLOW MONO FMI
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-11
IF related bits (3):
RESTRICTED, contains NDA items
BITS AGCM
FUNCTION DVB AGC M ode
EPVI
Enable Preset Value IF-PLL
SETTING 0: internal mode 1: external mode 1: value can be loaded
FUNCTION
PVI1
Preset Value IF-PLL-1
STEPS 255
PVI2
Preset Value IF-PLL-2
255
MACRO IF
I
IF
RANGE
FU REM SC Ext = AGC from DVB add-on SC DVB down-mix
MACRO FU REM IF
SC Load while EPVI=1 and External reference IFE= 1
Philips Semiconductors
BITS
I/O I
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-12
DVB related bits:
Proper AGC control requires feedback from a digital DVB demodulator. With AGCM=1, the SIFAGC pin 42 becomes an input for an analogue AGC control voltage (generated by DVB add-on). The Down-Mix function of UOC-III does not have a complete synthesizer. If a certain DVB add-on requires a different mixing frequency, the add-on can supply a reference into pin 33. The frequency of that reference should be programmed in PVI2/1 and latched after a strobe on bit EPVI. GTV Function: AGCM: ptun_SetAGCMode EPVI: psys_SetIFPLLOscillatorPresetValue IFE: PVI1: psys_SetIFPresetValue1 PVI2: psys_SetIFPresetValue2
RESTRICTED, contains NDA items
Power
Sync & Geometry
VIF & SIF
Colour
YUV
Micro
Stereo
RGB
In/Out
This “Mono” sound section refers to the mono sound decoder in the analogue part of UOCIII. The sound demodulator in the digital part (mono & stereo) is described in section “Stereo”.
Philips Semiconductors
Mono
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-13
Mono sound:
RESTRICTED, contains NDA items
• AM mono demodulator in QSS operation • Integrated sound band pass
(4.5 / 5.5 / 6.0 / 6.5 MHz)
• Alignment free (Narrow-Band) PLL FM demodulator, switchable: (4.5 / 4.72 / 5.5 / 5.74 / 6.0 / 6.5 MHz) • Second-Sound-IF-input (SSIF) and INTer-Carrier-Output (INTCO) for additional selectivity (4.72 / 5.74MHz & FM-radio modes)
The IF frequency is stabilised using the X-tal reference oscillator. Sound band pass filters are integrated, although for extremely critical signal circumstances it is still possible to add one externally.
Philips Semiconductors
• FM mono Inter-carrier or QSS operation
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-14
Mono sound & demodulator:
RESTRICTED, contains NDA items
AGC
fi = 360o Multiplier 0o
Clipper LPF
VOUT
The Multiplier in an AM sound demodulator folds the IF frequency spectrum back to zero Hz. Together with a Low-Pass-Filter this has the same effect as a bandpass filter in the IF stage. The incoming AM signal is rectified. After integration (LPF) the result is the amplitude variation (LF) of the IF spectrum.
Philips Semiconductors
External BPF (SAW) SIF
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-15
Synchronous AM demodulation:
RESTRICTED, contains NDA items
fi = 360o Multiplier
SSIF Set fOSC
90o
OSC Loop Filter
VOUT = 0 at 90o Narrow-Band PLL frequency range = fOSC +/- 150 kHzTYPICAL
VOUT = -1/2 at 45o
No external filters needed No filters needed
VOUT = +1/2 at 135o
(internally added for enhanced FM performance)
The narrow PLL loop filter is especially optimized for selectivity. Therefore the external bandpass filter can be omitted. The PLL frequency is selected via I2Cbus (gives improved sensitivity), making the NB-PLL solution multi-standard. To optimize the sound performance with extreme, non-standard signals it is still possible to add an external filter. Sound distortion, due to video contents: Before SAW, video modulation is purely AM. Due to Nyquist-slope, upper IF frequencies are attenuated. Result is AM-to-PM conversion. The IF-PLL will lock to this (PM-modulated) Picture Carrier and thus the PM can couple to audio: via the audio down-mixing (multiply FM with PM-distorted carrier). With black or full-white (or gray) video, the PM has a rhythm of mainly 16kHz. But when e.g a cross-hatch is applied, the video frequencies introduce extra side-bands around the PM distortion. This again pollutes audio demodulation. Audio THD should be measured with equipment that filters out only the applied audio modulation plus its harmonics. Otherwise you include noise into the THD measurement.
Philips Semiconductors
Internal BPF AGC
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-16
Narrow-Band PLL FM demodulator:
RESTRICTED, contains NDA items
Mono output + DeEmphasis
39
AGN=0 : 125mV AGN=1 : 250mV (nominal 27 kHz swing, 54% modulation) DSG=0 : SCARTOUT = 1VRMS (8V required) DSG=1 : SCARTOUT = 2VRMS
AGN 2.5V 15K
SM0/1
Volume + 12 dB
NBPLL
MAX. sound volume (DSG=1) 1400 1000
0 dB
C=33p for BTSC stereo
De emphasis level De emphasis level
500
C=3n9
oct dB/ +6 Sound output [mV]
-6
f1
dB/ oct
T=54µs
f2
100 10
100
1k
10k
100k
f
0.3
[Hz]
MIN. sound volume (mute)
- 64 dB
The high frequency roll-off is determined by the de-emphasis capacitor on pin DeEmph. The low frequency cut-off is determined by the value of the external decoupling capacitor on pin DecsDem. The capacitor value should remain < 22µF, to allow fast enough DC-settling, after the +5V is applied.
Philips Semiconductors
38 Decoupling
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-17
Audio frequency response NB-PLL:
RESTRICTED, contains NDA items
Bit BPB FMSound Carrier
Narrow Window Bits FMWS1..0 Wider Window
• Digital acquisition helper brings FM-PLL back in range, when it loses lock to the FM carrier (set auto-mute: SM1,0=0,1 to limit noise from acquisition helper)
SM1,0 = 1,0 permanently mutes the FM demodulator output. Software can select between SM1,0=1,0 and SM1,0=0,1 to mute or de-mute the Front-End FM-mono sound (NB-PLL). GTV Function: mono/av-stereo: psnd_SetMute()
Philips Semiconductors
Band Pass
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-18
FM-Window & Band pass:
RESTRICTED, contains NDA items
FM sound carrier selection 10.7 MHz radio (overrules FMA..C)
SETTING
FMR
TV mode or FM Radio mode
I/O
MACRO
FU
REM
Sound Sound
SC SC
Mono
1: 10.7 MHz carrier
I I
1: FM radio mode
I
Sound
SC
Video blanked
FMA FMB FMC FMD FMR FM - DEMOD. BP
SOUND TRAP REM
0
1
0
x
0
4.5 MHz
Intern 4.5 MHz
NTSC-M, PAL-M/N
0
1
1
x
0
4.724 MHz
Extern 4.5 MHz
2nd language Korea
0
0
0
x
0
5.5 MHz
Intern 5.5 MHz
PAL-BGIDK, SECAM-BG
0
0
1
x
0
5.74 MHz
Extern 5.5 MHz
2nd language A2
1 1
0 1
0 0
x x
0 0
6.0 MHz 6.5 MHz
Intern 6.0 MHz Intern 6.5 MHz
PAL-I PAL-DK, SECAM-DK
x 1
x 0
x 1
1 x
x 1
10.7 MHz 7.902 MHz
Extern x FM radio mode Extern Video blanked Eco FM radio USA
1
1
1
x
1
9.608 MHz
Extern Video blanked Eco FM radio Euro
• Eco FM radio uses narrow-RIF-SAW + fixed SIF-mixing frequency: - Euro : (Sound = 38.9 -5.5 =) 33.4MHz, mixed with 43.008MHz = 9.608MHz - USA : (Sound = 45.75 -4.5 =) 41.25MHz, mixed with 49.152MHz = 7.902MHz ⇒ Alternatives : 43.008 -37.508 = 5.5MHz or 49.152 -44.652 = 4.5MHz
The available functionality depends on the IC type number. In general, un-used bits have no effect, but they should be written “0” for compatibility with future versions. During eco-FM-radio mode the IF-PLL has no picture-carrier to lock-onto, instead it will be set to a fixed frequency (derived from Xtal). • fXTAL/4 * 7 = 24.576/4 * 7 = 43.008 MHz , or • fXTAL/4 * 8 = 24.576/4 * 8 = 49.152 MHz By using (narrow) SIF-SAW filters (for TV sound), the Narrow-Band PLL can directly demodulate mono FM-radio. GTV Function: FMR: ptun_SetTVFMMode FMA..FMD: psys_GetFMDemodulatorCentreFrequency
Philips Semiconductors
FUNCTION
FMA/B/C FMD
Also usable for Eco-FM radio modes
BITS
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-19
Mono Sound related bits (1):
RESTRICTED, contains NDA items
FUNCTION Automatic Volume Levelling mono AVL capacitor or East-West output AVL gain Maximal Narrow-Band FM PLL Lock FM PLL in Window (see FMWS) FM PLL Window Select
BPB BPB2
By-Pass sound Band pass filters By-Pass Band filter 2
MONO CMCA
MONO FM demodulator on/off Complete Mono Channel Active, mono out on HP outputs Adapted Gain for Ntsc mono sound Sound Mute
AGN SM1..0
BITS VOLL VOLR
FUNCTION VOLume control Left VOLume control Right
SETTING I / O MACRO 1: on I Sound I Sound 0: EW, 1: AVL available 1: maximal I Sound 1: PLL in lock O Sound 0: PLL in window O Sound 00: 100kHz narrow I Sound 01: 225kHz normal 10: 450kHz wide 11: 900kHz 1: filters bypassed I Sound 0: high-Q filter I Sound 1: 2nd filter bypassed 1: active I Sound 0: not active I Sound 1: active 1: +6dB gain I Sound 00: no mute I Sound 01: Auto-mute FM audio 10: mute FM/AM audio
STEPS 127 127
RANGE -70..0 dB -70..0 dB
MACRO Sound Sound
FU UC UC
FU UC SC SC SC SC SC
REM Shared pin Fast settling Digital acq. For FM radio, for selectivity, for high mod. for overmodulation
TK TK More range for overmodulation SC Off during stereo SC 1=No mono AVL, 0=AVL on HP-L SC SC “Auto” limits noise from digital acquisition-helper
REM Device without DSP QFP128 only
For areas where over-modulation is expected, FMWS1,0 can enlarge the FMPLL window to 900kHz (effective after the acquisition is complete). The 100kHz narrow window is only intended for FM-radio. The 225kHz window can be used for areas where over modulation never occurs. Use 450kHz for all other circumstances. GTV Function: FMWS: psnd_SetFmWindowSelect We advice to use SM1,0=0,1 for automatic muting of the mono FM-PLL demodulator (fast attack and slow decay of 20..40ms). Position SM1,0=1,0 can be used to mute the sound during channel switching. Position SM1,0=1,1 will not mute at all and is reserved for test purposes. Normally transmissions with standard “M” (=4.5MHz) sound have an FM swing of 25kHz, only half of the 50kHz of other FM sound standards. To obtain equal sound output level, the signal can be amplified by +6dB via AGN=1. During channel-change you can set AVLM=1 to get faster settling of the monoAVL-circuit to the new selected audio signal. GTV Function: AVL: psnd_SetAVL AVLE: psnd_SetAVLEnabledOnEastWestOutputPin AVLM: psnd_SetAVLGain
Philips Semiconductors
BITS AVL AVLE AVLM FML FMW FMWS1..0
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-20
Mono Sound related bits (2):
RESTRICTED, contains NDA items
BP-off makes FML more sensitive
BPB=1, sound band pass off yes
M-SAW selected ?
Follow SAW filter switching of the video-colour-search
= 4.5MHz Narrow
FMA,B,C= 5.5/6.0/6.5MHz
SAW filter
FMD=1, wait 3ms, FMD=0 Wait 10ms
Best order: 6.5→5.5→6.0→4.5
Read FML
Need SW integration of FML bit
yes
Max 10 times ? > 5x FML=1 ?
no
BPB=0, band pass on
BP-on makes FMW more reliable
Wait 20ms
5 out of 10 or earlier
Read FMW yes
FMW=0 means FM-NBPLL in window
Max 10 times ? > 5x FMW=0 ? Found: De-Mute
5 out of 10 or earlier
no
Toggling FMD necessary for ≤ ES7.2D, to “unstick” mono NB-PLL at: power on cycle, search tuning and changing system or channel
??
The Narrow-Band-PLL mono FM demodulator has a digital acquisition helper, with a frequency window around its calibrated center value (FMA/B/C). With the help of some software, an audio carrier search can be implemented. 1- Simply select an FM frequency. 2- Then wait and see if the PLL demodulator can lock (bit FML). 3- Finally check if the PLL-FM demodulator is in window (bit FMW). With BPB=1 the sound band passes are off. This makes FML more sensitive. With BPB=0 bit FMW is more reliable. A solution is to integrate FML and FMW by software over several read-outs. To avoid a false lock on other carriers (4.43 MHz colour, 5.85 MHz NICAM), the search order should be: 6.5 → 5.5 → 6.0 → 4.5 MHz. GTV Function: mono/av-stereo: psnd_DetectStandard After an FM carrier is found, the NB-PLL will try to stay locked. If the carrier goes outside the frequency window (FMWS1,0), the digital acquisition helper will quickly bring the NB-PLL back into the window. We advice to select FMWS1,0=1,0 (=450kHz) as best compromise between selectivity and over-modulation.
Philips Semiconductors
Mono: Narrow-band FM-PLL
FM-PLL carrier search
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-21
Audio Carrier Search:
RESTRICTED, contains NDA items
Power
Sync & Geometry
VIF & SIF
Colour
YUV
Micro
Stereo
RGB
In/Out
The digital demodulator can handle stereo and mono standards, independent of the analogue mono-NB-PLL demodulator.
Philips Semiconductors
Mono
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-22
Stereo sound:
RESTRICTED, contains NDA items
HP2..0 SC2..0
InL,R4 InL,R3
Analogue domain :
Digital domain :
InL,R4 InL,R3
Dual 5:1
InL,R2
InL,R2
AM/FM
AM/FM
Dual 8:1
Scart VOL/R, 8:1 HPVC HP
DSP SSIF AGC
ADC Dem Dec Noise gen
Vol/Bal:Aux1/2/3 L,R,C,Surr,Sw, AVL,BBE,VDS Dolby Pro Logic, Beep, Control ..
• 1st SIF = QSS down-mixing • AM demodulation • FM mono demodulation
LS output switch
SSIF
input switch
AM
ADC
External sound IF
2ND
FM
InL,R5
DCXO
SSIF
QSS
SIF
Tuner
InL,R5
DAC1 DAC2
I2S1 I2S2 I2S3
I2SOUT1 I2SOUT2 I2SIN/OUT3
• 2nd SSIF with separate AGC • Switch for external SSIF input • Analogue cross-bar switches • Volume controlled HP output
• Stereo sound demodulation • Output processing • Digital cross-bar switching • I2S In and outputs, FM stereo radio • DCXO Xtal oscillator trimming
I2C write address of SSD = B0 H I2C read address of SSD = B1 H
Philips Semiconductors
SAS2..0
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-23
Stereo audio processing:
RESTRICTED, contains NDA items
Video luminance
Sound carrier
Colour carrier(s)
Second sound carrier: FM or NICAM frequency
• Modulation Schemes for Terrestrial TV Sound Carriers: - FM (Frequency Modulation) - AM (Amplitude Modulation) - NICAM (DQPSK)
: most common : mono & only in France (L,L1) : Digital transmission
Philips Semiconductors
Multiplex standards
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-24
Evolution of Audio/Video standards:
RESTRICTED, contains NDA items
L+R
1
SAP (FM) dbx compressed
L-R dbx compressed
2
f/fH
3
4
5
EIAJ multiplex spectrum: 25 15 5 (L+R)/2 1
(L-R)/2 or “B” FM 2
Professional channel
Pilot 3
4
f/fH
6
6.5
Philips Semiconductors
25 15 5
Pilot
FM deviation [kHz]
50
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-25
BTSC multiplex spectrum:
RESTRICTED, contains NDA items
SAP/EIAJ
SSIF
FM/AM Ch 1
Down mixer
FM/AM Ch 2
Deci.
NICAM dec.
DCXO
ADC
Deci.
FM ident DemDec HW
•
Noise det.
DemDec part of Sound DSP decimation deemphasis dBx noise red. dematrix channel select Dem Dec Easy Programming
L/A
Audio Control Bass MgT
Beeper (L+R)/2
Digital Input Crossbar
MPX
Main Channel Processing Decoded Stereo-Left or Dual-A (or mono)
R/B Mono SAP
Noise / silence
Demodulators
Dolby External L,R Pro Logic or AM-mono VDS
Digital Output Crossbar
ADC
DAC1
SW Processing Decoded Stereo-Right or Dual-B (or mono) DAC2 Centre Channel Processing Surround Chan. Processing Mono from 1ST sound carrier AUX1/I2S1 Channel SAP from BTSC AUX2/I2S2 Channel AUX3/DAC1 Channel
I2S1 I2S2 I2S3
Audio Monitor
Auto L,R or dual A,B decoding, whatever standard detected or selected (or identical to “MONO” if no multi-channel available, indicated by flags: GST,GDU=0,0 )
•
MONO from 1ST sound carrier (FM or AM)
•
SAP (Second Audio Program) for BTSC, optional dbx decompression
•
DCXO Xtal oscillator trimming = more accuracy (+ phase adaptation for NICAM)
The DEMDEC decoding runs on a 32kHz basis. The sound DSP executes 108 MIPS. I2S input is only possible at 32kHz, in master-mode. Supported formats: Philips, Sony and Japanese LSB justified format.
Philips Semiconductors
EPICS7A Sound DSP + embedded firmware
AudExt
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-26
Demodulator / Decoder:
RESTRICTED, contains NDA items
System
M/N M
Mono BTSC + SAP EIAJ A2+ A2 Nicam Nicam A2 A2* A2 Nicam Nicam Stereo
M-Japan M-Korea B/G B/G I D/K
D/K L/L1 FM radio
• DBX
TM
Carriers [MHz] SC1 SC2 4.5 4.5 5 x fH 4.5 4.5 4.724 5.5 5.742 5.5 5.85 6.0 6.552 6.5 6.258 6.742 5.742 6.5 5.85 6.5 5.85 4.5 ..10.7 -
SC1 = mono mono MPX MPX ½(L+R) ½(L+R) mono mono ½(L+R)
mono AM MPX
SC2
FM-deviation [kHz] nom/max/over 15/25/50 - / - /50 pilot=15.7kHz FM - / - /15 15/25/50 pilot=55,1kHz ½(L-R) 15/25/50 R 27/50/80 Nicam 27/50/80 Nicam 27/50/80 R 27/50/80
Nicam Nicam -
27/50/80 AM index: 54/100/- [%] 40/75/150 pilot=19kHz
noise reduction included, according BTSC system specification
Philips Semiconductors
Standard
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-27
Supported Sound standards:
RESTRICTED, contains NDA items
DEMDEC = minimum SW interaction • Auto signal detection, identification, de-matrixing, muting, routing, selection of de-emphasis, type & level adjust • ASD = auto-standard detection, or SSS = static standard selection
DemDec EXPERT mode Static Standard Selection Auto Standard Detection
OVerModulation ADaPTation
• EXPERT mode = without automatism • Optional over-modulation adaptation to overcome problems with largely over-modulated FM carrier (China, India...)
Philips Semiconductors
• DDEP = intelligent user interface to
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-28
DDEP features:
RESTRICTED, contains NDA items
FUNCTION
SETTING
I / O MACRO FU REM I
SSD
SC
I
SSD
REST
Each bit enables detection of the sound carrier of a certain standard, Set at least one RESTart standard recognition
00: ASD, auto detect 01: SSS, forced standards 11: Expert mode xxxx1: 5.5MHz xxx1x: 6.5 xx1xx: 6.5 (France AM) x1xxx: 6.0 (UK,HongKong) 1xxxx: 4.5 (Kor, US, Jap) 01: toggle
I
SSD
DDMUTE
DemDecMUTE of decoder outputs
1: Soft Mute
I
SSD
SC B/G-A2+NICAM D/K-A2+NICAM L/L1-NICAM I – NICAM M-A2,BTSC,EIAJ SC E.g. after changing SAW+STDSEL SC Cosine, 32x2ms
OVMADPT
OVerModulationADaPTion
I
SSD
SC
I
SSD
UC SC
STDSEL4..0 STanDard SELection,
SAPDBX
1: Enable Second Audio Program DBX expansion 0: Use dbx for BTSC stereo 1: Use dbx for SAP FH acc. PAL used for BTSC pilot tone 1: PAL fH for BTSC pilot
I
SSD
STDRES4..0 STandarD REcognition Status
Standard & Stereo mode
O
SSD
SC
SNDMOD
0000: Normal 0001, 0010: Hall, Matrix 0011: DPL (normal centre) 0100: DPL 3-stereo 0101: DPL phantom centre 0110, 0111: VDS 422, 423 1000: SRS TruSurround 1001: Noise sequencing
I
SSD
UC
FHPAL
Sound MODe
GTV Platform: stereo: psnd_SetStandard, psnd_DetectStandard for EPMODE, STDSEL, REST, STDREST stereo: psnd_SetMute for DDMUTE stereo: psnd_SetEffect for SNDMOD stereo: psnd_SetSAPDecompression for SAPDBX Rest of bits is not implemented
Philips Semiconductors
BITS
EPMODE1..0 Easy Programming Mode
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-29
SSD control bits (1):
RESTRICTED, contains NDA items
FUNCTION
SETTING
MAIN Signal Source for LS 000: L/R or A/B (or mono) 001: MONO 010: SAP CENTERSS Idem for Centre channel SURROUNDSS Idem for Surround channel 011: Ext via ADC AUX1SS 100: I2S Idem for Aux1 channels AUX2SS 101: Noise Generator Idem Aux2 channels AUX3SS 110: Digital Silence Idem Aux3 channels MAINDM MAIN Digital Matrix 000: AB 001: [A+B]/2 forced mono AUX1DM 010: AA AUX2DM 011: BB AUX3DM 100: BA 110: Auto AA, if Dual received 111: Auto BB, if Dual received ASAFO1 Audio Select for DAC2L 0000, 0001: Main L, R 0010: Subwoofer ASAFO2 0011: Center Idem for output DAC2R ASDAC1L 0100: Surround Idem DAC1 left output ASDAC1R 0101, 0110: Aux1 L, R Idem right output ASI2S1L 0111, 1000: Aux2 L, R Idem I2S output 1 left ASI2S1R 1001, 1010: Aux3 L, R Idem right ASI2S2L 1011: Main Sum Idem I2S output 2 left ASI2S2R 1100: Digital Silence Idem right
GTV Function: psnd_Connect
I / O MACRO FU REM I
SSD
UC -If no stereo then mono -Mono first carrier -BTSC second audio -Ext or AM-mono -Master-mode only -For Dolby balance
I
SSD
I
SSD
UC -Stereo -Mono from stereo -Dual language A -Dual language B -LR swapped -Auto-Matrix on -Auto-Matrix on UC
Connect any signal to any output
Philips Semiconductors
BITS MAINSS
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-30
SSD control bits (2):
RESTRICTED, contains NDA items
Channel1: FM, 6.5MHz mono output Measure carrier amplitude, using ch. 2 AM demodulation
Phase 1: measure carrier amplitudes: (at least one) 4.5, 5.5, 6.0, 6.5MHz
2.
Determine maximum amplitude
3.
If maximum < threshold: FAILED
4.
Decide mono standard: B/G, D/K, M, I, L
5.
Phase 2: initiate search for multichannel standard(s)
6.
Signal result in status bits STDRES4..0
Find largest? 6.258
6.742
Channel 2: 6.258MHz FM, Europe IDENT on
Channel 2: 6.742MHz FM, Europe IDENT on
timeout Ident found? yes Set standard “D/K A2 (1)”
5.85
timeout Ident found? yes Set standard “D/K A2 (2)”
Channel 2: 5.85MHz FM, Europe IDENT on timeout NICAM found? yes Set standard “D/K NICAM”
5.742
Channel 2: 5.742MHz FM, Europe IDENT on timeout Ident found? yes Set standard “D/K A2 (3)”
This audio detection algorithm is executed by firmware in the audio DSP. It can be configured by embedded (GTV) software to suit a certain application. GTV Function: stereo: psnd_DetectStandard
Philips Semiconductors
Example: D/K search procedure
1.
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-31
Auto Standard Detection:
RESTRICTED, contains NDA items
Soft mute of DemDec outputs
DDMUTE=1, wait 32ms M-SAW selected ? STDSEL= 5.5/6.0/6.5MHz REST=0 →1 → 0 DDMUTE=1 Read STDRES4..0 yes
yes
Follow SAW filter switching of the video-colour-search
= 4.5MHz Narrow
SAW filter
Toggle to restart ASD process Keep sound muted Get result
Still searching ? DDMUTE=0, wait 32ms Adjust Back-End
De-mute DemDec outputs Possibly adapt AVL, volume-trim etc.
Found
• Automatic selection of Mono/Stereo or AA/BB for Dual (set user preference)
Philips Semiconductors
Stereo: using DDEP with ASD
ASD carrier search
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-32
Channel switch with ASD:
RESTRICTED, contains NDA items
AUX3/DAC1 Channel
(L+R)/2 SW SM
C SM S SM
S Delay
DAC2
AUX1 SM AUX2 SM AUX3 SM
DAC1
I2S1 I2S2 I2S3
Noise / Silence Audio Monitor
The Noise generator: - fulfills the DPL licensee requirements - produces weighted noise with >9dB/octave roll-off - has a center frequency between 500Hz and 1kHz - is selectable for all sources, in all combinations for L, R, Centre and Surround A Noise Sequencer (under user control) allows easier alignment of sound parameter balance between the speakers.
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-33
AUX2/I2S2 Channel
+
Philips Semiconductors
AUX1/I2S1 Channel
Main SM
Digital Output Crossbar
Master Volume +Trim
DVB or DBB
Main Equal C Equal
BBE
Bass Management
Pseudo Hall Matrix
(L-R)/2
S Msel
Beeper
Volume +Trim
Level Adjust
SIN
C Msel
S Bass C Bass Main Bass Tre Tre, Loud Tre Loud
SAP
CIN
(L+R)/2
Mono
Digital Input Crossbar
DemDec
R/B
S
VDS422/423 or TruSurround
DPL C
C
Ext R/B
L/A
Main Msel
L,R DPL
S-DPL
Main
AVL
L,R M/ST Ext L/A
Ext Spatial Stereo or Ext. Pseudo Stereo or 3D sound
Stereo Audio Back-End:
RESTRICTED, contains NDA items
Left Out
Right In
Right Out Level Detector (optional weighting)
Attack / Decay Filter
1/X
UREF
• Decay time constants: 20 ms, 2, 4, 8, 16 s • Weighted-mode reduces influence of bass components • Adjustable threshold UREF
(optional)
Philips Semiconductors
Left In
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-34
Stereo AVL: Auto Volume Leveling
RESTRICTED, contains NDA items
Mono
Extended Pseudo Stereo
Stereo
Extended Spatial Stereo
DPL encoded
Dolby Pro Logic
Virtual Dolby Surround
Philips Semiconductors
Source signal:
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-35
Sound-Field features:
RESTRICTED, contains NDA items TM
• Produces a larger sweet spot • SRS approved • “Centre” and “Space” control
TM
SRS TruSurround : • SRS TruSurround virtualizer (422/423), SRS approved “422” = 4 channels to 2 speakers (virtual centre + surround speakers) “423” = 4 channels to 3 speakers (virtual surround speakers)
Philips Semiconductors
• Retrieves the spatial information from any stereo signal
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-36
SRS 3D Sound:
RESTRICTED, contains NDA items TM
TM
• Stage includes Dolby 3 Stereo and Phantom (= no center speaker) mode • Noise sequencer & Bass ManagemenT
(BMT = bass redirection)
• VDS 422/423 according to Dolby specification, Dolby approved
Pseudo Hall / Matrix: • Pseudo Matrix:
Centre: (L+R)/2 Surround: (L-R)/2, up to 30 ms delayed
• Pseudo Hall:
Centre: (L+R)/2 Surround: (L+R)/2, up to 30 ms delayed
Philips Semiconductors
• DPL licensee requirements fulfilled
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-37
Dolby Pro Logic, Virtual Dolby Surround :
RESTRICTED, contains NDA items
Right
Adaptive Matrix
Left
Auto Balance
+ L*
+ +
C*
-3dB
R*
+ +
Surround Processing
S*
DPL Ph 3ST
-10dB
lp
SW’
lp
a1
L
DPL Ph 3ST DPL Ph 3ST
b1
L’
+
a3
C
+
C’
b3 a2
R
DPL Ph 3ST
b2
+
R’
a4
S
b4
S’
[dB] BMT1 BMT2 BMoff -10 -100 -100 a1 -10 -100 -100 a2 -10 -4.5 -100 a3 -10 -4.5 -100 a4 a4DPL -100 -100 -100 Sw 0 1 1 Flat Flat b1 HP b2 HP Flat Flat HP Flat b3 HP HP Flat b4 HP
Mode
DPL L C R S
Phantom L+C-3dB R+C-3dB S
3-Stereo L+S-6dB C R+S-6dB -
• Virtualize speaker(s) for “Centre” or “Surround”
• • •
BMT1 = single woofer system with improved filtering: small speakers for L, R, C, S plus extra SubWoofer BMT2 = normal center mode with bass splitter (DPL): large speakers for L, R; small for C, S (SW is optional) BMoff = wide center mode (DPL): large speakers for L, R, C; small speaker for S
The internal Low-Pass-filter for the SubWoofer can be switched flat, to allow the use of external SubWoofer filtering. If DPL is active, then a4DPL is used.
Philips Semiconductors
0 1
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-38
Dolby Pro Logic & Bass Management:
RESTRICTED, contains NDA items
Right In
Stereo expander
Mixer Right Out
• The Stereo Expander makes a more wide sound field (“Incredible-Stereo”) • The Mixer controls the intensity of the widening effect
(alpha)
Extended Pseudo Stereo (EPS): Left Out Mono
De-correlator
Stereo expander
Right Out
• The De-correlator produces a pseudo stereo signal from a mono signal • Control of effect intensity
(“Incredible-Mono”)
Philips Semiconductors
Left Out Left In
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-39
Extended Spatial Stereo (ESS):
RESTRICTED, contains NDA items
300
1k
3k
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-40
100
Loudness:
8k
dB +12 +10 +8 +6 +4 +2 +0 -2 -4 -6 -8 -10 -12 -14 20
50
100
200
500
1k
2k
• 5 bands equalisers in L/R-Main and Centre channels • -12dB to +12dB in 1dB steps
5k
10k
Hz
• Max. boost 18dB @20Hz, 4.5dB @16kHz; range 30dB • Adjustable non-attack-level & non-attack -frequency
Philips Semiconductors
5-band graphic Equaliser,
RESTRICTED, contains NDA items Dynamic Ultra Bass - II
Generate higher harmonics
Level Sensor
Headroom
Auto Gain
Left Out
Right Out
Advice: Do not combine DVB, DBB, BBE together
Right In
• Impression of deep bass, by shifting the bass info to higher frequencies • Used in small TV-Sets without subwoofer or full range speakers Dynamic Bass Enhancement
Dynamic Bass Boost (DBB): Left In Right In
Level Sensor
+12dB 0dB
60Hz
Left Out Right Out
Boost Control
• Level-dependant Bass-Boost, needs subwoofer or large main speakers
Philips Semiconductors
Left In
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-41
Dynamic Virtual Bass (DVB):
RESTRICTED, contains NDA items TM
loudspeaker
BBE
frequency
Amplitude
Amplitude Compensation
BBE
frequency
loudspeaker
• Dynamic delay compensation + program driven bass/treble augmentation • Improves reproduction of transients • Restores brilliance and clarity of original live sound
Philips Semiconductors
Audio Delay
Delay Compensation
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-42
BBE :
RESTRICTED, contains NDA items
M+L Left Out
LowL+M+L LowL+LowR=SW Sub Woofer control Right In LowR+M+R
M+R
½SW+M+L
(½SW)+M+L SW+2M+(L+R)
Right Out ½SW+ +M+R
-½SW-M-R
(-½SW)+M+R
• Usual construction: one amplifier is inverting ⇒ heavy load for SW speaker Left In
M+L Left Out
LowL+M+L LowL+LowR=SW Sub Woofer control
(½SW)+M+L SW+(L-R)
Right Out -½SW+M+R
Right In LowR+M+R
½SW+M+L
(-½SW)+M+R
M+R
• New: “Eco Sub Woofer” = better power efficiency for SW-speaker (selectable via software)
M L R LowL LowR SW
= Mono contents = most of the audio energy = Unique components in LEFT channel = Unique components in RIGHT channel = Low frequency contents of LEFT channel = Low frequency contents of RIGHT channel = Assembled from LowL and LowR
Usually one of the loudspeaker amplifiers is inverting. The low Sub Woofer spectrum can not be reproduced by the (small) L & R speakers, so no filtering is needed for L & R. But in this construction, the Sub Woofer speaker has to deal with a heavy extra load (+2M+L+R). Via software you can enable “Eco Sub Woofer” mode, that avoids this problem. Note: the 2 loudspeaker amplifiers must have the same polarity.
Philips Semiconductors
Left In
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-43
Eco Sub Woofer:
RESTRICTED, contains NDA items
range -15..+15dB (-84dB mute at “-16”), resolution 1dB
• Soft Mute/demute: cosine curve of 32 steps, rate = 2ms (takes 32 ms) • Master Volume & Trim: – Trim = baseline of Volume setting (per channel) – Master Volume = offset, added to the major audio channels Sum of Trim + Master Volume clipped to +24dB (max. gain) – Smooth Volume: 1/8dB steps, max. speed of 62,5dB/sec
• Bass & Treble:
(independent of equaliser = easy control)
– Range from -16dB up to +15dB – External resolution 1dB – Smooth: Internal resolution 1/32dB, max. rate of change 15.6dB/sec
During power-off state the outputs “LS” and “HP” are muted.
µC I2C-bus Master Volume
Trim +
Audio samples
Gain Module
Philips Semiconductors
• Level Adjust:
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-44
Level-adjust, Volume/Trim, Tone:
RESTRICTED, contains NDA items
(Bass, treble and loudness not affected)
– Master Volume + Trim limited to -30dB
• Static Control mode:
(Set Loudness none-attack level ≤ 0dB)
– Master Volume + Trim limited to -1dB – Bass, treble or equalizer limited to +8dB
• Dynamic Volume mode:
(Set Loudness none-attack level ≤ 0dB)
– Master Output signal limited to -3dB – Bass, treble not affected
• Dynamic Control mode:
(Set Loudness none-attack level ≤ 0dB)
– Master Volume + Trim limited to +3dB – Bass & treble dependent on volume (see graph)
Bass & Treble limiting in Dynamic Control mode:
Bass/Treble active +15dB
-12dB Master Volume +Trim
+10dB
-7dB Master Volume +Trim
+5dB
-2dB Master Volume +Trim
0dB
+3dB Master Volume +Trim
-16dB -16dB
0dB
+15dB
Bass/Treble selected
Philips Semiconductors
• Static Volume mode:
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-45
Clip management:
RESTRICTED, contains NDA items
Power
Sync & Geometry
VIF & SIF
Colour
YUV
Micro
Stereo
RGB
In/Out
Philips Semiconductors
Mono
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-46
In / Out switching:
RESTRICTED, contains NDA items
AV2+4
R/ C /PR G/Vid/Y B / PB
Vid C Y
Y,C4
CVBSO PIP
• • • •
2x full SCART 4x CVBS 3x S-VHS 2x DVD
AV3
A new feature is the capacitor at input YsyncIn. This allows DC re-clamping of the black-reference level, right before the sync-separator. This improves sync performance. The DC-level on CVBS output pins allow direct coupling of a 75Ω transistor buffer/driver: +5V
75 Ohm cable 1k
UOC- III
GTV Function: psnd_Connect()
75Ω
75Ω 1k
CVBSOUT
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-47
Y,C4 InL,R4
Sw0
YsyncIn
Yout
RGB2
InL,R5
Fbl2
InL,R3
Vid Fbl R/C G B
RIN LIN
LSL,R
Philips Semiconductors
G/Y
RIN LIN No YUV Loop
Stat R / PR
CVBS2
AV3
OutL,R2
SVO
RGB3
Fbl3
CVBS3
AV2
R L Vid
B / PB
CVBSO
InL,R4
YsyncIn
UVout
Yout
InL,R3
CVBS2
InL,R5
OutL,R2
SVO
RGB3
YUVin
Y
1x full SCART 1x SCART-in 3x CVBS 2x S-VHS 1x DVD
1k
AV1
Vid Fbl R G B
C
Loop
B / PB
RIN LIN
• • • • •
Vid
G/Y
InL,R2
OutL,R1
IFVO
Stat
Vid
LSL,R
PIP
RIN LIN
R / PR
AV1
R L Vid
C3
Stat
RIN LIN Feature
Vid Fbl R G B
Stat
Fbl3
R L Vid
RIN LIN
C3
R L Vid
CVBS3
InL,R2
IFVO
OutL,R1
SCART AV-switching (1):
RESTRICTED, contains NDA items
AV1
PB
AV2
GTV Function: psnd_Connect()
RIN LIN
Vid C
C /PR
Y AV3
Vid/Y AV4
PB
CVBSO PIP
LSL,R
• • • •
4x CVBS 3x S-VHS 2x DVD 1x MonitorOUT
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-48
RIN LIN
RGBF3 RGB2
InL,R4
Sw0
YsyncIn
Yout
InL,R3
CVBS2
RGB3
Vid
Y Monitor-OUT
AV3
RIN LIN PR
HP
CVBSO
Y
3x CVBS 2x S-VHS 1x DVD 1x MonitorOUT
Philips Semiconductors
Vid
AV2
No YUV Loop
Vid
Fbl3
InL,R2
HPL,R2
Y,C3
IFVO
SVO
OutL,R1
RIN LIN
InL,R5
InL,R4
C
Loop
PB
R L
• • • •
Vid
Y AV1
Y,C4
YUVin
Yout
YsyncIn
UVout
InL,R3
RGB3
CVBS2
Vid PR
Monitor-OUT
PIP
RIN LIN
InL,R5
Vid
HP
LSL,R
Fbl2
Vid
RIN LIN
Y,C4
RIN LIN
Feature
R L
Fbl3
InL,R2
Y,C3
HPL,R2
IFVO
OutL,R1
SVO
Cinch AV-switching (2):
RESTRICTED, contains NDA items
0
0
0
1
0 1 0 1 0 1 0 1
0 0 0 0 1 1 1 1
1 1 1 1 0 0 0 0
0 0 1 1 0 0 1 1
x 0 1 0 x x x x x x x
SVO1/0 SVO pin 48 function 00
Selected Video
CV2
CVBS1 CVBS1 CVBS2 CVBS2 Y2/C3 CVBS3 Y3/C3 CVBS4 Y4/C4 CVBS5 Y5/C5
Remark PIP output Mute CVBS1 Internal from IF CVBS2 “Internal” from pin CVBS2 CVBS2 Bit CV2 = 0 Y2+C3 No YCD in this position CVBS3 Y3+C3 CVBS4 Y + C added = CVBS Y4+C4 CVBS5 Only when YC=1 Y5+C5
Remark
01
IF video output (CVBS1) Selected Video Output
SCART, after Sound trap & GD See bit INA..D
10
IF video input
To Sound trap & Group Delay
0
CVBS signal at input
11
Spare
-
1
Y/C signal detected
YCD Y/C D etection
• Y/C Detection (YCD) only done once: directly after source-switching
The YCD detector compares the chroma-amplitude on the selected Y and C. For this it needs the chroma bandpass circuit, therefore the YCD detection can not be done continuously. GTV Function: IN: psys_SetSourceSwitch CV2: psys_SetCVBS2InputSignalSelection YCD: psys_GetOutputYCDetector
Philips Semiconductors
INA INB INC IND CS1A CS1B CS1C CS1D 0 0 0 0
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-49
Video switching CVBS/Y/C:
RESTRICTED, contains NDA items
Y
YUV2..0, IE3/2
Y
Clamp
U
V
RDS,TXT,CC
DVD/RGB2
RGB2
SYS
Digital Scaling & Double Window
Sync
C3 59 C4 52 C5 70
DVD insert
RGB insert
CVBSSEL
ADC
INTF CLD
YUV -toDVD
VBI
Clamp
DVD-level-YPRPB
YUV insert
U V
CLD
Clamp
INTF
DVD -toYUV
IntC
Clamp Colour decoder
55 58 51 72
RGB -toDVD
Comb
CVBS1 CVBS2 CVBS/Y3 CVBS/Y4 CVBS/Y5
CVBS & Y/C Switch
Y
Y U V
Clamp Digital insert
IE3/2,IN3,FI N,FINM, YUV2..0 Fast-Insertion control PIP RGB insert
PIP YUV insert
DINT
CVBSOUT 64
• External loop can be YUV or YPRPB (DVD) level (bit INTF) • Connect YSyncIN to YOUT via 100nF, for optimal sync clamping • PIP insertion possible over Double Window (after feature loop and digital interface)
All input signals are “translated” into YUV or YPRPB (=DVD) and can be looped through an external interface. In this loop you can insert e.g. a picture improvement feature or PIP. YOUT is always available, to be coupled to YSyncIN via 100nF, irrespective of the chosen input. All input signals can be routed through the digital interface for half-screencompression or panoramic-zoom. For PIP insertion you can use bit FINM to insert AFTER the digital interface. Please note that PIP insertion always requires a Fast-blank insertion control, so IE2 or IE3 and pin Fbl2 or Fbl3 must be activated too (but must be inactive during vertical). GTV Function: FINM: psys_SetFastInsertionMode INTF: psys_SetAmplitudePolarityYUV
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-50
V
72 71 70
Peaking,coring
U
RGB3 IN2
+PIP insert
Philips Semiconductors
73 YSync IN
75 76 74
DAC DAC DAC
B3 / PB
78 79 80
IN3
Scaling
Optional PIP or YUV-feature loop
ADC ADC
77
G3 / Y
Fbl3
R3 /PR
Insertion & loop-interface:
RESTRICTED, contains NDA items
B
0
001
0 1
C
0
010
-
D E F
0 0 0
011 100 101
G 0
110
0
H I
0 1
111 000
-
J
1
111
-
1
Function RGBF3 pins Function RGBF2 pins
RGBF3 input (IE3=1)
DVD3 input (IE3=1) DVD3 input (IE3=1) DVD3 input (IE3=1)
Remark
RGBF2 input (IE3,2=0,1) IE3=1 disables RGBF2 Loop interface DVD Loop interface YUV YUVF2 input (IE2=1) YUVF2 priority over RGBF3 DVD2 input DVD2 input (IE3=0) RGBF2 input (IE2=1) Loop interface DVD
RGBF3 priority over DVD2 IE3=1 disables DVD2 RGBF2 priority over DVD3
Loop interface YUV
DVD3 input (IE3=1)
YUVF2 input
RGBF3 input (IE3=1) DVD3 input (IE3=1)
CVBS5 or Y5/C5
YUVF2 priority over DVD3 RGBF3 priority over Y/C DVD3 priority over Y/C
• DVD = YPRPB = colour bar 100% saturation: Y= +1.0VPP, PR= +0.7VPP, PB= +0.7VPP • YUV =
colour bar 75% saturation: Y= +1.4VPP, U[B-Y]= -1.33VPP, V[R-Y]= -1.05VPP
• For insertion, always IE3/2 and pin Fbl3/2 must be activated (not for loop interface)
GTV Function: YC: psys_SetCVBS IE: pimg_SetRGBYUVBlankingEnable YUV: psys_SetRGBYUV INTF: psys_SetAmplitudePolarityYUV
Philips Semiconductors
Configuration YC YUV2..0 INTF A 0 000 -
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-51
Video configuration YUV/RGB/DVD:
RESTRICTED, contains NDA items
Remark
0 1
1 0
0 0
x low CVBS or YC mode low x
1
1
0
low low
0 0
1 1
0 1
x x
1 1
0 0
0 1
high x
1
1
0
1 1
1 1
0 0
1
1
1
low high Priority: YUV ⇒ RGB ⇒ DVD. high low If input-2 and input-3 are of the W hen both are RGB, condition IE3=1 disables high high same type, then input-3 gets RGB2 completely x x priority over input-2
high RGBF2, YUVF2 or DVD2 x RGB2, YUV2 or DVD2 x x
RGBF3 or DVD3 RGB3 or DVD3
Defined by bit INA..D
Switched on by Fbl2=high Forced on Switched on by Fbl3=high Forced on
• While FIN=1, pins Fbl2+Fbl3 are not in use but they can still be read via IN3/IN2 ⇒ useful as digital inputs • FINM=1 inserts fast-insertion after digital interface (PIP), full-insertion remains before digital interface
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-52
IE3 IE2 FIN Fbl3 Fbl2 Displayed source 0 0 x x x
Input
Output
Fbl3 Fbl2 IN3 IN2 low low low high
0 0
0 1
high low
1
0
high high
1
1
Bits IN3 and IN2 (while FIN=0) are sampled during the vertical interval (VBI). This allows software to detect the difference between fast-OSD-RGB-insertion (Fast-blanking overlay on just a few lines) and full-screen RGB insertion. Only during full screen insertion the Fbl3/2 line will be permanently high (so also during VBI). GTV Function: FIN: psys_SetForcedInsertion FINM: psys_SetFastInsertionMode IE: pimg_SetRGBYUVBlankingEnable IN: psys_SetSourceSwitch
Philips Semiconductors
Both enabled
One enabled
Both disabled
Switching priority YUV/RGB/DVD:
RESTRICTED, contains NDA items
•
Remark PIP inserts itself in the loop via its own switch, no OK Fbl required No RGB2/DVD2 is disabled during RGB3
PIP at RGBF2 over DVD3
OK
PIP at YUV2 over RGB3 PIP as DVD over anything
OK YUV has priority over RGB No PIP not possible as DVD
PIP at RGBF3 over RGB2
No RGBF2 permanently disabled while RGB3 enabled
PIP at RGBF3 over DVD2 PIP at RGBF3 over YUV2
OK RGB has priority over DVD OK RGB has priority over YUV (set FINM=1)
PIP insertion AFTER feature loops: set FINM=1 & use Fast-blanking
1. Insertion can always be done into a YUV- or DVD-loop interface 2. PIP can best be inserted as YUVF2, or in series with RGBF3 (via own switch) 3. Dual full-SCART with 2x RGB can only enable one RGB at a time
Philips Semiconductors
Fast insertion of e.g. PIP PIP as YUV into YUV- or DVD-loop PIP at RGBF2 over RGB3
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-53
Fast PIP insertion possibilities:
RESTRICTED, contains NDA items
64
V
Y
75 76 74
Insertion Y
73 YSync IN
U
V
72 71 70
PIP also Compressed
• PIP in YUV-loop uses its own insertion switch PIP insert RGBF or YUVF
FBL Y
U
V
Y
74
73
75
72 71 70
PIP not Compressed
• PIP only of CVBS or Y/C sources R G B FBL
PIP insert RGBF or YUVF +bypass RGBF
FBL
G
B
R
+ 75
72 71 70
• Outside PIP-area, PIP-IC bypasses external RGBF input
Now PIP can show RGB/YUV input
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-54
U
PIP in YUV-loop uses own switch
Philips Semiconductors
CVBSPIP
PIP use-cases:
RESTRICTED, contains NDA items
FM
InL,R5 InL,R4
Dual 5:1
InL,R3 InL,R2 FM AM
InL,R3 InL,R2 FM AM
SC2..0
Dual 8:1
Scart 8:1
VOL/R, HPVC HP
AM
External 2ND sound IF
SSIF AGC
ADC
DSP
SSIF
LS DAC1
ADC Dem Dec
Noise gen
Audio DSP
Optional
SMLS
DAC2
I2S1 I2S2 I2S3
DAC
I2SOUT1 I2SOUT2 I2SIN/OUT3
• SCART: DAC1 = Front-End signal InL,R1 Non-SCART: DAC1 = selected signal, unprocessed
AC3 DSP
SIF SSIF
QSS
Tuner
InL,R5 InL,R4
DAC
LS1 LS2 LS3 LS4
LS5 LS6 for test purposes
DAC
I2SIN
(from tuner) (SAS2..0)
• DAC2 available for monitor (outputs LS), when I2S DACs are added
(LS1..6)
• I2S = future-proof extension interface, e.g. to an AC3-decoding DSP
I2S outputs can be connected to an external DAC, e.g. UDA1334 DAC, to obtain more audio outputs. In that case the “LS” outputs can be serve as extra audio monitor outputs. I2S output offers “future-proof” extension possibilities, e.g. when you want to upgrade a TV with an additional DSP for AC3 decoding. In the current silicon the third I2S port has limited functionality (test purposes only). When volume-controlled HeadPhones outputs are not needed, bit HPVC=0 can bypass the amplifier. This enhances the S/N performance when HPOUT is used as “fixed-level” output. GTV Function: SAS register is used in psnd_Connect to establish signal paths. Bit HPVC has no implementation (initially set in LibCoMa)
Philips Semiconductors
HP2..0
SAS2..0
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-55
Audio stereo switching:
RESTRICTED, contains NDA items
DemDec
Audio DSP
LS
Left Right Centre Surround Sub Woofer
DAC2 DAC
I2S1 I2S2 I2S3
UDA1334BT
DAC UDA1334BT
SRC
SPDIF
•
DAC1
Dual 8 : 1 8:1 HPCV
Monitor bass+treble controlled Left Right Centre Surround
LS
DAC2
Monitor output is sound controlled
Headphone independently switchable
Virtual DPL
Eur-Eco DPL Dual 8 : 1 8:1 VOL
InL,R2/3/4/5 FM AM
LS
Left Right
DAC2
HP-out = only volume controlled
•
DSP
DAC1
Scart
Dual 8 : 1 8:1 HPCV
Scart or OFF
HP
FE DSP
DemDec
InL,R2/3/4/5 FM AM
•
InL,R2/3/4/5 FM AM
DemDec
Digital
•
Asia DPL HP
FE DAC1
Scart
DSP
Dual 8 : 1 8:1 VOL
DemDec
Analogue
InL,R2/3/4/5 FM AM
DAC1
LS
OFF or Centre OFF or Surr Left Right
DAC2
User-choice for either Scart-out or DPL
Full DPL: In European SCART chassis, the tuner signal (Front-End) must always remain present at the SCART output. This occupies DAC1. A full Dolby Pro-Logic implementation with 5 loudspeaker channels requires two external I2S DACs. Virtual DPL: The sound DSP inside UOC- III “Hercules” can also virtualize DPL, requiring just two audio amplifiers. European Eco DPL: This option allows the TV-user to decide between either SCART-Front-Endsound output or four independent channels for DPL. The Sub Woofer channel can be virtualized or connected between L&R amplifier outputs. Asia DPL: Asian TV chassis normally have a “monitor” output that reproduces the same audio & video as displayed on the TV screen (so Front-End = inactive while external sources are selected). If you don’t implement independent HeadPhones control, then 4 channels are available for DPL reproduction.
Philips Semiconductors
Full DPL
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-56
Stereo use-cases:
RESTRICTED, contains NDA items
I2S_D2 I/O pin
Data Mute
Sfor0 PCS
OutL
100Ω
OutR
Deem UDA1334
UOC- III “Hercules”
UDA1334
• Very simple application • I2S_Clk can be set 4 times faster to act as SysClk for noise shaping
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-57
I2S_D0 I2S_D1
BitClk WordSel
100Ω 220k
I2S_CLK I2S_WS
Sfor1
220k
VDDA
SysClk :4
VREF
Philips Semiconductors
1Ω VSSA
24.576MHz
VSSD
I2S_CLK = 256*fS BitClk = 64*fS I2S_WS = fS
1Ω
+3V3
“Floating” Xtal
VDDD
DCXO
I2S-DAC application:
RESTRICTED, contains NDA items
BITS
0
0
0
0 0 0 1 1 1 1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
Headphone Output: AM Scart/Cinch Output: 0 1 -
REMARK
Selector Audio Input FM-mono intern From NB-PLL AM-mono intern From AM demodulator Audio 2 input Audio 3 input Audio 4 input Audio 5 input DSP Fixed output DAC1 Not available at DSP vol contr output DAC2 audio INPUT selector Mute
FUNCTION
SETTING
0: bypassed 1: LS outputs muted D efine S ound G ain from input to output 0: 0dB, 1: +6dB
I / O MACRO FU REM
H P V C H ead P hones V o l u m e C ontrol active S M L S S ound M ute L S outputs
I
Sound
I
Sound
S C Not HP outputs
DSG
I
Sound
SC +6dB needs 8V
• 5 sources: four externals + one via Tuner (AM or FM)
GTV Function: psnd_Connect psnd_SetMuteChannel
S C Better S/N
Philips Semiconductors
HPO2 HPO1 HPO0 SO2 SO1 SO0 SAS2 SAS1 SAS0
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-58
Audio I/O switching:
RESTRICTED, contains NDA items
E2D,QSS
QSS AM FM-De15K Emphasis Mute Selected = Ext MONO
39
SM0/1,FMI,AM
VOL 62, 63
AM FMI
CMB Function of pin 33 I/O 2..0 000 Mono AVL capacitor (AVLE=0), I SIF to NB-PLL and Stereo Decod. 001 2.1V + chroma subcarrier REFOUT O 010 SWO low output < 0.8V O 011 SWO high output = 4.5V O 100 Reference carrier input for I DVB down-mix (REFIN) 101 SSIF to NB-PLL and Stereo Dec. I 111 SSIF input to mono NB-PLL, I intern SIF to Stereo Decoder
AudioOUT volumecontrolled
AVLE 21
East-West drive 110º Mono
East-West Amplifier Mono AVL capacitor
AVL AVL
ChromaRef OUT Switch output
2.1V+Ref OUT Ref to DVB IF down mixer
QSSOUT or SCARTOUT non-controlled
33 +4.5V
Mix Ref input
SSIF
To Stereo Decod. To mono NB-PLL
SSIF input CMB2..0
330..10kΩ
From intern SIF
The function of these pins depend on the chosen application, e.g the capacitor for mono-AVL can be connected at pin 21 or pin 33. CMB2..0=000: In a mono-FM-configuration pin 33 can be used to connect the AVL capacitor. CMB2..0=101 or 111: By setting bit SSIF=1, pin 33 can become a Second-Sound-IF input. Useful for: - FM-radio - external sound band pass filter for 2nd of dual-carrier sound 4.724, 5.74MHz - extra selectivity (4.5, 5.5, 6, 6.5MHz) for extremely difficult signal circumstances GTV Function: QSS: psnd_SetQSSAmplifierMode FMI: psnd_SetQSSAmplifierOutputSelection AM: psnd_SetQssAm E2D: ptun_SetAudioSignalOnAUDEEMPin CMB: psys_SetCombFilterControl
Philips Semiconductors
QSS FMI AM E2D Function pin 39 Mode 0 0 FM de-emphasis Intercarrier 0 1 Ext. audio Out 1 1 0 FM de-emphasis QSS-mono 1 1 1 Ext. audio Out 1 0 0 - QSS output QSS mode 0 1 1 - AM output
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-59
Options for pins 21,33,39,62,63:
RESTRICTED, contains NDA items
Ext
ExtSnd Int
Ext
SVO FM
CVBS1 Int DeEmph
CVBS In Ext Sound In
SCART1-output is always Front-End
CVBS Out Sound Out
15k
(tuner) E2D Int
Europe
Select
VOL Input CVBS2 Ext
Ext
ExtSnd Int
SVO
Ext
CVBS1 Int DeEmph
FM
15k E2D Int
Asia-Pacific Select
VOL
GTV Function: psnd_Connect
CVBS In Ext Sound In CVBS Out Sound Out
Monitor Out
Monitor-output is viewed source
Philips Semiconductors
SCART1 CVBS2 Ext
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-60
Source switching Europe ⇔ Asia:
RESTRICTED, contains NDA items
– Sound Mute can be combined on Vertical-GUARD
– LED can be multiplexed on local keyboard – Reset can be forced by short-circuiting “DecV1V8” – Mains-failure / PowerDown = connect to p27 EHT, read via bit XPR – Most I/O’s can be used as 3-level output, combine e.g. write-protect with Standby, or 2 standby modes...
• UART added for communication to add-on micro (DVB, DVD)
GTV Function: 3 level output: rbsc_SetMLPort Analogue value readout: rbsc_GetADC Switching from output to input an setting a value: rbsc_ConfigPort, rbsc_SetPin
Philips Semiconductors
• Many pins can be “doubled” :
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-61
More functions with LESS pins:
RESTRICTED, contains NDA items
3.3V LED 10k
LED
560
Mute
4.5V
VGM1,0 13 47k
Vguard
3.6V
Sample & Hold
TDA8357
NDF
EVG=1
Vertical blanking period Blanking of RGBOUT pins
UOC III “Hercules”
• Double use of Vguard-input-pin (e.g. as LED driver or as Mute-output) • Input: read bit NDF (=1 when guard-pulse fails), Vertical protection if bit EVG=1 • Open-drain Output : low when LED=1, floating during Vblank
GTV Function: NDF: psys_GetVerticalOutput EVG: psys_SetVerticalGuardMode LED: psys_SetModeLEDDriver
(1ms out of 20ms)
Philips Semiconductors
VGM1 VGM0 Mode of pin Vguard 0 0 Vertical Guard (bit NDF) 0 1 Vguard + LED output (0..3.3V) 1 0 Switch output (0..5V) 1 1 Input-only (result in bit NDF)
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-62
Vguard-input + I/O:
RESTRICTED, contains NDA items
I/OOUT Config. UOC III “Hercules”
Upper 0.75V of ADC range can not be used, due to +5V tolerant-construction of I/O pads.
1k2 150
S1
180
S2
240
S3
330
S4
470
S5
820
RL1
S0 0/
7
1/
7
2/
7
3/
7
4/
7
5/
7
6/
7
S6
LED 100k
P3.x/ ADC
ADCIN
+3.3V
RL2
• Keyboard scanning time-multiplexed with LED output (for Remote Control acknowledge & Error Signaling)
Reading back the ADC input costs just a few micro seconds. This is not noticeable in the light output of the LED. The ADC input range VDD,MINIMAL- 0.75 Volt is lost, due to internal protections that make I/O pins 5V tolerant. The ADC input has 8 bit resolution, so the resistor ladder network can be increased to handle more keys. In the application however, one should allow enough margin between the levels to handle noise from large currents flowing through ground tracks, cross talk etc. GTV Function: rbsc_GetLocalKeyboard rbsc_SetLEDState
Philips Semiconductors
+3.3V
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-63
Analogue Local Keyboard + LED:
RESTRICTED, contains NDA items
+3.3V
(due to +5V tolerant-construction of I/O pads)
0.75 * 100 / VDD,MIN = 75 / (3.3 * 90%) = 25,25% Highest usable level = 255 * 74.75% = 189D = BDH
ADC
S5
1
S4
SW level SW level 1
• Reserve ½ area noise margin above highest switch
1
• Choose e.g. R0 = 1.2kΩ (not too high, for noise immunity)
1
• Re-calculate levels with REAL resistors
½
820 1
R6
470
S6
R5
330
1
R4
240
½
R3
180
• Position each switch in the middle of its area, S0 needs only ½ area (no tolerance below zero)
VDDP R0
R2
150
• Divide this into the no. of keys you want, e.g. into 7 areas
1K2
25.25%
• Upper 0.75V of ADC range can not be used :
R1
S3 S2 S1 S0
• Re-calculate area-limits to be exactly in between chosen resistor divider levels ⇒ set in SW
In this example with 7 keys, standard range resistors can be used. The resistor tolerance should be less than 10%. We advice to use 5% types, allowing more noise margin in the application. E.g. for switch S4 the resistor divider should give: (R1+R2+R3+R4) / (R0+R1+R2+R3+R4) = KeyNumber / NumberOfKeys * AvailableRange = 4/7 * 74.75% = 0.43 Via a spreadsheet the resistor values and their ADC limiting values can be easily be calculated. So switch S4 is pressed when the software reads back an ADC value between 97D and 123D. The Hi-limit for S6 is ½ area above its center, leaving an extra noise margin under the Dead Zone ( = [74.75% * 255]-14 ). Absolute Sum Sum values Key Center R1..Rn Rn Practical R1..Rn Dead zone [V] 0.75 0 0.0000 0.00 0.00 0 0 Vdd, nominal [V] 3.3 1 0.1068 143.46 143.46 150 150 Minimal Vdd 90.00% 2 0.2136 325.87 182.41 330 180 R0 [Ohm] 1200 3 0.3203 565.61 239.73 570 240 NumberOfKeys 7 4 0.4271 894.71 329.11 900 330 8 bit DAC 255 5 0.5339 1374.61 479.90 1370 470 6 0.6407 2139.76 765.15 2190 Relative values 820 Dead zone [%] 25.25% AvailableRange 74.75%
Center 0.0000 0.1111 0.2157 0.3220 0.4286 0.5331 0.6460
GTV Function: LibCoMa Resource Basic Switches: RBSC_KEY1UPPERBORDER.. RBSC_KEY7UPPERBORDER
Hi-limit =Dec =Hex 0.0556 14 E 0.1634 42 29 0.2689 69 44 0.3753 96 5F 0.4808 123 7A 0.5895 150 96 177 B0 0.6941
Philips Semiconductors
ES6.2D samples: upper dead-zone of 1.3V plus lower dead zone of 200mV ??!!
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-64
Calculating Local Keyboard resistors:
RESTRICTED, contains NDA items
10k
+3V
Config
Config
Config
Mid
High
Out
Out
Hi Mid
47k
47k
Low
47k
47k
Out
Lo 10k
Open-Drain, low
Open-Drain, float
Push-Pull, high
3-level decoder + buffer: e.g. VST-3-band switch
• 3-levels by switching between Open-Drain and Push-Pull
+3V
10k 47k
On/Off-TV 47k
• Example: 2 standby modi for a TV+VCR combi
I/O UOC III
Lo =Off Mid=VCR stby Hi =On
Standby-VCR
10k
Software can change the I/O pin configuration at any moment. GTV Function: 3 level output: rbsc_SetMLPort Switching from output to input an setting a value: rbsc_ConfigPort, rbsc_SetPin
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-65
3.3V
1k
3.3V
3.3V
47k
3.3V
Philips Semiconductors
+8V
1k5
3-level outputs: drive more with less
RESTRICTED, contains NDA items
Power
Sync & Geometry
VIF & SIF
Colour
YUV
Micro
Stereo
RGB
In/Out
Philips Semiconductors
Mono
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-66
Power:
RESTRICTED, contains NDA items
Video-Signal-Processor (VSP) needs +3.3VSTBY and +5V Scart audio output level of 2VRMS needs +8V, else 1.2VRMS at +5V Digital part needs +1.8V ⇒ can be generated by IC (+external transistors) During SLEEP modes, +1.8V is generated inside the IC
Several Sleep modes: • Set I2C-bus bit STB=0 to stop HOUT deflection drive by the VSP If +5V is maintained, the VSP remains fully functional (for TV-VCR combi’s) • Set µC SFR bit ROMBK.STDBY=1 to disable: VSP, OSD, RDS, TXT/CCacquisition and Stereo sound Decoder (SSD) • Set SFR bit PCON.IDL=1 to halt SW execution of the 80C51-µC, while PWM, RCP, UART, I2C, INT, Timers/Counters, WatchDog stay active
When H+V deflection is not needed (e.g. VCR-mode or LCD-TV), all other functions in the VSP can be kept active, simply by maintaining +5V. If any of the +5V supply inputs fail (or too low), each has a supply-guard detector that will immediately stop the related functions in the VSP. In µC-STDBY mode the 8051 core remains fully functional, but the VSP is put to sleep. Before going into µC-IDLE mode, the software should enter µC-STDBY mode first. This takes care that after wake-up from IDLE mode, many circuits stay off. Another power mode called µC-POWERDOWN can be used instead of IDLE, but waking-up is then more difficult. In POWERDOWN mode only an external INTerrupt (or via the static SADAC) can wake-up towards STDBY mode. GTV Function: fpmt_SetPowerState psys_SetTVProcessorStandby
Philips Semiconductors
• • • •
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-67
Power supply inputs:
RESTRICTED, contains NDA items
no
-
??mA 40mA 10mA ??mA
-
STB=0
-
STB=x
off off coma
On = All functionality available on
VCR mode = Front-end still active Deflection off µC fully functional (set OSD=off) limited µC-STDBY mode (Remote wake-up) IDLE µC-IDLE mode (using RCP) Clock µC-POWERDOWN mode stop Re-activate via INTerrupt or reset
• Startup Standby ⇒ Application mode can be done from 3.3V-only • Mode Stop = Clock off ⇒ slower wake-up ⇒ check compatibility with Remote Control protocol (may miss first command, mode STOP needs repeating full command codes like with RC-5)
In Standby & Idle the external 1.8V for the u-processor is switched off. Only a part of the digital core is kept alive, to detect wake-up events, by an internal 1.8V, derived from the 3.3V standby supply. It is even allowed to generate the 1.8V in the line output stage, when switching to Standby & Idle, this 1.8V supply will automatically be 0. To get the lower power consumption, the digital Micro-core still has to be switched to IDLE mode (bit PCON.IDL). In the transition to Standby mode, the micro must first disable the OSD. Prior to entering IDLE or POWERDOWN always invoke µC-STDBY mode first (bit ROMBK.STDBY), to avoids high current peaks at wake-up. During Idle mode the RCP (Remote Control pre-Processor) should be used to reduce false wake-up & obtain optimal power saving. In mode Stop the internal clocks are halted. Re-starting takes more time. Therefor this mode is not suitable when a RC-protocol is used that doesn’t repeat the whole command code at every key-repetition (e.g. NEC: sends keycode only once, followed by fixed repeat-codes). If you missed the first command, you can not detect what it was
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-68
-
on tuner
280mA STB=0
off
no
TV Micro Remark part part
Philips Semiconductors
Stop
Sleep
transition Standby Idle
on
190mA 2mA 100mA
280mA STB=1
off
VCR
HOUT
on
2.5VOUT
Application 190mA 2mA 100mA mode
+1.8V (extern)
DecDig
+5V needed
Mode
+8V (+5V) +3.3V Standby
Power Modes:
RESTRICTED, contains NDA items
SW set I2Cbit STB=0
Application Mode
SW set SFR PCON.IDL=1
SW set SFR ROMBK.STDBY=1
µC-Idle mode
µC-Standby HW resets
Transition
Any interrupt : Timer/RCP/Ext/UART/ I2C/WatchDog/…
IDL/PD
Only External interrupt SW set bit STB=1
HOUT = active +5V = needed 1.8V loop active
Soft-Mute audio, Disable amplifier
SW set SFR ROMBK.STDBY=0
HOUT = off +5V = not required 1.8V loop active
VSP disabled 1.8V loop off OSD/TXT/CC off
µC-PowerDown SW set SFR PCON.PD=1
Moving from “Application-Mode” to “µC-IDLE-mode” always goes via a short “Transition-state” and then to “µC-STANDBY-mode”. Software must set µC-STANDBY prior to entering IDLE-mode, because every interrupt from e.g. Remote control (RCP) or timer (e.g. wake-up-timer) will bring the µC back to STANDBY-mode (and the VSP stays asleep). For minimal TV-sleep-mode power we advice to use the RCP. This will reduce the number of false wake-ups significantly. As estimated average TV-sleepmode power you can use: 90% µC-IDLE-current + 10% µC-STANDBY-current. GTV Function: fpmt_SetPowerState
Philips Semiconductors
SW set OSD off, SFR SADB.SSD_ON=0
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-69
Control of Standby Modes:
RESTRICTED, contains NDA items
DecV1V8
+3.3VddA1
1.8V
max +1.8V
INT,Timers, RC-Preproc 80C51 core & FlashProm
Detector 2.1V shortens lifetime drastically. A built-in detector (bit SUPR=1) signals this unwanted situation (e.g. show error message on OSD)
The UOC- III “Hercules” avoids the need of (expensive) 1.8V stabilisers. Instead, it offers a 2.5V (3mA) output (pin DecDig) for an emitter-follower (PNP-boosted NPN), with analogue feedback via 1.8V input pin 96. Note: It is not allowed to pull current out of the 1.8V inputs. Use emitter- or diode-type to supply these pins (or supply 1.8V out of 3.3VSTANDBY). It is important to avoid dangerous situation by accidentally short circuiting of components or shorts in components due to end of lifetime. On this aspect “Hercules” has similar robustness as the TDA95xx UOC family. GTV Function: psys_GetSupplyProtection
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Short-circuits:
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-72
Protection strategy external transistors:
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FUNCTION Enable Vertical Guard No vertical DeFlection guard pulse Direct restart after Flash protection
XDT X-ray DeTection XPR X-ray PRotection
• Flash protection:
SETTING I/O 1: enable protection I 1: failure O 0: soft restart I 1: direct restart 0: protection I 1: overvoltage O
MACRO Pow/Prot Pow/Prot Pow/Prot
FU REM SC Mute RGB OUT UC SC PHI2 pin
Pow/Prot SC Pow/Prot SC EHTO pin
(anti-glitch : condition must be active > 1µs)
– pulling pin p17 “PHI2” > 4.1V forces an immediate-stop – when pin is back to normal level: • DFL=0: restart HOUT via softstart (= best safety for H deflection circuit) • DFL=1: restart HOUT direct (= shortest HOUT disruption)
• X-ray protection:
(anti-glitch : condition must be active > 1µs)
– pulling pin 32 “EHTO” > 3.9V sets XPR=1 & forces slow-stop of HOUT – XDT=1 disables auto-switch-off, but error condition (XPR=1) can still be read
• Vertical Guard: when EVG=1, condition NDF=1 mutes RGBOUT
Status bit XPR is latched and cleared after an I2C-bus read action, unless the fault condition still exists. XPR is triggered when the EHT-compensation pin 32 is forced outside its normal operating range (1.2 .. 2.8V), above 3.9V. XPR=1 will cause a slow-stop of the horizontal line drive (HOUT, pin 67) plus discharge of the picture tube (OSO=1). This protection can be disabled by setting XDT=1. Hint: Pin 32 can be used for switch-off via the mains switch, using an external detection circuit to monitor when the supply voltage drops. Pulling phi-2 pin 17 above 4.1V will immediately stop HOUT. If pin 17 is left floating again, the line drive will automatically restart (Unless software reacts to protection bits like SUP before HOUT is restarted) : - with DFL=0 it will do a gentle soft-restart. - with DFL=1 it will immediately continue with normal HOUT periods. This gives fastest recovery, but make sure that your line-deflection stage can handle it. To prevent built-in protections from reacting on glitches, pins 17 or pin 32 must be kept above trigger voltage longer than 1 µs before the protection will act. Status bit NDF is NOT latched. It is cleared after the fault condition is removed. In some chassis during source- or channel-change the vertical guard pulse is missing for some frames. Therefore we advice to check NDF=1 during at least > 200ms, before reacting to it in software (e.g. switch to standby).
Philips Semiconductors
BITS EVG NDF DFL
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-73
Power & protection related bits (1):
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FUNCTION Power On Reset STandBy
SETTING I / O MACRO FU REM 1: failure detected O Pow/Prot SC 0: standby of TV proc. I Pow/Prot UC 1: operational DEFL DEFLection timer enable 1: read-out enabled I Pow/Prot SC DFL4..0 DeFLection timer read-out 5-bits status O Pow/Prot SC Slow start/stop
• Software must read POR until POR=0
(POR and XPR are cleared after reading)
• When POR=1 or XPR=1 : software MUST reset STB=0, BEFORE switching on again (STB=1) • New: If Flash-prot did shut-down HOUT, SW can detect this via DFL4..0 • HOUT slow-start process takes at least 1175ms (DFL4..0)
Status bit POR is cleared after an I2C-bus read action, unless the reset condition still exists. POR is only related to the 3.3V part of the VSP and the reset input. It has nothing to do with the 5V part. When POR=1, all I2C register data needs to be rewritten: after POR=0 again. Bits DFL4..0 represent the status of slow-start (-stop). With DEFL=1 the software can read this to monitor the line-start-up (-shut-down) process. GTV Function: POR: psys_GetTVProcessorPOR STB: psys_SetTVProcessorStandby DEFL: psys_SetReadOutDeflectionTimerControl DFL: psys_SetFlashProtection EVG: psys_SetVerticalGuardMode NDF: psys_GetVerticalOutput DFL: psys_SetFlashProtection XDT: psys_SetOvervoltageInputMode XPR: psys_GetXrayProtection
Philips Semiconductors
BITS POR STB
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-74
Power & protection related bits (2):
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• Conditions that trigger SUP=0 will also slow-stop HOUT: – when VP1,2,3 or VDDCOMB drop below 4.0V – BGDEC drops below 2.1V
• ⇒ DSU : HOUT automatically restarts when SUP=1 again
NOTE: only works with proper designed application where nobody pulls the phi-2 pin too high during start-up, otherwise: switch on via “TV-Switch-On”
• ⇒ MSU / LSU : SW has to toggle STB:=1→0→1, before HOUT restarts + execute “TV-Switch-On” (can not restart automatic because 5V derived from line deflection)
• An “1.8V” supply higher than 2.1V drastically shortens life-time Software should check SUPR=1 and show there is a problem
Important : when the 5V falls below a certain level (4V), other protection bits can accidentally get triggered. If e.g. XPR=1, the HOUT will NOT automatically restart. Therefore all UOC- III “HERCULES” software should continuously check POR, XPR (or disable the protection functions). Short spikes on the 5V supply can be handled by the HERCULES itself. If software reads SUP=0 for more than 40ms, we advice to switch to standby (STB=0). GTV Platform: SUP: psys_GetTVProcessorPowerSupply SUPR: psys_GetSupplyProtection
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BITS FUNCTION SETTING I / O MACRO FU REM SUP 5/8 Volt SUPply present 1 : OK O Pow/Prot SC SUPR 1.8 Volt SUPply Risen > 2.1V 1 : 1.8V too high O Pow/Prot SC Dangerously high
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-75
Power & protection related bits (3):
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DFL
Bit function ON/OFF selection of duty cycle Hout Set switch-off Hout with vert. defl in overscan Alternative function when Vguard not used Flash-protection: during start-up force to ‘1’, after start-up make choise Xray Detection/Protection
XDT
FBC RBL RGBL DDLE red defl ssd hsnf
Fixed beam current during switch-off Force RGB Blanking Force RGB Blanking during start-up DecDig loop selection disable REFOK enable readout deflection timer soft start-up enable/disabled speed of I2C-bus
Bit name POR XPR NDF SUP SUPR setoff dfl0..dfl4
Bit function Power on Reset Xray prot No vert. defl Supplies OK 1.8V to high prot read back when soft stop has finished read back of deflection timer
Remark If needed:must be set during STB=0 If needed:must be set during STB=0
- if Protection: set switched to STB and XPR output bit is set to ‘1’, after reading and recovering, XPR output bit to ‘0’ To start-up toggle STB ->0->1 - if Detection: XPR output bit is set to ‘1’, after reading and recovering, XPR output bit to ‘0’ Blanking level under control of CCC-loop Fixed blanking level
Useful for e.g. LCD-TV
OUTPUT BITS important for PMT Remark
GTV Function: STB: psys_SetTVProcessorStandby SDC: psys_SetDutyCycleHorizontalDrive OSO: psys_SetVerticalScanAtSwitchOff VGM: psys_SetFunctionVguardSwioPin DFL: psys_SetFlashProtection XDT: psys_SetOvervoltageInputMode FBC: psys_SetFixedBeamCurrentSwitchOff RBL: pimg_SetRGBBlanking RGBL: pimg_SetRGBOutputBlanking DDLE: RED: psys_SetREFOKBit DEFL: psys_SetReadOutDeflectionTimerControl SSD: psys_SetSlowStartUpMode POR: psys_GetTVProcessorPOR XPR: psys_GetXrayProtection NDF: psys_GetVerticalOutput SUP: psys_GetTVProcessorPowerSupply SUPR: psys_GetSupplyProtection DFL: psys_SetFlashProtection
Philips Semiconductors
INPUT BITS important for Power ManagemenT (VSP = “COSMIC”) Bit name STB SDC OSO VGM1..0
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-76
Important bits for PMT:
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Method A Method B Method C Store cap-bank value in Eeprom “Power-On” ??
To TV-standby
Choose the method you like SW should recall this value every time AC-on
Consistency Check
+5V & 1.8VEXT available @ reset Go into TV-standby or switch-on ?
On or Off ? On ??
Check SSD availability “Load DCXO cap-bank”
Load optimal value from Eeprom Check for start-up problems
“TV-Switch-On” Serious problem?
No
Yes
2.7V, the VSP-digital part is in control & forces HOUT=high • 2.5VDECDIG & 1.8VPERMANENT will come-up too (µC internal reset sequence begins > 1.2V) until software starts running, then SW enables 5V & 1.8VSWITCHED
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-79
4.0V
5VSWITCHED
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5.0V
Moment of AC-on
Example: AC-on for DSU
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– Cosmic initialises itself automatically • Hout forced high (protection when 3V3 1.4V (1V8EXT keeps 8051 reset, will change) • µC begins internal reset (takes several ms, most I/O pins set LOW) 2 • SW Init I C, “Load DCXO-cap-bank” (get optimal value from Eeprom or from FLASH) • SW initialise WatchDog, RCP, I/O pins …. • IF TV-set has to stay asleep (e.g. read on/off status back from Eeprom) THEN SW switch “TV-Sleep” ELSE - SW refresh configuration control of µC & SSD and SW Reset-OSD - SW make sure µC is NOT in SLEEP-mode (µC-STBY/IDLE/POWERDOWN) - SW read VSP status until VSP-POR=0
• Now the SW can begin with “TV-Switch-On”
GTV Function: fpmt_SetPowerState
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• 3V3STB rises:
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-80
DSU / MSU: Power-On
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(µC-STANDBY/IDLE/POWERDOWN)
– SW check POR=0, “Reset-OSD”, Init SSD (keep sound muted) – SW write all I2C registers, always keep STB=0 (RGBL=RBL=DFL=1, OPC=AKB=0) • Optional: choose OSO,FBC,SDC,VGM, (reduce VSP version control register FFH) • Optional: to use 1V8 loop: set DDLI=1 (else DigDec fixed at 2.5V) – DSU: SW check VSP-SUP=OK (8/5V>4V, clock=OK, 3V3>2.7V, DecDig>2V, BGDec>2V) MSU: No check on SUP (5V comes from line deflection LOT/FBT) – Optional: SW (re-)enable desired protections XDT,EVG – SW activate supply for FBT/LOT line deflection stage (can also be done with DecDig) – SW activate HOUT: STB=1 – IF startup fails (too long > 5s) (SW check DFL4..0 ) THEN do a “Safety-Shut-Down” (and blink error LED) ELSE (no need to check SUP ⇒ is already part of DFL4..0 during slow-start) – IF VGUARD used (EVG=1 to enable VGUARD-protection) THEN check that vertical reads back NDF=0 within 1000ms – Optional: SW (re-)enable desired protection DFL – Start up the CCC loop (black current + RGB gain stabilisation)
During the slow-start-process we advice to set DFL=1. In applications with Flash-detection circuitry or Dynamic Phase-compensation connected to the Phi2-pin, the extra wires can sometimes lift the DC level on the pin too high (With DFL=0 this would cause a slow-restart, perhaps even multiple restarts). After Slow-Start is completed, SW can set DFL according set-makers choice. The slow-start-process begins with setting STB=1. If DEFL=1 the SW can now monitor the start-up of HOUT. Normally this takes 1175ms unless any protection mechanism is activated. Should the start-up take much too long (>5s), then software can best do a safety shut-down (e.g. retry 3 times and then stay off). Set STB=0, switch-off and show the error (e.g. on an LED). If a vertical guard pulse is connected, bit NDF (No DeFlection) can be checked to verify correct operation of the vertical deflection stage. Use this option always together with EVG=1 (Enable Vertical Guard), to mute the display and prevent damage to the picture tube. If software keeps on reading NDF=1 for more than 1000ms after SUP=1, apparently the vertical deflection is damaged. Set STB=0, switch-off and show the error (LED). Bit NDF=1 can be caused by more conditions: - Vertical guard pulse: not present / low enough / high enough / wrong timing - Vertical ramp capacitor (150nF) short-circuited
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• Precondition: µC NOT in any sleep mode
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-81
DSU/MSU: TV-Switch-On
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(read all VSP status bits in ONE action) (3V3, DecDig) (1.8V too high) (no vertical) (no +5/8V) (HOUT off via slow-stop, when possible) (µC=standby + VSP=sleep, DecDig=low) (discharge, retry 3 times) (blink error LED, signal WHY) (Xray prot via EHT pin) (flash prot triggered)
Regular check: When the TV in running, the timing for error conditions is different from the “cold” start-up timing. Some status bits are latched (POR, XPR) others are not. All status bits should be read within one I2C-bus message. This avoids that one routine clears a latched bit, that should have been read by another routine. Safety Shut Down: After switching to standby we advice to insert some delay time, to discharge power supply capacitors. If e.g. during a flash-over or spark-test some circuit has gone into latch-up, the problem is often removed by powering it down. The advised procedure gives a balanced trade-off between safety and ruggedness against mains interruptions (AC on/off/on/off…). GTV Function: LibCoMa settings for the time-out of violations psys_GetProtectionViolation
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• Advised error handling: IF POR=1 or SUPR=1 during > 5s or NDF=1 during > 200ms or SUP=0 during > 40ms THEN “Safety-Shut-Down” : Set STB=0 Wait 1.2s set SFR ROMBK.STDBY=1 Wait > 1s and try to restart (POR=0) If the error persists, then switch off & remain in standby ELSE IF XPR=1 or DFL4..0 < 0FH THEN TV-Switch-On (fast)
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-82
Regular Check (1):
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– IC-temperature > 130º
– IC-temperature > 140º – 1.8VEXT or 3.3V too low
⇒ Reduce power (blink error LED & switch off non-vital functions, e.g. disable SSD??) ⇒ Immediate switch off ⇒ Do a “Reset-OSD” N1B/C?? : clear 1V8 + 3V3 flags
Reset OSD: • SW Reset-OSD consists of: – – – –
Mute sound, switch SSD=off Switch-off DINT=0 SW toggle bit SFR ROMBK.D6:= 0→1 If problem persists ⇒ “Safety-Shut-Down”
(⇒ resets OSD & all except 8051 core)
Temperature flags in EDET: When the IC gets very hot (>130º Celsius), the µC can receive an interrupt signal that allows the software to switch-off non-vital functions. If this is not enough too cool down the IC and the temperature rises above 140º Celsius, then SW should switch-off the TV immediately. Reset OSD:
does NOT reset the 8051 µC core
At each switch-on of 1.8VEXT and +5V, software can now reset its OSD part by writing SFR register ROMBK.D6 from “0” to “1” (other transitions have no effect). We advice to combine this reset with switching off the SSD and the digital video interface. GTV Function: Interrupt definition in fpmt_dcn.c file
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• Error flags in TCG-µC are handled on interrupt basis (EDET)
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-83
Regular Check (2):
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Soft-mute audio SW remove OSD (dynamic animation: close the curtains) SW set STB=0 (triggers HOUT slow stop) SW read DFL4..0 & wait until < 02H?? (Hdeflection ready with slow stop process) Disable supply for FBT/LOT Temp. for N1C??: disable EDET SW set µC SFR ROMBK.STANDBY=1 (DecDig falls low) SW disable WatchDog, set Keyboard_wake_up…. SW set µC-IDLE mode (Timers & RCP remain active) – Micro will stand-still until an interrupt wakes the 8051 – Upon RCP interrupt: temporary in STANDBY, then return to IDLE mode
• Upon wake-up: – re-enable WatchDog, Keyboard, SFR ROMBK.STANDBY=0 – Temp. for N1C??: re-enable EDET & discard one false EDET-interrupt – TV-Switch-On
GTV Function: fpmt_SetPowerState
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• • • • • • • • •
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-84
DSU/MSU: TV-Sleep
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• IC-production stores a nominal cap-bank center-value in FLASH = FLASH-value
(using typical components, to annihilate IC production tolerances)
• Registers involved to control the cap-bank: – µC-SFR register: • P3DCXOCTRL.D6..D0 • P3DCXOCTRL.CAPMUX
(POR value = factory-FLASH-value ) (1= from SSDNICAM , 0= from SFR)
– SSDNICAM register: (non-SSD versions: set CAPMUX=0) • DCXO_CTRL_REG.NICPLCENTER (POR value = 3FH,7bit = 3F8H,10bit) • DCXO_CTRL_REG.NICPLPLIM (Frequency-range limiting) • DCXO_CTRL_REG.NICPLSCALE (Phase adaption speed)
GTV Function: psys_SetCrystalAlignment psys_GetCrystalOptimumViaNicam psys_GetCrystalOptimumViaColour
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• Trimming of integrated Xtal-clock-capacitors enhances total accuracy
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-85
DCXO timing & tuning (1):
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– µC-SFR register: • I2S.I2S_CLK1..CLK0 • I2S.EN_I2SCLK
(I2S bit clock, 00 = 256 x FS) (1 = I2S bit clock out, 0 = GPIO)
• Remarks: 256 x FS = 8.192 MHz = DCXO output frequency / 3 • I2S output clock can be made visible on GPIO pin 103 (P0.3/I2SCLK) • I2S output is only available in full stereo or AV stereo version •
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• Other µC Registers, used for tuning:
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-86
DCXO timing & tuning (2):
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– SSDDEMDEC register: • DDEP_CONTROL_REG.DPMODE (DEMDEC easy programming mode) • DDEP_CONTROL_REG.STDSEL (Standard selection) • DDEP_CONTROL_REG.REST (Reset DEMDEC) – SSDINFO register: • INF_NIC_STA_REG.VSP (Identification of NICAM sound) • INF_NIC_STA_REG.CO_LOCKED (NICAM frame and CO sync.) – SSDDEV register: • INF_DEV_STA_REG.VDSP_C
(NICAM decoder VDSP flag)
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• Other SSD Registers, used for NICAM tuning:
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-87
DCXO timing & tuning (3):
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– COSMICSYNC1 register (0x3E) : • SYNCHRONISATION1.red
(bit 6, REFOK bit disabled)
• During DCXO tuning, the internal 24.576Mhz reference VCO of the VSP could loose its lock to the DCXO. No-lock sets bit SUPOK=0 and HOUT will switch-off. This is prevented by setting bit red=1 during DCXO tuning
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• Other VSP Registers involved:
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-88
DCXO timing & tuning (4):
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A set-maker can find his own Application-OPTIMUM via 3 methods : (No alignment –only transfer of FLASH VALUE-- gives same accuracy as UOC-II)
1. Per IC you can read back it’s FLASH-value via P3DCXOCTRL.D6..D0, directly after µC-POR 2. For a specific IC+application, find it’s best ABSOLUTE-value: -A- NICAM test signal ⇒ read back from NICPLCENTER (CAPMUX=1) -B- SW controls cap-bank ⇒ measure frequency e.g. via I2S clock output -C- Colour test signal, determine middle of colour locking range ⇒ read back from P3DCXOCTRL.D6..D0 (CAPMUX=0) 3. OFFSET-value = ABSOLUTE-value – FLASH-value Store the OFFSET-value in Eeprom (Nvmemory) 4. Combine this OFFSET-value per IC with it’s own FLASH-value
•
Remark: when each individual TV is aligned, you can also store the ABSOLUTE-value of it’s IC in Eeprom
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•
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-89
Optimal value for DCXO cap-bank:
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Apply NICAM signal (e.g. B/G NICAM) with good reception quality –
• •
Set COSMICSYNC1 bit red=1 Load SSD with FLASH-value – – –
•
(=NICAM spec.)
(reg 0x3E.bit 6) (read-out via SFR, directly after POR)
Set DCXO_CTRL_REG.NICPLPLIM to 0x1FF Set DCXO_CTRL_REG.NICPLSCALE to 0x0 Set DCXO_CTRL_REG.NICPLCENTER to 0x0
Set-up the DEMDEC in the SSD – –
•
Use a NICAM generator with ≤ 1 ppm frequency tolerance
(511=max) (0=max range, scale 1.0)
(via DDEP_CONTROL_REG)
Set EPMODE (bits 1..0) to 0x01: Static Standard Selection mode Set STDSEL (bits 6..2) to 0x05: B/G NICAM
Re-start the DEMDEC to acquire NICAM (via DDEP_CONTROL_REG) –
Set REST (bit 7) in DDEP_CONTROL_REG to ‘1’
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•
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-90
-A- Find optimum: using NICAM (1)
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Wait until NICAM is detected, using status bits: –
• •
INF_NIC_STA_REG. VDSP or CO_LOCKED or INF_DEV_STA_REG. VDSP_C and the error-counter ERR_OUT has gone down to 0X0
Wait 100..500ms extra to make sure PLL is fully settled Read 7-bit ABSOLUTE-value from INF_NIC_ADD_REG.DCXOCAPS, (unsigned 7-bit integer, stable when only one LSb toggling)
• •
Save in Eeprom Set COSMICSYNC1 bit red=0
(reg 0x3E.bit 6)
Philips Semiconductors
•
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-91
-A- Find optimum: using NICAM (2)
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– –
• • • • •
(=8.192MHz)
Set I2S.I2S_CLK to “00” Set I2S.EN_I2SCLK to ‘1’
Set COSMICSYNC1 bit red=1 (reg 0x3E.bit 6) Start with FLASH-value (read-out via SFR, directly after POR) Use SW to modify this in P3DCXOCTRL.D6..D0 until I2S clock reads-out correct MHz Store this 7-bit ABSOLUTE-value in Eeprom Set COSMICSYNC1 bit red=0 (reg 0x3E.bit 6)
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Measure absolute frequency via I2S clock output: • Enable pin 103 (P0.3/I2SCLK) as I2S bit clock output @ 256 x FS
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-92
-B- Find optimum: using I2S
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Find the middle of the colour-locking range: • Start with FLASH-value • Select a very good CVBS signal e.g. with PAL colour • Set COSMICSYNC1 bit red=1 (reg 0x3E.bit 6) • SW modify DCXO tuning until colour is found • Make sure Cosmic is locked to that colour • SW decrease DCXO tuning until colour is just lost ⇒ LOW LIMIT • SW increase DCXO tuning until colour is just lost ⇒ HIGHLIMIT • Optimal 7-bit value: (HIGHLIMIT + LOW LIMIT)/2 = ABSOLUTE-value • Save this in Eeprom • Set COSMICSYNC1 bit red=0 (reg 0x3E.bit 6)
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-93
-C- Find optimum: using colour-lock
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• SW initialise cap-bank settings: Non-SSD versions: set CAPMUX=0 & don’t write DCXO_CTRL_REG Set COSMICSYNC1 bit red=1 (reg 0x3E.bit 6) IF stored in Eeprom THEN fetch & copy into SSDNICAM DCXO_CTRL_REG & in P3DCXOCTRL.D6..D0 ELSE SW fetch 7-bit FLASH-value from P3DCXOCTRL.D6..D0, convert into 10-bit data & write to DCXO_CTRL_REG. NICPLCENTER Set COSMICSYNC1 bit red=0 (reg 0x3E.bit 6)
• N1B: Note: non-SSD version is not possible for N1B !!! • N1C: cap-bank is controlled by SFR P3DCXOCTRL.CAPMUX, from – CAPMUX=1 : SSDNICAM DCXO_CTRL_REG register (during NICAM) – CAPMUX=0 : SFR P3DCXOCTRL.D6..D0 (in non-SSD version mono/AVstereo)
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• N1B/C: During µC-POR & SLEEP modes, DCXO is HW-initialised to 7FH
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-94
Load DCXO cap-bank:
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2
1
3
4
POR I2C
STB Hout
Sl.Start
Sl.Start
Sl.Start
When POR=1, read till POR=0, write all I2C registers with STB=0. Then set STB=1 POR is reset to 0, at the first I2C status register-read after 3.3 Volt supply > 2.50 Volt
1 When POR = 1, software must read till POR = 0. Then all I2C registers must be written with STB = 0 Pending on the power supply: 5 V from main supply: check SUP = 1 5 V from FBT: Low Voltage Start-up, no extra check needed Then write STB = 1 2 When the power drops shortly (spike )below 2.50 V, POR is set to 1 and latched. H-out is immediately switched off. When the software detects POR = 1, the start-up procedure as in 1 must be repeated 3 When the power drops below 2.50 for a longer time, Hout is immediately stopped and the device is put in reset condition 4 Once the voltage rises above 2.50 V again, the start-up procedure as in 1 must be followed The presence of the 3.3 Volt is basic for reliable working of the µprocessor part and the digital part (I2C registers and Hout drive circuit). Checking the 3.3 V regularly by reading POR and taking appropriate action when POR = 1 has absolute priority over all other matters. The µprocessor will not work when 3.3V is too low (< ~1.9V). GTV Function: LibCoMa settings for the time-out of violations psys_GetProtectionViolation
Philips Semiconductors
3.3 2.50
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-95
Protection: +3.3V supply
RESTRICTED, contains NDA items
2
3
4
5
6
SUP
+3V3 stays intact
STB Hout
Sl.Start
Sl.Stop
Automatic
Automatic
Sl.Start
Sl.Start
RGB Pin 17 PHI-2 Pin 32 EHTO
Sl.Stop
Sl.Start
Disch.
Sl.Stop
Disch.
4.1V
3.9V
XPR Reset to 0, first I2C read after pin 32 < 3.9 V
We assume the 3.3 Volt is OK. Note that the 4.0 level of the + 5 V supply has in reality a hysteresis of about 0.2 Volt (4.1 V SUP → 1, 3.9 V SUP → 0) 1 Check SUP = 1. Write STB = 1. Then Hout will begin via Slow Start. 2 When 5 V supply drops below 3.9 V, Hout will be stopped according the Slow Stop procedure. The RGB outputs are immediately blanked. 3 When the supply rises again above 4.1 V, Hout will automatically start again via Slow Start 4 The Flash protection is activated when the voltage at pin 17 is kept ≥ 4.1V longer than 1 µs. Hout is immediately stopped to protect the line transistor and RGB outputs are blanked. When pin 17 drops again < 6 Volts, Hout is automatically started via Slow Start. 5 The Overvoltage protection is activated when the voltage at pin 32 is kept above 3.9 V longer than 1 µs. XPR is set to 1, Hout is switched off according the Slow Stop procedure, RGB outputs discharge the EHT and the IC is set in Stand-by. When XPR = 1, software must read till XPR = 0, then write STB = 0 followed by STB = 1 6 Writing STB = 0, Hout Slow-Stops and RGB outputs discharge the EHT. GTV Function: STB: psys_SetTVProcessorStandby SUP: psys_GetTVProcessorPowerSupply XPR: psys_GetXrayProtection
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-96
1
5 4.0
(=DSU)
Philips Semiconductors
Protection: +5V from main supply
RESTRICTED, contains NDA items
Protection: +5V from FBT 2
3
4
5
SUP
Handling differs from previous slide !!
STB Hout
LSU
RGB Pin 17 PHI-2 Pin 32 EHTO XPR
Slow St.
LSU
LSU
Slow St.
LSU
Disch.
Slow St.
Disch.
4.1V
3.9V
Reset to 0, first I2C read after pin 32 < 3.9 V
• With LSU/MSU, SW action is needed to recover from dip / flash / Xray-protection
1 When the 3.3 V is ok and all I2C registers are written, STB can be set to 1. Hout performs a Low voltage Start-up via Slow Start The 5 Volt from FBT will rise. At 4.1 V (0.2 V hysteresis.) all other video processor blocks are released (including RGB outputs) 2 When the 5 V drops below 3.9 V (e.g. due to overload), H-out will stop according the Slow Stop procedure and the RGB outputs are immediately blanked. Because the Hout is stopped, the 5 V will not return any more. The µprocessor can check this by monitoring the SUP bit. A new Low Voltage Start-up must be initiated by writing STB = 0 followed by STB = 1. 3 Activating the Flash protection stops immediately Hout and blanks the RGB outputs. Also now the 5 V doesn’t return because Hout is stopped. A new Low Voltage Start-up must be initiated by toggling STB (see 2) 4 Activating Overvoltage protection stops Hout via Slow Stop, RGB outputs discharge the EHT and the IC is set in Stand-by. The µprocessor must check XPR and SUP and when XPR = 0 initiate a new Low Voltage Start-up by toggling STB. 5 Setting STB = 0 switches off Hout via Slow Stop and the RGB outputs discharge the EHT.
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-97
1
Philips Semiconductors
5 4.0
(=LSU/MSU)
RESTRICTED, contains NDA items
Power
Sync & Geometry
VIF & SIF
Colour
YUV
Micro
Stereo
RGB
In/Out
Philips Semiconductors
Mono
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-98
H/V sync & geometry:
RESTRICTED, contains NDA items
• Low Voltage Start-up facility (LVS) • Intelligent Vertical count-down circuit • Vertical driver optimized for DC output stages • H & V geometry including Parallelogram and Bow correction for large screen picture tubes • H & V Zoom function for 16:9 + (digital) Panorama • Slow Start / Stop procedure
The low voltage start-up (LVS) makes it possible to initialise the horizontal drive using only 3.3 V. It is possible to supply the +5 Volt from scan rectification of the FBT/LOT. Parallelogram and Bow correction are available for applications with real flat picture tubes. When vertical is zoomed out more than 105%, the extra over-scan is blanked to prevent picture tube damage.
Philips Semiconductors
• Alignment free H-oscillator, 2 control loops
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-99
H,V-sync & Geo Processing:
Switch On
64µs
HDRIVE 28,8µs
28,8µs
28,8µs
0 to 12% in 57ms
12 to 73% in 73ms
55%
45%
35,2µs
28,8µs
73 to 100% in 1045ms
With bit SDC the duty cycle can be changed from 55:45 to 60:40 when STB=0
time TON %
Switch Off 25% 0 24µs
24µs
1mA picture tube discharge,
8µs
1175ms
24µs
during 38ms 43ms
During slow start, the off-time of HOUT is kept fixed at 28.8 µs. The on-time increases from 0 to 35.2 µs (for 55:45 duty cycle). In this way, overstress of the line transistor is prevented and the EHT builds up gradually. The three speedvariations even enable the use of very large picture tubes with a “DAF” gun. During switch-off, the Hout frequency is doubled immediately and the duty cycle is set to 25% fixed, during 43 ms. The RGB outputs are driven high to get a controlled discharge of the picture tube with 1 mA during 38 ms. This will decrease the EHT to about half the nominal value (= safety requirement). For this feature, the RGB amplifier must be able to return a 1mA “Iblack” measurement current (like TDA6108A). When bit OSO is set the white spot/flash during switch off will be written in overscan and thus will not be visible on the screen. Careful application must guarantee that the vertical deflection stays operational until the end of the discharge period. With bit SDC the duty cycle can be changed from 55:45 to 60:40 when STB=0. GTV Function: STB: psys_SetTVProcessorStandby OSO: psys_SetVerticalScanAtSwitchOff SDC: psys_SetDutyCycleHorizontalDrive
Philips Semiconductors
Slow start / quick stop:
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17
Flash detection
Video sources 74 YOUT
DC clamp
73 YSYNC
SN2..0
SYM
Noise detector Hsync separator 50% 30%
SSL Selected Video
Data sync sep.
To TXT/CC decoding
CSO HTXT
Switch
SD2..0,CMSS
XDT XPR
SID VID
Flash Prot.
FXTAL Calibrator
FOA/B
Safety DFL
>4V
HBL,WBF/R Blanking 67
Timing VCO :1600
PHI1
Clk 3V3 5V Dig BG
18
HOSD
POC
PHI2
Slow Start & Stop
HP2 STM Line oscillator phi-1 loop Coincidence SL detector V IVW/F, OSD FSI Vsync separator Auto70/35 70%
FSL
Vertical Divider FORF/S, DL, NCIN,OSVE
HSH, HP, STB,SDC LineHB,SDC Phase “soft” lock phi-2 loop SandCastle VA,VSH,SC,VLIN,VX, Generator VSC,SBL,VSD Vertical Geometry Vertical Vertical Geometry Sawtooth HCO >3.9V East-West EW,PW, XPR Geometry L/UCP,TC
Horizontal drive
26
66 FlybackIN / SandCastleOUT 22 23 32
Vertical drive EHT/XrayProt
21 EW drive (AVL)
27
New: Better sync performance, due to clamp right before sync part. The horizontal oscillator (PHI-1) uses the X-tal reference frequency to calibrate it's free running frequency (roughly 25MHz). It has several time constants and gating modes, including a “very slow” mode (stable OSD) when SID does not identify valid CVBS. By forcing phi-2 pin 17 above 4.0Volt, the HOUT is immediately stopped. Using an external detection circuit this can be used for flash protection. When the voltage drops < 4.0 volt, HOUT starts via the slow start procedure. Pin 36 can be forced >3.9V to implement an over-voltage detector (status bit XPR). HOUT will be slow-stopped. Software has to toggle STB=0 and back to STB=1 before HOUT starts again (safety). For non-EW versions, pin 21 connects the AVL capacitor (bit AVLE=1). The R and C at pins 26 and 27 must have good temperature stability To enable TXT/CC decoding from YPrPb input, set bit HTXT=1. In all other cases the data comes via the CVBS-switch and HTXT should be set 0 GTV Function: SID: ptun_GetIdents, ptun_GetVideoIdent XPR: psys_GetXrayProtection AVLE: psnd_SetAVLEnabledOnEastWestOutputPin
Philips Semiconductors
Sync and Geometry:
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RESTRICTED, contains NDA items
+ Max. +5V Horizontal drive (open drain output)
FlyBack In / Sandc. Out
5.3V 3V
Deflection Timer
FBT/LOT
Flyback capacitor Capacitive divider
+8V
Wrong H-timing = colour problems (loads Burst-Key)
66 24k
DFL4..0
+
67
Clipper
ϕ2 ϕ1
+
100..300µA
Current limiter
SandCastle
Active Pull down at start-up
5.3V = Burst-Key 3V = H-clamp 2.7V = DC detect 2V
= Vertical
• Switch-on protection (= 300mV below H-clamp level) takes care that HOUT never switches ON during an FBT-flyback
The PHI2-loop compensates for temperature effects of the switching of the deflection transistor (high voltage and large currents). The “SandCastle” pulse contains all synchronisation information: - the PHI-1 related chroma Burst-Key pulse - the PHI-2 feedback = H-flyback = Horizontal blanking pulse - the Vertical retrace = Vertical blanking pulse We have to avoid destructive switch-on of the line deflection transistor during a flyback period. A built-in protection will NOT switch the Horizontal drive “on” (= pin 66 goes low) when the H-flyback input has a DC level above 2.7V. When a capacitive divider is used to derive the Flyback information, an active pull-down will prevent H-flyback from accidentally floating too high. Hint: If you see SandCastle being pulled low, apparently the IC tries to (re)start. During a slow-stop(protection), you can also see the pulling-down. If you have colour detection problems, then check the timing of the H-flyback in the SandCastle pulse. If the Burst-Key pulse is distorted, then also the timing for the colour recognition may be affected.
Philips Semiconductors
SandCastle pulse:
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Sync Gating
No Noise
RF
Slow
Full
VCR
Fast
Clever
00
Slow
Full
01 10
Fast
Full
11
Auto
RF, DVD
VCR only Sync loss
Fast
FOA/B
17
None
Fast Search Very Slow
No signal
Very Slow
Hsync separator
VID 1 0 SL
OSD-mode
VID Remark 0 PHI1 coupled to SID 1 PHI1 only controlled by FOA/B/POC
No Noise
1
PHI1
1 POC
:1600 SL STM
INA..D CVBSSW
SID
FXTAL
Coincidence detector
Noise detector
SID,SL= 0,0
• Use OSD-mode or POC=1 only when video-sync-performance is irrelevant
0
Calibrator VCO 1600xFH
Video Ident
Slicer CMSS
Switch Switch
Phi1mode
VDX VDXEN Coupling VIF-AGC-gating to Sync x 0 Yes, while INA..D = tuner 0 1 Yes, Sync is coupled to VIF signal 1 1 Not coupled, no sync gating
H+V sync
IF-AGC
CVBSINT Y/CVBSEXT
SD2..0
(and SW must detect SL=1 to exit from OSD mode)
• If you use FOA,B=0,1 (Slow mode) ⇒ SW must select FOA,B=0,0 when IVW=0 (otherwise catching may be slow)
Normal off air reception or cable: FOA,B = 0,0 (Auto) for RF or VCR, possible on all program numbers FOA,B = 1,1 (Fast) is optimised for VCR, but not suitable for RF FOA,B = 0,1 (Slow) is best for RF-only or DVD, but not suitable for VCR No RF signal conditions The “Very Slow” no-signal mode (controlled by SID,SL,VID=0,0,0) enhances the OSD stability (e.g. during search-tuning) SoftWare overrule: For extreme conditions, SW can force a slow “OSD-only” mode via FOA,B = 1,0 (e.g. when SL=0). Switching back to normal mode must be done by SW under the condition: SL=1 or an integration of SID over a longer period. POC=1 gives very stable OSD but also disables SL. It should only be used when video synchronisation is irrelative (e.g. welcome-screen). SID acts as PHI-1 helper when VID=0 and SD2,1,0=0,0,0 or selects the same source as INA..D. IF-AGC-gating: When PHI-1 sync is synchronous to the tuner signal, active gating can improve the signal stability. If a tuner CVBS signal goes via a “SCART-loop-through” (= external input), set VDX,VDXEN=0,1 to active IF-AGC-gating.
Philips Semiconductors
PHI-1 loop: VDX,VDXEN,INA..D
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SD2..0 CMSS Video input Remark 000 1 Selected by INA..D Main sync separator 001 0 CVBS1 (tuner, IF) Use separate, dedicated 010 0 CVBS2 sync separator. 011 0 Y/CVBS3 Source selection for SID is 100 0 Y/CVBS4 101 0 G2/Y/CVBS5 (pin 72) done by SD2..0. 110 0 G3/Y (pin 79) (In these positions CMSS=don’t care) 111 0 Spare
SID as PHI-helper
Switches PHI-1 slower when there is no signal
SD2..0=0,0,0 & CMSS=1
Couple SID to the main video & sync separator
Wait 10??ms VID=0 Coupled circuits
Allow some time to stabilise Then couple SID to PHI-1 time constant Gives better OSD stability during noise-only, prevents PHI-1 from staying FAST @ no sync
• When sync fails (SL=0) then PHI-1 will try to re-acquire in fast-mode • With VID=0, SID can automatically select slow-mode
(gives more steady OSD)
• SW can also force slow-mode: VID,FOA,FOB = 1,1,0
(but needs SW to return)
With CMSS=1, the SID detection bit uses the main sync separator, which is always coupled to the displayed picture (as selected by INA..D). When SID has to judge a signal from another, non-selected source, then bit CMSS=0 makes SID use another, independent sync separator circuit. GTV Function: CMSS: psys_SetVideoIdentSyncSelection FO: psys_SetPhiOneLoopTimeConstant VID: psys_SetVideoIdentificationActsOn FO: psys_SetPhiOneLoopTimeConstant SID: ptun_GetIdents, ptun_GetVideoIdent SL: ptun_GetSyncIdent VID: psys_SetVideoIdentificationActsOn POC: psys_SetSynchronisationEnable SD: psys_SetVideoIdentificationSource IN: psys_SetSourceSwitch VDX: psys_GetModeIFSyncInterface VDXEN: psys_SetEnableVDX
Philips Semiconductors
SID (1): as PHI-1 helper
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-104
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Switch SID as PHI-1 helper Stable OSD 1x per second yes
Check: Auto source switching Check: Auto de/mute SCART1 out During AV modes: Control recalibration of IF
Most of the time SID helps PHI-1 Once per second SID is used for other tasks Sample presence of sync on all sources Integrate the result over several samples When there is no sync on the Tuner signal, then mute the FE-A/V outputs on SCART1 Implement this as ONE process, to avoid unnecessary switching
Loop forever
• Software extends functionality of SID circuit by multiplexing tasks
Every time when the source selection for SID is modified, or when it’s sync separator (CMSS) is changing, please always allow some 10ms stabilisation time before reading back SID.
Philips Semiconductors
SID (2): for multi-purpose
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Check presence of sync, e.g. once every 2 seconds
?? ES7.2D During TVstandby SID can not yet be used for wake-up
Sample all sources VID=1 SL=0 ? yes
FOA,B= 0,1 slow OSD mode CMSS=0, SD2..0 > 0,0,0 Temporary: for SD2..0=001 (CVBS1) use LOCK instead of SID
Next SD2..0
Wait 10??ms Read SID=1 ?
no
All tested ? CMSS=1, SD2..0=000 Wait 10 ??ms
Temporarily break coupling between SID & PHI-1 no
If sync was already failing, then set PHI-1 slow during the sampling of SID Test all available sources (SD2..0 ≠ 0,0,0) SID to Front-End + CMSS=0 temporary gives false sync indication
Detection time of SID circuit + switch-over time Is sync available on that source ? Test all & do the switching after some integration Re-couple SID to PHI-1 Let it stabilise to avoid glitch
VID=0 Restore FOA,B
Put PHI-1 back to your own preference
Coupled circuits
• No need for sense-contacts & signal detectors, fully under SW control • For RGB(F) sources, check also IN2,IN3
If you want to “borrow” the SID bit for detecting sync on other input signals (non-selected), then you will have to stop using SID as PHI-1 helper. SW can quickly poll all available sources and then restore SID as PHI-1 helper. Advice: Integrate the read-outs of SID for each external source over several samples, e.g. continuously “1” during 1 second. This avoids too nervous switch-over when e.g. a plug is connected or a VCR starts to play. While you are polling other external sources, you can either: - force PHI-1 always slow during this polling period (= simple) - check the IF-lock bit IFPL & switch PHI-1 slow if it fails (= need SW) - only force PHI-1 slow when SL=0 before you started polling (=advised), and accept some OSD instability during a few ms.
Philips Semiconductors
SID (3): automatic source switching
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-106
RESTRICTED, contains NDA items
RESTRICTED, contains NDA items
AV1 CVBS-Status
to be used for loop-through” decoders/de-scramblers
• Make it a USER’s choice to select for AV1: SCART-AV1 choice [1] Tuner output + External input, correlation unknown [2] No Tuner output, only External input [3] Decoder ON = Tuner signal looped-through
V D X V D X E N Coupling V IF -A G C -gating to Sync x 0 Yes, while INA..D = tuner 0 1 Yes, Sync is coupled to VIF signal
Bits VDX,VDXEN=x,0
Remark Active IF gating only when Tuner is selected VDX,VDXEN=x,0 and No tuner output during External input VSW=1 during Ext. input (like Asia-Pacific: no cross-talk) VDX,VDXEN=0,1 Active IF gating even when AV1 input selected gives better tuner performance
• IF-gating makes LOCK more reliable • With [1] during external AV input the IF-PLL can loose lock too early at high modulation, result = re-calibration of IF-PLL with visible distortion • SW can improve this, during AV input: – Disable auto-recalibration via IFLF=1, couple SID to tuner (SD2..0=0,0,1 CMSS=0) – When SID also detects no tuner signal, then temporarily set IFLF=0 (= recalibrate)
When the De-Scrambler detects a signal that it can decode, it will activate the “CVBS-Status” line. Now SW should react by switching to AV1 external input. Front-End mode: While the tuner signal is selected (INA..D=0,0,0,0) the IF-gating is keyed by the sync circuitry, so SID is then freely available to do other functions. If the IF gets out-of-lock AND there is no sync, then the IF-PLL will be recalibrated (IFLF=0). In AV modes: (not Decoder-On) Now sync coupling is not possible (not synchronous to tuner signal), so then the SID circuit can be used to decide about recalibration. While IFLF=1 it will not recalibrate. Remark: In TV/VCR combi’s the Front-End can be kept active during TV-standby (STB=1) by maintaining the +5V power supplies. In this special case the SID detector is forced to Front-End (SD2..0=irrelevant, overruled by hardware), but SW needs to set CMSS=0 (= use dedicated sync separator). The SID detector can only work while +5V is available. GTV Function: IN: psys_SetSourceSwitch VDX: psys_GetModeIFSyncInterface VDXEN: psys_SetEnableVDX IFLF: psys_SetCalibrationIFPLLDemodulator
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-107
Tuner
IF
FE
Philips Semiconductors
• European SCART1 plug permanently outputs tuner signal,
SCART1 De-Scrambler
SID (4): IF gating & recalibration
SCART1 = always tuner audio & video output
Auto mute SCART1 out
If front-end is viewed: better use SL, otherwise: use SID independent
INA..D=0,0,0,0 ? no
SD2,1,0= 0,0,1 CMSS= 0 Wait
yes
SL=1 ?
10??
ms
IFLF= 0
no no
SID=1 ? yes
Mute SCART1 outputs
Temporary: use LOCK instead (see next slide)
yes
Demute SCART1 outputs
Restore IFLF Background process
Couple SID to front-end Use other, dedicated sync separator Allow time to stabilise Allow IF-recalibration if no sync
Mute audio and video
IFLF=1 prevents IF from recalibrating Loop Mute/Demute as a background process
• Use SID →temporay: LOCK to mute tuner output signal on SCART1 if no sync • When SD2..0=0,0,1 and IFLF=0 then SID=0 will recalibrate the IF
SL is a more reliable video signal indicator, but always coupled to PHI-1 (= selected/viewed video source). While watching a source OTHER than frontend, you can use SID because this has its own independent source selection (SD2..0) and sync separator (CMSS=0). Video mute: Do NOT mute the Front-End via VSW=1, as this will shut-down the whole IF section and tuner-AGC. Consequently SID will never detect sync anymore. -Front-End video output “IFVO” (pin 43,44) can be muted via IFO2..0. - Selected video output “SVO” can be muted via SVO1..0=1,0 (??=1,1). - CVBS-PIP video output can be muted via CS1A..D=0,0,0,0. GTV Function: IN: psys_SetSourceSwitch SL: ptun_GetSyncIdent SD: psys_SetVideoIdentificationSource CMSS: psys_SetVideoIdentSyncSelection IFLF: psys_SetCalibrationIFPLLDemodulator SID: ptun_GetIdents, ptun_GetVideoIdent
Philips Semiconductors
SID (5): SCART1 front-end mute
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-108
RESTRICTED, contains NDA items
LOCK detection:
• SID has a tiny problem while CMSS=0 (dedicated sync slicer) but only when: – A tuner signal without sync is received (Front-End no signal), gives high noise amplitude – AND an other source is viewed
• Unwanted effect: SID keeps telling there is sync, while there’s only noise • Temporary solution: use LOCK instead, but only in this case (FE while AV selected)
• Careful: also LOCK has its attention points: – When FE is viewed, LOCK is vertically gated = more reliable (black during VSYNC) = OK – When AV is viewed (Back-End synchronised to other source) & VIF input signals are modulated > 85% (white picture), then LOCK toggles between lock/no-lock, while there’s still signal
• Solution: read LOCK several times and integrate via SW – E.g read 4 times with > 20ms interval; then integrate: ≥1 out of 4 = OK
GTV Function: CMSS: psys_SetVideoIdentSyncSelection SID: ptun_GetIdents, ptun_GetVideoIdent
Philips Semiconductors
Temporary problem, will be solved by trimming the dedicated sync slicer (CMSS=0) in future silicon. (Normal sync slicer = OK)
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-109
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TEXT PHILIPS
TEXT PHILIPS PHILIPS
• HOSD connected to PHI-2 (HP2=1): (coupled to the display) Stable OSD with noise & VCR trick modes PHI-2 corrections (HP, HB, HSH) not active on OSD • HOSD connected to PHI-1 (HP2=0): (coupled to the incoming signal) PHI-2 corrections (HP, HB, HSH) also active on OSD Slightly less stable OSD with noise & VCR trick modes
Three horizontal geometry corrections are made in the PHI-2 loop: • Horizontal Parallelogram HP • Horizontal Bow HB • Horizontal Shift HSH When using the parallelogram and bow correction the horizontal reference of the OSD must be connected to the PHI-1 to obtain the same geometry correction for incoming signal and OSD (HP2 = 0). When these corrections are not needed, the setmaker is free in his choice Note when the horizontal reference is taken from the PHI-2, (HP2 = 0) the horizontal position of the OSD is not changed when shifting the video with HSH. GTV Function: HP2: psys_SetSyncForTextOSD HB: pimg_SetHorizontalBow (BOW) HSH: pimg_SetHorizontalShift (HS)
Philips Semiconductors
Horizontal reference OSD:
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Weak, noisy signal 70% 70% 60%
Strong signal
Large signal
35% 100% 100%
>350mV
Top TopSync Sync 175mV
• Slicing level depends on noise detector (Fixed 175mV under Top Sync for very large sync pulse amplitude)
• FSL=1 forces 60% (use for non-standard signals with distorted black level) • Similar bit for Horizontal: SSL (SSL=1: 30%, SSL=0: 50%)
The vertical synchronization automatically adapts its sync-slicing level to the signal conditions. For optimal performance, it slices: - at 60% for weak signals (> 24db, measured by the noise detector ). - at 35% for strong signals (or forced 60% when FSL=1). With negative modulation, the sync pulses have the largest amplitude of the IF signal. When there is noise, it is best to slice near the top of the pulse, at 60%. For strong signals (no noise) we slice at 35%. This improves behavior with signals that have compressed sync, only during vertical interval. In areas where this is not needed, the sync performance can be made more immune to disturbances by fixing the level to 60% via bit FSL=1 (e.g. coded signals with variable black level during vertical or some cheap DVD players). When the sync amplitude becomes extremely large (> 350mV), the slicing is done at a fixed level of 175mV below top sync (end of proportional AGC range) The horizontal sync separator slices at 50% or 30%(direction top sync), depending on the SSL bit. GTV Function: FSL: psys_SetVerticalSyncSlicingLevel SSL: psys_SetSlicingLevelSyncSeparator
Philips Semiconductors
Vertical Sync slicing:
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NCIN=1
IVW=0
NCIN=1
IVW=1
IVW=1
7 frames
Acquisition Mode
IVWF=1
15 frames 6 frames
Narrow Window 522..528 lines 622..628 lines
15 frames
Norm Window 525 ± 1 line 625 ± 1 line
Direct Sync
3 frames
Direct sync in window else sync at 528/628
3 frames
Exact counter sync
Vertical rolling
No vertical catching
Small vertical jump
No vertical catching
None
Effect of missing vertical sync pulse Effect of position change vertical sync pulse
• Divider system + DC vertical amplifier gives: - Fast settling (speed-up with NCIN=1 : keeps vertical forced into Acquisition Mode) - Minimal visibility of (short) sync interruption • Automatic Comb-filter = OFF in “Acquisition Mode”
In “Norm” window, the counter inserts after exactly 525/625 lines a vertical retrace pulse and checks whether there is a pulse from the vertical sync slicer. A missing pulse (temporary disturbance) will not be visible because it inserts a vertical retrace pulse, at the correct position. After 3 missing pulses of the vertical sync slicer it will go to “Narrow” window. A missing pulse will cause insertion of a vertical retrace pulse after 528/628 lines. Here a slight jump of three lines can be visible. After 3 more missing pulses the system goes into fast “Acquisition” mode using directly the output of the vertical sync separator to generate the vertical retrace pulse. This divider system assures fast settling and at the same time high immunity against intermitted disturbances (spike noise). Setting bit NCIN=1 will speed-up vertical catching even more, e.g. when switching channels: - Change channel or video input - Force NCIN=1 - When SL becomes 1, force NCIN=0 (after phi-1 is locked). Note that as long as NCIN=1, bit IVW will not indicate “vertical-in-lock”. Before the 50/60Hz indication bit FSI is really valid, bit IVW=1 should be checked to make sure the vertical synchronization is really locked. The result is: 50Hz, 60Hz or not-locked.
FSI=1 FSI=0
Philips Semiconductors
Vertical Divider:
NCIN=1
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-112
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BITS FORF/ FORS
NCIN SSL FOA..B
POC VID FSL OVSE HTXT MVK
FUNCTION FORced Field frequency
SETTING I / O MACRO FU REM 00: auto 60Hz, I Sync SC 01: forced 60Hz, 10: keep last, 11: auto 50Hz Force No CoINcedence for vertical 0: normal, I Sync SC For faster vertical 1: force search window divider catching Sync Slicing Level 0: 50% I Sync TK 1: 30% direction top sync Forced phi-1 time constant 00: Auto I Sync SC 01: Very slow mode 10: fast/slow+gating 11: fast Phi-One Control sync mode 1: loop switched off I Sync SC Video IDent mode 0: SID controls phi1 loop I Sync SC Improves OSD 1: no influence stability Forced vertical SLicing Level 0: auto, 1: fixed 60% I Sync TK Enable Vertical OverScan 1: enabled I Sync SC (RGB measurment lines) Href for TeleteXT from own 0: dedicated sync slicer I Sync SC 0= normal, 1= 1: from main sync circuit dedicated TXT sync slicer TXT/CC via YPRPB 1: active (anti) MacroVision Keying I Sync SC Active only during NORM mode
For enhanced stability of On Screen Display e.g. during search-tuning, the phi1 loop can automatically be switched slow by SID (=Signal-Ident = simple 16kHz detector). Set bit VID=1 to enable this. With POC=1, the phi-1 is set to free-run mode (X-tal locked). In this mode bit SL can not be used to detect line-sync-lock. GTV Function: NCIN: ptun_SetVerticalDividerMode SL: ptun_GetSyncIdent IVW: ptun_GetStandardVideo FOR: psys_SetForcedFieldFrequency SSL: psys_SetSlicingLevelSyncSeparator FO: psys_SetPhiOneLoopTimeConstant POC: psys_SetSynchronisationEnable VID: psys_SetVideoIdentificationActsOn FSL: psys_SetVerticalSyncSlicingLevel OVSE: HTXT: psys_SetCsoSourceForTxt MVK: psys_SetMacroVisionKeyingEnabled
Philips Semiconductors
Sync related bits (1):
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-113
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BITS FUNCTION
SETTING
I / O MACRO FU REM
SL IVW
Sync in Lock 1: phi1-loop locked In Vertical divider Window during 0: no standard 15 consecutive sync pulses 1: 525/625 lines IVWF IVW Fast during 7 pulses 1: valid V-sync
O
Sync
SC
O
Sync
SC
O
Sync
SC Faster than IVW
FSI
O
Sync
SC
I 0: 55:45 I 1: 60:40 000: < 18 dB O 001..110: 18 .. 43 dB 111: > 43 dB
Sync
SC
Sync
SC Change activated only while STB=0 SC
HP2
Field Synchronisation Indication 0: 50Hz 1: 60 Hz H-Phase ref. of OSD to phi-2 0: to phi-1
SDC
Set Duty Cycle of H-out
SN2..0 Signal-to-Noise ratio readout of selected source
BITS HB HP HSH WBF WBR
FUNCTION Horizontal Bow Horizontal Parallelogram Horizontal SHift Wide Blanking Front Wide Blanking Rear
STEPS 63 63 63 15 15
RANGE -1.. +1 us -0.75.. +0.75 us -2.. +2 us 3.5 .. 5.9 us 7.8 .. 10.2 us
Sync
MACRO Sync Sync Sync Sync Sync
FU AL AL AL SC SC
REM
For the “real-flat” picture tubes the IC offers controls for Horizontal-Bow and Parallelogram (HB and HP). These controls are internally made as dynamic offsets between phi-1 and phi-2 loops. Normally the On Screen Display is synchronized to the phi-2 loop (= most direct coupling for a fixed position on the screen), but when HB and HP are used, bit HP2=0 should be used to synchronize the OSD to the phi-1 loop. Otherwise the OSD will appear curved, while the video display is straight (bow & parallelogram compensated).
Philips Semiconductors
Sync related bits (2):
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-114
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BITS DL HCO
FUNCTION De-interLace Horizontal COmpensation EHT tracking mode Overscan Switch Off
OSO SBL VSD
VGM1..0
Service BLanking Vertical Scan Disable (set to mid position on screen for VG2 black current alignment, see HBC, WBC) Vertical Guard Mode
LED
LED switch output
AVG
Adjustment VG2 voltage
FBC
Fixed BeamCurrent switchoff
EVB
Extended Vertical Blanking
SETTING 1: de-interlace 1: off, only on vertical 0: both EW & vertical 1: switch off in vertical overscan 1: active 1: no vertical deflection
I/O I I
MACRO Geo Geo
FU REM SC SU
I
Geo
SU
I I
Geo Geo
AL AL
00: vertical guard 01: vg & LED output 10: switch output 11: input, via NDF bit 0: LED off, switch high 1: LED on, switch low 0: normal operation 1: enable measurement 0: Blanked RGB outputs 1: Fixed beam current 1: active
I
Geo
SC
I
Geo
SC
I
Geo
AL
I
Geo
SC
I
Geo
SC
To minimise visibility, the discharge of the picture tube during slow stop can be done in vertical overscan by setting bit OSO=1. To help Vg2 alignment, the vertical deflection can be disabled via VSD=1 (one horizontal line on the screen). With AVG=1 the beam current can be read out via HBC and WBC, to align the “VG2-voltage (see section “RGB processing”). This even makes automatic alignment of VG2 (“screen”) possible.
Philips Semiconductors
Geometry related bits (1):
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BITS EW PW
FUNCTION EW W idth EW Parabola/W idth
SC TC UCP LCP VA VS VSH VX VSC VL0..1
S-Correction EW Trapezium Correction EW Upper Corner Parabola EW Lower Corner Parabola Vertical Amplitude Vertical Slope Vertical SHift Vertical eXpand (zoom) Vertical Scroll Vertical Linearity
VLIN
Vertical Linearity
STEPS 63 63
RANGE 700-0 uA 0-440 uA
MACRO Geo Geo
FU AL AL
63 63 63 63 63 63 63 63 63 00 01 10 63
-10 .. 25 % 100 uA -55 .. 55 % -55 .. 55 % 80 .. 120 % -20..+20 % -5.. +5 % 75..138 % shift -18..19 % Full screen Lower vert lin Upper vert lin 85 .. 117 %
Geo Geo Geo Geo Geo Geo Geo Geo Geo Geo
AL AL AL AL AL AL AL UC AL AL
Geo
AL
REM middle top/bottom top-bottom
VL0/1=00
Component tolerances and DC offsets in the vertical circuit are compensated by the alignments: Vertical Slope (VS), SHift (VSH) and Scroll (VSC). Mechanical offset in a picture tube is only compensated when a DC-coupled vertical amplifier is used, like TDA8357/59.
Philips Semiconductors
Geometry related bits (2):
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-116
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4:3 tube, picture 16:9 full width Vertical Compress SubTitle
16:9 tube, picture 4:3 side bars
16:9 tube, picture 16:9 sub title in black bar
+ Vertical Scroll SubTitle
SubTitle
SubTitle SubTitle
Horizontal Expand
+ Vertical Zoom
SubTitle SubTitle
+ Vertical Slope : Move up bottom, top remains SubTitle
SubTitle SubTitle
Vertical Expand
SubTitle SubTitle
Vertical Slope : lift sub title
• + Digital zoom 3:4 ⇔ 16:9 and panorama mode (some types)
On a 4:3 picture tube the vertical zoom function can be used to compress a “full-screen” 16:9 picture back to normal aspect ratio. On a 16:9 picture tube, a 4:3 picture can be displayed with black, vertical side bars. To make the picture “fill” the screen again, we can use H + V expand. If sub titles needs to be lifted, the Vertical Slope (VS) or Scroll (VSC) can be used. VS will keep the top of the screen constant, but modify the aspect ratio. VSC will move the whole picture and keep aspect ratio constant. On a 16:9 tube, a 16:9 picture in “letter-box” format is normally expanded to fill the screen. In some area’s the black bars are used to transmit sub titles or online news flashes. In that case the Vertical Slope can be used to lift the lower black bar back on the screen. Some versions of TDA110xx have digital zoom: - linear compression = 4:3 on 16:9 tube with black side-bars, or - panorama = non-linear stretched left & right edges GTV Function: VS: pimg_SetVerticalSlope (VSL) VSC: pimg_SetVerticalScroll
Philips Semiconductors
Geometry Zoom:
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4:3 picture on 16:9 CRT
Width adjustment
Outside visible picture, in overscan WBF
WBR
Position of horizontal blanking adjusted separately LEFT: Wide-Blanking Front (bits WBF) RIGHT: Wide-Blanking Rear (bits WBR) On /off = bit HBL (Horizontal Blanking) Wider range = bit WBI (6.24µs shift to center, use for digital 4:3 compression on 16:9 CRT)
When a 4:3 picture is displayed on a 16:9 tube, the East/West modulation can be used to compress the picture to normal aspect ratio. But the edges of the video, that are normally in the overscan, will then become visible. This can be adjusted with Wide Blanking front and rear. In case the CVBS timing is not symmetrical, both Front and Rear edge blanking can be adapted individually. GTV Function: WBF: pimg_SetWideBlankingStart WBR: pimg_SetWideBlankingEnd HBL: pimg_GetWiderHorizontalBlanking WBI: psys_SetTimingWideBlanking
Philips Semiconductors
Wide blanking:
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-118
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Mono
Power
Sync & Geometry
VIF & SIF
Colour
YUV
Micro
Stereo
RGB
In/Out
Philips Semiconductors
Colour decoding:
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-119
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• PAL+NTSC or PAL+SECAM+NTSC Full Multi system, including Latin America
• Automatic-detecting colour search system, or software-forced system ≤ ES7.2D: Automatic Comb switching=OK, but manual toggling CFA can show visible vertical jump ⇒ hide this by switching during VBI interval. Will be solved in UOCIII-N2
??
• Integrated Base-band delay lines
• Automatic COMB filter for PAL-M/N/BG and NTSC-M – Enabled by CFA=0, permanently off when CFA=1 – Automatically switches off when: • No proper colour-system detected • No vertical in-lock (IVWF=0, or while NCIN=0)
Philips Semiconductors
Colour Decoder:
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Y/C, B&W or comb
CFA0
YD3..0
DTR 4H/2H
0..320 ns
Y
AutoComb Filter
FXTAL COMB
ACL
YCD
Direct Digital Synthesiser
Chroma detector
1bit
Burst detector ACC
RefO
H/2
Cbps
Auto System Manager
Digital Filter
0o 90o
C
Y/CVBS
FCO,CM2..0, PSNS,CHSE1..0
HUENTSC
PAL / NTSC
Σ∆
CD2..0
IDN/P/S
H/2
YINT
IDP
+/-
UINT
C
IDN CB
Filter tracking
Y/C mode
VINT 1H
IDS
H/2
SBO1..0 B-Y
SECAM CLO Cloche
R-Y
BPS 1H
VCO
15
The CVBS signal is split into: - luminance path “Y” where all chroma components are trapped - chroma path “C”, via a band pass filter (“Cloche” for SECAM) The Direct-Digital-Synthesiser locks to the incoming colour carrier, during the chroma burst. All trap and band pass frequencies are set relative to the DDS. Colour is detected by combining information of the 3 multipliers: - Presence of a chroma-burst will set IDN (Ident Ntsc) - A +/- 90° phase alternation each line (H/2) sets IDP (Ident Pal) - A SECAM-demodulated level alternation each line H/2 sets IDS(Ident Secam) For NTSC signals, the U+V baseband delay line can be bypassed or can be used as simple kind of comb filter. When the real comb filter is ON and NTSC is decoded, please set BPS=1 (=bypass) for optimal effect. The base-band delay between Y and U&V (e.g. caused by different groupdelay in SAW filter) is aligned by the luminance-delay bits YD3..0. The automatic comb-filter is disabled when: - there is no stable vertical in-lock condition (IVW=0) - there is no suitable colour system detected (CD2..0=0 or Secam/NTSC443) - software disables it via CFA0=1 (preferred during search-tuning & AutoStore)
Philips Semiconductors
Colour Decoder Circuit:
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-121
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Chroma signal Nominal burst level
Burst
Nominal carrier level
Too large colour carrier
Too small colour carrier
A video signal (CVBS) is fed through a chroma band pass filter, to separate the burst and colour carrier from the Black & White part. The Automatic Colour Control circuit measures the chroma amplitude during the burst-key pulse (generated by synchronization part). It then tries to make this amplitude equal to the nominal value. Since chroma amplitude and burst amplitude have a fixed relationship in the video standards, the colour carrier will be stabilized to its nominal value too. If an attenuation or amplification of the colour frequency (e.g. 4.43 MHz) has occurred in the transmission of the TV signal, the ACC will automatically compensate this. The original colour saturation level is reconstructed.
Philips Semiconductors
Colour Decoder: ACC
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Chroma signal Nominal burst level
Burst
Nominal burst, but wrong ratio chroma-to-burst
Nominal carrier level
Maximal carrier level
• Too high chroma carrier level = over saturation • ACL=1 reduces during scan, burst unaffected
When the ratio between burst amplitude and chroma level is wrong, severe over-saturation can occur. The Automatic Colour Limiter will reduce undesired over saturation, caused by too high chroma/burst-ratio. It reduces the too high chroma carrier level to a maximum allowed level. The ACL adapts the chroma gain only during scan, so that the burst amplitude remains unaffected (maintain good chroma sensitivity). Note: Please disable the ACL circuit during SECAM reception (FM-modulated chroma) by setting I2C-bus bit ACL=0. In most other cases the ACL can best be left “on” (ACL=1). GTV Function: ACL: pimg_SetAutomaticColourLimiting
Philips Semiconductors
Colour Decoder: ACL
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Chroma band-pass characteristic
+ SAW filter roll-off PC
CC
= A-symmetrical Ideal chroma spectrum Band-pass-filtered chroma chroma spectrum spectrum Setting bit CB=1 gives 10% shift: More symmetrical spectrum
When a SAW filter has too much roll-off for high chroma frequencies, this can be compensated by setting tool-kit bit CB=1 or CLO=1 for SECAM. This shifts only the chroma bandpass (not the calibration). Especially the FM-modulated SECAM colour system profits from CLO. Under weak-signal-conditions, the SECAM PLL demodulator can sometimes loose its lock to the chroma carrier. Then it will jump to “where the maximum energy is”. Result = colour streaks (typical red- & blue-ish “flameche”) after a bright vertical line on a noisy CVBS picture. With a more symmetrical spectrum, the chroma PLL will reduce visibility of the SECAM flameche. The AM-modulated PAL and NTSC chroma systems are less affected by SAW filter roll-off, but under specific field conditions the “tool-kit” bit CB can help to improve weak-signal ident-performance Use CB=1 or CLO=1 only if necessary because it does affect the chroma spectrum. GTV Function: CLO: psys_SetCentreFrequencyClocheFilter CB: pimg_SetChromaBpCentreFrequency
Philips Semiconductors
Chroma Roll-Off, bits CB or CLO:
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BITS
FUNCTION
SETTING
ACL
Automatic C olour Limiting
1: on
I / O MACRO I
ColDec
F U REM TK
PSNS
P al S ensitivity at N oisy S ignals
0: lower sensitivity
I
ColDec
T K For VCR (forced) & PAL-only Please combine with SN1,0 S C For NTSC if Combfilter= ON
BPS
B yP aS s base band delay line
1: bypassed
I
ColDec
DTR
D ouble chroma T R ap
0: single, 1: double
I
Filt/Sw
CB
C entre of chroma B andpass
1: 10% shifted
I
Filt/Sw
S C Suppress more, less bandwidth SC
CLO
CLO che centre frequency
1: shifted
I
Filt/Sw
S C SECAM “Bell” filter
00: -34dB 01: -37dB 10: -41dB 00: +4.0 01: +1.0 10: -1.0 11: -4.0kHz 001: 2.1V+subcarrier
I
Filt/Sw
SC
I
Filt/Sw
AL Compensate tolerance, 01 or 10 to be used as “neutral”
I
ColDec
S C See I/O switching
I
Filt/Sw
SC
CHSE1..0 C h roma ident Sensitivity for PAL and NTSC SBO1..0
S E C A M B -Y O ffset
CMB2..0 Multi-purpose CoM B pin function CFA C o m b Filter Action FCO
Forced Colour O n
0: 4H-PAL/2H-NTSC 1: off 1: no colour killing
I
ColDec
TK
COMB
C O M B filter active
0: Not active
O
ColDec
SC
YCD
Y/C D etector, higher chroma burst on ”C” than on “Y/CVBS”
0: CVBS detected 1: Y/C signal detected
O
ColDec
S C Works only once, directly after a source change
Pin 33 (RefIn/Out…) can have different functions, which can be selected by the bits CMB2..0. With FCO=1 the colour killing function can be disabled (only when one single colour system is forced). This enables colour under non- standard condition, e.g. trick play in TV-VCR combinations. A forced suppression of colour can be done by setting SATuration=0. E.g. while software tries to determine the colour standard by switching SAW filters.
Philips Semiconductors
Colour Decoder related bits:
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CM3/2 /1/0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Colour Mode selected PAL/NTSC/SECAM PAL/SECAM PAL NTSC SECAM PAL/NTSC PAL NTSC PAL/NTSC/SECAM PAL/NTSC PAL NTSC PAL/NTSC PAL/NTSC PAL NTSC
Auto Auto Auto Forced Forced Forced Auto Forced Forced Full Auto Auto Forced Forced Full Auto Auto Forced Forced
Freq. Fa Fa Fa Fa Fb Fb Fb Fa,b,c,d Fc Fc Fc Fb,c,d Fd Fd Fd
Software sel.
PAL-BG/I/DK NTSC-443 SECAM PAL-N Auto PAL-M Tri-norma
CD3/2 Colour Freq. MHz /1/0 Detection 0000 No system 0001 NTSC-443 Fa 4.433619 0010 PAL-BG/I/DK Fa 0011 “NTSC?” Fb 3.582056 0100 PAL-N Fb 0101 “NTSC?” Fc 3.575611 0110 PAL-M Fc 0111 NTSC-M Fd 3.579545 1000 “PAL?” Fd 1010 SECAM
NTSC-M
• For correct RGB-matrix during DVD/YUV input, SW should define: - when FSI=1 (60Hz) : CM3..0=1,1,1,1 & MAT=0 - when FSI=0 (50Hz) : MAT=1
Each colour system can be forced using the CM bits. For flexibility also three automatic modes are implemented: -1000 = Full (all systems at all chroma frequencies) - 0000 = PAL/NTSC/SECAM 4.43 MHz only (Europe) - 1100 = NTSC M, PAL M, PAL N (Tri-norma, LATAM) The CD info is derived from the information of the three different demodulators, plus the locked frequency of the digitally controlled chroma oscillator. Normally there is no coupling to the vertical frequency, so even “non-standard” (VCR) signals like e.g. “PAL-443 at 60Hz with DK-sound” can be recognised. Except “SECAM-60Hz” can not be decoded in AUTO-mode. Remark: PAL at frequency Fd (NTSC-M) is not possible when CM2..0=1000. We have blocked this position to improve robustness against false locking. Also NTSC ident is blocked for PAL-M/N frequencies.
Philips Semiconductors
Colour Mode bits:
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Subcarrier MHz
50Hz FSI=0
Fa
4.433619
PAL-443
Fb Fc Fd
3.582056 3.575611 3.579545 SECAM
PAL-N ? SECAM
60Hz FSI=1 NTSC-443 PAL-60 ? PAL-M NTSC-M (ME)SECAM-60
False 50 FSI=0
False 60 FSI=1
NTSC-50 ?
-
NTSC ? NTSC ? PAL ? -
NTSC ? NTSC ? PAL ? -
• Distorted signals may be mis-identified ( transcoding VCR, noisy RF… ) • Combine CD3..0 with FSI, IVW and decide by software • Changing CM3..0 is (internal) vertically synchronised (always wait until next Vertical Blanking Interval (= VBI-interrupt EBUSY), before it is effective)
• Auto-modes: each frequency-change takes 2xVBI time, before a colour system can be detected • Advised order for 3.5MHz standards: PAL-N→PAL-M→NTSC-M (Fb,c,d)
By using an intelligent software-forced colour-search procedure, a reliable colour detection can be achieved even under difficult circumstances. The algorithm can then be optimised, by intelligent combination of: - Vertical deflection (50Hz, 60Hz or not locked) - Sound decoding (M, BG, I or DK) - Selected SAW filter (M or BGIDK) GTV Function: fmst_SetColour / Sound / System fmst_GetColour / Sound / System fmst_GetDetectedColour / Sound / System fmst_IsColourNTSC / PAL / SECAM fmst_IsColour / Sound / SystemDetectionBusy SL: ptun_GetSyncIdent PSNS: CM: pimg_SetColourDecodingDirect FSI: psys_GetFieldFrequency
Philips Semiconductors
Handling non-standards:
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4.5 MHz narrow VIF+SIF filters
Set CM=(PAL-N),TriNorma
Reset: CM=PAL-N, wait 1xVBI then set CM=TriNorma 2 x 20ms per chroma frequency
Loop 3x
Select M-SAW
60Hz
Select BG-SAW
Wait 2xVBI Standard OK ? no
All 3 tested ?
Set CM=Auto at freq. Fa FSI=0 ?
Low sensitivity, wait 2xVBI no
Allow PAL-60 ?
“China”-option
PSNS=1, wait 1xVBI PAL detected ? NTSC detected
yes
PAL-60
yes
NTSC-443
yes
PAL-60 or NTSC-443 or SECAM-60
yes
PAL-M, PAL-N or NTSC-M Test FSI before switching SAW
yes = 50Hz
Select BG-SAW Set CM=Auto at freq. Fa Wait 2xVBI Standard OK ? Not found, try again
yes
PAL-443, SECAM-50 or NTSC-50
High sensitivity, wait 1xVBI Standard OK ? Not found, try again
• If not found, retry a few times
A full-multi-standard TV receiver has switchable SAW filters. Software should set the colour-detection mode CM3..0, dependent on the selected SAW filter. Pre-conditions: SL=1 (video present), PSNS=0 (no preference for PAL). We advice to test the small bandwidth “TriNorma” systems first, in the order Fb→Fc → Fd. To make sure the IC starts in the correct order, please set CM3..0=0110 (PAL-N). Wait for the next Vertical Blanking Interval (VBI or “Busy-interrupt”), since the CM bits are only clocked-through during VBI. Then set CM3..0=1100 (TriNorma) and allow 2 VBI periods: one for clocking-through the CM bits plus one for the IC to detect a colour system. If this did not yield a detection, then determine the vertical frequency from bit FSI. For 50Hz, set CM3..0=00xx to only test at frequency Fa (PAL-443, SECAM-50, NTSC-50). Wait only once 2xVBI, because the frequency Fa remains constant. PAL can be given higher priority via PSNS=1, since NTSC-50 is non-standard. Remark: Use PSNS=1 ONLY after channel switching & the signal is stable. For 60Hz, test PAL-60 only when you really want it, since this often causes false identification with NTSC-443 (e.g. played-back from noisy tape). SECAM-60 is deliberately tested after PAL & NTSC since this rarely occurs. Not found means you can retry a few times, but not indefinitely. Black&White transmissions without chroma-burst still exist. Therefore we advice to stop colour-search after a few seconds. Select M- or BG-SAW, dependent on the audio carrier. If that is not present, then take the M-SAW.
Philips Semiconductors
Off-air M/BG switching:
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Mono
Power
Sync & Geometry
VIF & SIF
Colour
YUV
Micro
Stereo
RGB
In/Out
Philips Semiconductors
YUV features & processing:
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• Full YUV-loop interface (alternatives: DVD,CVBS,RGB or Y/C) • Internal OSD insertion (not Saturation or Contrast controlled) • Double window implementation • Linear / non linear scaling for 16:9 sets • Tint (~hue) on UV signals
(including DVD)
• Peaking, Coring, Black \ Blue \ White-stretch, Transfer-Ratio and Scavem (also on TXT)
Philips Semiconductors
YUV processing:
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= located in digital die 74 75 76
Comb PAL SECAM
+4.5V
CMB0/1
CD2..0
Alternative function
HUENTSC
BKS,BSD, AAS,TFR WS Y
DINT
IE2, IE3
Dyn. Skin tone
YD
IN3
78 79 80 77
R / Pr G/Y B / Pb Fbl3
65
Svm
Scavem processing
Tint
TPAL TSECAM TNTSC
Scavem Delay TXT
UV offset
CM2..0
IN2
RGB-to-DVD Inverse PAL-Matrix
Delay
NTSC 33
YUV-to-DVD
R/C/Pr G/Vid/Y B/Pb Fbl2
U
BLS
G
+ V
HCT
R
B
RINT
PK, TINT, DSK SAT MUS,MAT COR TUV Halftone OUV, OFB, OSD BLOG,BLOR
Switch
Y PR PB
FXTAL
Peaking,coring
51 54 58 72 55 59 70
V
SYS
Switch
CVBS2 CVBS/Y3 CVBS/Y4 CVBS/Y5 C3 C4 C5
CVBS & Y/C Switch
Fa=4.433619 MHz Fb=3.582056 MHz Fc=3.575611 MHz Fd=3.579545 MHz
U
DVD-to-YUV
Scaling & Double Window
Calibrator
Chroma Oscillator
Y
INTF Sync
70 72 71 75
Bluestretch
YSync IN
Matrix
73
YUV2..0, YC, INTF, FIN, FINM, IE3/2
BINT CON
MMR: 87F7H
• During DVD/YUV input colour detection is impossible; SW must select the correct RGB-matrix (NTSC-matrix when FSI=1 (60Hz) : CM3..0=1,1,1,1 & MAT=0 or PAL-matrix when FSI=0 (50Hz) : MAT=1)
Colour decoding of PAL/SECAM/NTSC needs some processing time, that has to be compensated in the luminance path (fixed time). Further delay between Luma and Chroma is compensated by YD=Y-delay alignment. OSD amplitude is set independently of Contrast or Saturation by Memory Mapped Register 87F7H in the µProcessor part and by bit HCT. Half-tone insertion (box with reduced contrast of main picture) is possible. External RGB+F input (SCART) is converted to YUV, allowing Saturation control. Since RGB-to-YUV uses an inverse-PAL matrix, also YUV-to-RGB should be forced to PAL matrix (MAT=1), to get correct colours. - “YUV” mode is compatible with add-on feature IC’s, - “YPBPR“ mode allows direct connection of a DVD player. The AC-coupling to YSYNCIN via an external capacitor allows better clamping and enhances the sync performance. It also eliminates horizontal-picture-shift when switching between video sources. For full-screen-inserted RGBF input (without Sync-on-green), the sync normally comes via a CVBS input. Set SYS=1 only for this mode.
GINT
Ins RGB
Philips Semiconductors
Signal routing:
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-131
RESTRICTED, contains NDA items
FUNCTION SETTING I / O MACRO FU REM I Filt/Sw SC RPA1..0 Ratio Pre/Aftershoot of peaking 00: 1/1, 01: 1.5/1 in direction white 10: 2 I Filt/Sw SC RPO1..0 Ratio Pre/Overshoot of peaking 00: 1/1, 01: 1/1.3 in direction black 10: 1/1.7, 11: 1/0.7 I Filt/Sw SC COR1..0 CORing, active below this video 00: off, 01: 20 IRE level 10: 40 IRE, 11: 100 IRE I Filt/Sw SC CRA0 CoRing A?? on SVM 0: 8%, 1: 15% BITS
BITS
FUNCTION
PEAK5..0 PEAKing YD3..0
Y (Luminance) Delay
STEPS 63 15
RANGE MACRO FU REM -20 .. 75 % Filt/Sw UC Neutral = 0D H 0 .. 415 ns 0 .. 520 ns
PF1,0 Peaking Freq Delay Used for 190 ns NTSC-M/N, PAL-M/N 00 2.7 MHz 160 ns Alternative for 00 01 3.1 MHz 10
3.5 MHz
11
4.0 MHz
Filt/Sw SC
Fsc = 4.43MHz Fsc = 3.58MHz
REM 3.6 MHz Chroma
Set makers choice 143 ns PAL-BG, SECAM, NTSC-443 4.4 MHz Chroma 125 ns External RGB/DVD No Chroma encoding
GTV Function: YD: pimg_SetLuminanceDelayTime HCT: psys_SetHighContrastOSD SYS: psys_SetYUVSynchronisationInputMode FSI: psys_GetFieldFrequency CM: pimg_SetColourDecodingDirect MAT: pimg_SetColourMatrixAdaption
Philips Semiconductors
Peaking & coring:
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-132
RESTRICTED, contains NDA items
OSD
SMD1
Delay
YINT
ScaVeM processing
Delay SVM2..0
SVMA, SPR2..0
SMD0
CRA0
VMA1/0 Gain
2Vpp max. 65 VMOUT
Hor. position
SVM output
SFR:SCAVTXT
Positiondependent gain adapt left
10
50 IRE
Yin
100
right
• No VM for small signals (VM-coring area, defined by bit CRA0) • High VM-gain for grey signals up to 50IRE; less gain for larger signals • Selectable delay between VMOUT and RGBOUT
(max. Video: -210ns, OSD: -300ns)
• VM gain adapted to H-position on the screen (temp. simplified parabola, no SPR2/1/0) (edges of screen need more VM than centre)
• SVMA=1 : more low-frequency gain
(6dB extra at 1MHz)
Scan Velocity Modulation improves the horizontal spot quality of a picture tube, by temporary changing the scan speed of the electron beam. Near left&right edges we need more SVM than in the center, especially for real flat CRT tubes GTV Function: CRA0: pimg_SetCoringOnScavem SVMA: psys_SetScavemOutputSignal
Philips Semiconductors
Scan-velocity modulation (VM):
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-133
RESTRICTED, contains NDA items
Yout
50
20
S BK
=0
Stretch
BSD=1
BSD=0
10 0 -10 -20
10
20
Yin
• I2C bit BSD sets black stretch depth to -10 or -20 IRE • Black Stretch switched off when bit BKS=0
GTV Function: BSD: pimg_SetBlackStretchDepth BKS: pimg_SetBlackStretchMode
50 IRE (above 50 IRE no stretch)
Philips Semiconductors
Black Stretch (1):
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-134
RESTRICTED, contains NDA items
Required 10% active area to switch-off Black-Stretch 90% 10%
Test method : black pluge on a grey background
AA S= 1
Black stretch off AA S= 0
Measurement Window
active area
= • 1: Determine dynamic black-stretch-reference level (in window) • 2: In window, measure sum of area’s where video is below that reference • 3: If more than 10% area (relative to full screen) is below the reference, then switch black stretcher off (or 20% when AAS=1)
For best effect of the black-stretcher, the TV application has to be carefully optimised (Beam Current Limiting, stability of the CCC loop, no line sag). The easiest way to check the black stretcher, is with a gray background (below 50 IRE, otherwise no stretching at all). Then apply a black section, a bit less than 10% of the viewing area. If you increase the section above 10%, the black stretcher will switch off smoothly (no discontinuities). So when there is enough black in the video, stretching stops. GTV Function: AAS: pimg_SetBlackStretchArea
Philips Semiconductors
Black Stretch (2):
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-135
RESTRICTED, contains NDA items
max. 18% White Stretch
18%
10%
10 17 25 28 APL
Yout
12%
40
50%
8%
50
• GAM=0: White-Stretching dependent on average detector (= APL) Bits WS1/0 determine: - the Average Picture Level (APL) where the white stretching begins - maximum achievable stretch (at 50 IRE) • GAM=1: fixed non-linear luminance transfer Bits WS1/0 select one of 4 characteristics
GTV Function: GAM: pimg_SetGammaControl
(gamma)
Yin
100%
Philips Semiconductors
100%
=1,1 1,0 WS 0 =1, 1,0 WS ,1 =0 1,0 WS
White Stretch Gain increase
White Stretch / Gamma:
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-136
RESTRICTED, contains NDA items
Visible on a CRT: Unwanted white compression at high picture level
Reduce Brightness
10%
TFR=0
4
R TF
⇓
=1
2
TFR=1 TFR=0
0 20
APL
80
100 IRE
Less white compression, (some loss of dark details)
• Transfer Ratio = dynamic brightness reduction, changing linearly with the Average Picture Level (APL) • No video-dependent shift when bit TFR = 0 • Eco-Histogram = combined Black&White-Stretch plus Transfer-Ratio
A “histogram” function tries to maximise using all available shades of gray within the available contrast-space. By combining the features of UOCIII you can implement a similar behaviour: -Black-Stretch makes more contrast-space on the lower end: If the darkest part was not black yet, it will pull this towards black -TFR = auto-brightness: If the CRT produces much light output, the beam-current limiting will compress the brightest details. TFR=1 makes more contrast space for bright details, by reducing the brightness a little -White-Stretch (gamma): This will enhance details in the mid-gray values, but only if the average picture is not too bright GTV Function: TFR: psys_SetLuminanceDCTransferRatio
Philips Semiconductors
Transfer Ratio:
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-137
RESTRICTED, contains NDA items
RESTRICTED, contains NDA items
R,G,B gain
100
20 0
20
Yin
80 IRE
• Blue discolouration at high intensity = brighter impression
(at same energy)
• No effect on lower-intensity parts (e.g. skin tones) • Blue Stretch switched off when bit BLS=0 • NRR=1 : no RED reduction during Blue Stretch
(taste dependent)
Blue-Stretch gives a “brighter-than-bright” impression by making a blue discolouration for the brightest picture details. More light-output is not possible because of Beam-Current limiting. So Blue-Stretch enhances the lightimpression without needing more energy. GTV Function: BLS: pimg_SetBlueStretch NRR: psys_SetNoRedReduction
Philips Semiconductors
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-138
Blue Stretch:
Mono
Power
Sync & Geometry
VIF & SIF
Colour
YUV
Micro
Stereo
RGB
In/Out
The Cut-Off control circuit with “Continuous Cathode Calibration” stabilizes the picture tube alignment during age-ing of the TV set. Not only a White Point adjustment, but also a Black level offset adjustment is now provided. This enables independent colour temperature setting for Lowand High- light. With this new feature even (cheap) picture tubes with nonstandard gamma characteristics can be used. White Point registers: WPR, WPG & WPB for Red, Green & Blue. Black Level Offset registers: BLOG & BLOR = offsets on Green and Red (Blue instead of Red if OFB=1). The contrast of the OSD can be set via the RGBOSD control in a µProcessor MMR register. The Contrast setting has no effect on the OSD, but BeamCurrent limiter and PeakWhite limiter do (see next slide).
Philips Semiconductors
RGB back-end processing:
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-139
RESTRICTED, contains NDA items
• One-point offset compensation is sampled-analogue (should react fast & precise to EHT / VG2 variations)
• Gain-control needs stable application: digital implementation allows intelligent integration via software (wait till warm, skip exceptions)
• Long-term drift compensated, a little each time (SW can read back loop-parameters & store them as start values for next switch-on)
• Hide visibility of gain adaptation (e.g. SW adapts gain during channel-change) • Any Start-up behavior can be made via software (pre-compensation)
Philips Semiconductors
Digital black-current loop: Why?
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-140
RESTRICTED, contains NDA items
RESTRICTED, contains NDA items
1.2mA
ICATHODE
150µA
10µA
130V
VCATHODE
60V
• DC cut-off- & gain-control make a CRT-tube behave “ideal”
The R,G and B characteristics of a picture tube have a gamma shape. The DC offset (black, Cut-Off) is compensated, using measurement pulses (10µA because it is not possible to measure with zero current). This control loop has to react fast, because the Cut-Off depends on VG2, which is dependent on EHT-voltage, which can be influenced by BeamCurrent. A digital gain-loop annihilates differences, using a second calibration point (150..280µA).
Philips Semiconductors
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-141
CCC-loop:
UV-offset
BLOR,BLOG,O FB
Low Light Offset RGB
RBL
AKB,EGL,AVG CCC Measurement Pulse Generator
Blanking
0.8V RGBL
BINT
BOUT GOUT
GINT
ROUT
RINT
Beam Current Limiter Peak White Limiter
Drive level
GLOK, RG/GG/BG LPG
DACs VG2 Window
3x Counter
5=down
Load Preset Gain
PGR/G/B
Iblack
Σ
Sample & Hold
WBC,HBC 1mA Beam current Discharge
detector PTW 10µA
OSO,FBC
SLG1,0
190
CBS,PWL,SOC
220µA
DAC Reduce CON & BRI
White Point
CL3..0
150
BRI
WPR/G/B
280
BCL= Average BeamCurrent Limiter Info 83
Peak White
Leakage Compensator
• EGL=0 holds gain loop • LPG=1 allows pre-setting (& holds loop too)
A fast Peak White Limiter (PWL) and a slow Beam Current Limiter (BCL) can reduce contrast and brightness to avoid over-drive of the picture tube (prevent: geo-distortion, local doming, de-focusing). The Continuous Cathode Calibration loop (CCC, AKB= Auto Kine Bias) consists of a DC-offset correction (black current) and a gain correction loop. For good performance, the RGB amplifiers must be able to handle positive and negative leakage currents. This is included in all Philips Semiconductors RGB amplifiers with a current measurement output (e.g. TDA6107A/08A). The gain control loop annihilates gain differences between R,G and B channels (due to age-ing, component tolerances etc.) Before adapting the RGB drive, the IC will measure and compensate the leakage currents (normally 2..10µA). The IC can handle +/- 75µA. The black current input is also used to set 1 mA discharge current during controlled shut-down of HOUT (if bit OSO=1), and to measure the beam current during Vg2 alignment (VSD=1). During blanking (RBL=1) the outputs are driven 1.1V below black level. GTV Function: EGL: LPG: OSO: VSD: RBL:
pimg_SetEnableGainLoopCCC pimg_SetRGBGainPresetLoad psys_SetVerticalScanAtSwitchOff psys_SetVerticalScanDisable pimg_SetRGBBlanking
87 86 85 84
Philips Semiconductors
RGB output control:
OUV
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-142
RESTRICTED, contains NDA items
PTW = Picture Tube Warm detector
• During start-up: disable the gain loop, EGL=0 (For stable PTW-readout, the RED preset gain should be set approximately 3 steps higher than was previously read back in a warm set)
• Load preset gain into the counters by toggling LPG=0→1 • Set EGL=1 (enables measuring lines, counters are blocked while LPG=1) • Keep reading until PTW=1 : now the picture tube is warm, i.e. the RED gain-measuring line causes a current larger than the current selected (SLG1..0 :150, 190, 220 or 280µA)
• Set EGL back to 0 (makes PTW indication invalid) • After loading desired preset gains, toggle LPG=1→0
Before the cathodes of the CRT-picture tube are warm enough, it is not possible to display any picture/OSD. The heating-up takes several seconds and determines most of the “TV-cold-start-time”. Using the PTW bit, your software can read back exactly when the CRT can start to display = automatic adaptation of start-up time. GTV Function: PTW: psys_GetIndicationPictureTubeWarm EGL: pimg_SetEnableGainLoopCCC LPG: pimg_SetRGBGainPresetLoad
Philips Semiconductors
Using the PTW bit:
Mainstream Tv Solutions - 10-2003 – UOC- III “Hercules” presentation 2-143
RESTRICTED, contains NDA items
Start up CCC loop:
Set: gain current SLG to last value
Offset ∆ during startup (∆ =~3, on red) Keep LPG = 1 !!
Set: gain preset PGx=last value + ∆ Clock-in presets, toggle: LPG=0→1 Switch-on: STB=1 & wait 1.5s
Check for failures: SUP, NDF … Keep RBL=1 for black switch-on
Set: RGBL=0 , EGL=1 Start: Time-out
Give-up if it takes too long, >10s
Init: BCF_OK_Cntr=0 Sample BCF ~ once per frame
Wait 20ms (= 1x VBI) =10s
Time-out 140ºC (SFR FB ) DETector - 1.8V or 3.3VSTANDBY too low (SFR A1 ) CC data available I2C transmit/receive V-blanking period BUSY (config H/V via MMR 87FFH) 16-bit Timer 2 with 8-bit PRescaler UART transmit/receive RD(B)S data available INTerrupt 2
• 1V8EXT too high can be read via VSP bit SUPR Software can give each interrupt source its own priority level. Processes that require very accurate timing can be given higher priority. The Software Analogue to Digital converter (SAD) can be configured to trigger INT1, to bring the core out of Power Saving mode. This is useful to implement an analogue scanned local keyboard with wake-up. The Closed Captioning data acquisition is partly done in software. The acquisition of (faster) Teletext data is done by hardware. The I2C-bus hardware is designed for a “multi-master” environment. With software it is possible to implement I2C-bus master- and even slave-modes. Via the Display Busy interrupt it is possible to synchronize e.g. display updates to the vertical scan of the picture tube, avoiding transition effects. Timer2 is a 16-bit timer with 8-bit prescaler and auto-reload. With its very long time-span (8.192s) it is ideal for software clocks. Safety interrupt EDET signals conditions that can harm the silicon. Status can be read via bits: 1V8GUARD, 3V3GUARD, TEMP130 & TEMP140. Interrupt is cleared by writing bits to zero (=different from other interrupts). A voltage of > 2.1V at the 1.8V inputs drastically shortens lifetime. This error condition can be read from the VSP via I2C-bus bit SUPR.
H
H
Philips Semiconductors
• 12 Vectored Interrupts, 2 priority levels
Mainstream Tv Solutions - 10-2003 - Hercules presentation 3-6
80c51 Interrupts:
RESTRICTED, contains NDA items
(16-bit counter or 8 bit with automatic reload)
• Timer mode:
fXTAL= 24.576MHz
– Count rate = machine cycle = [2 x 6] / fXTAL = 0.4883µs
• Event Counter mode: – Count rate = 2 * machine cycle = 0.976µs
• Timer2 (16 bit) with (8 bit) Pre-scaler (has automatic reload) : – Interval = [TP2H * 256 + TP2L] * [TP2PR +1] * 0.4883us
• Timers remain active during STANDBY & IDLE mode
SFR registers, related to Timer 0 and 1 are: TCON 88H TMOD 89H mode selection, gating TL0 8AH value (R/W) of Timer 0 low byte TH0 8BH idem, high byte TL1 8CH idem, low byte of Timer 1 TH1 8DH idem, high byte Timer 2 has more controls: TP2CL 9CH current value of timer, low byte TP2CH 9DH idem, high byte TP2L 91H auto-reload value, low byte TP2H 92H idem, high byte TP2PR 93H 8-bit pre-scaler value TP2CRL 94H status register
Philips Semiconductors
• Timer0 & 1 are configurable as Timers or Event Counters
Mainstream Tv Solutions - 10-2003 - Hercules presentation 3-7
Timer/Counters:
RESTRICTED, contains NDA items
• Activate by setting bit WLE in Power Control SFR : PCON • Safe disable by loading the value 55H in WatchDog Key SFR WDTKEY • In some modes too early wake-up must be prevented. Advice: disable the Watchdog during – IDLE or POWERDOWN mode – ISP (otherwise: risk of incomplete programmed samples)
Philips Semiconductors
• Reset the micro-controller after reasonable time-out WatchDog interval = [256-WDT]*216*488.3ns (= 32ms .. 8.2s)
Mainstream Tv Solutions - 10-2003 - Hercules presentation 3-8
Watchdog Timer:
RESTRICTED, contains NDA items
(80c51 ‘MOV’ Instruction)
• 4 KBytes Auxiliary SRAM
(80c51 ‘MOVX’ Instruction)
• 10 KBytes of Display SRAM
(Using SFR TXT14,15)
• SRAM for 64 Dynamic Redefinable Chars (animation, morphing) • 16x12-Bit CLUT Memory
(mapped as registers)
Philips Semiconductors
• 256 Bytes Main SRAM
Mainstream Tv Solutions - 10-2003 - Hercules presentation 3-9
Embedded RAM Memories:
RESTRICTED, contains NDA items
128B RAM only Indirect addressing
128B SFR only Direct addressing
Special Function Registers = extension method for 80c51
80H
30..7FH
RAM
7FH
20..2FH
Bit-addressable space Register-Bank3
Lower 128 Byte RAM Direct & Indirect addressing 00H
18..1FH
R7 R6 R5 R4 R3 R2 R1 R0
Register-Bank select bits in PSW
10..17H Register-Bank2 08..0FH Register-Bank1
R-Bank
00..07H Register-Bank0
• Different addressing method for upper 128 Bytes accesses RAM or SFR
Philips Semiconductors
FFH
Mainstream Tv Solutions - 10-2003 - Hercules presentation 3-10
Internal RAM: “Idata”
The RAM between 30H and FFH is not allocated for any special area or functions . The Program Status Word is accessible as an SFR PSW , located at address D0H. Examples of addressing modes are:
Mnemonic
Instruction
Instruction bytes
Oscillator periods
Indirect : XRL A,@Ri MOV direct,@Ri MOV @Ri,#data
XOR indirect RAM to Accu Move indirect RAM to direct byte Move immediate data to indirect RAM
1 2 2
6 12 6
Direct : MOV direct,A ANL direct,#data MOV direct,direct
Move Accu to direct byte AND immediate data to direct byte Move direct byte to direct byte
2 3 3
6 12 12
RESTRICTED, contains NDA items
Auxiliary Xdata is accessed via 8051instruction “MOVX”
• Physical RAM shared for Teletext, Closed Caption & RDS/RBDS – Capture : store in RAM – Display : read & convert to RGB
• Auxiliary RAM (except Display RAM) is – Not initialised at Power-On-Reset – Maintained in Power Saving modes
Address FFFFH 9100H 90FFH 8800H 87FFH 87E0H
Area
Size
-
..64K
DRC’s
2.25K
Display Control
32B
871FH 8700H
CLUT
0.25K
84FFH 8000H
CC Data
1.25K
RD(B)S Data
1.25K
Display RAM
20K
74FFH 7000H 6FFFH 2000H 1FFFH 0000H
TXT/CC/RDS/RDBS
Auxilary RAM
All Xdata – except the Display-RAM – can be used to maintain data during standby-mode of the TV (even when a short reset occurs). Please note that this Xdata is NOT cleared, so software must do that after reset.
4/8K
Philips Semiconductors
• On-board “external” RAM, called
Mainstream Tv Solutions - 10-2003 - Hercules presentation 3-11
Auxiliary RAM: “Xdata”
RESTRICTED, contains NDA items
• Contents lost during Power Saving modes (SW use page-clearing) • Same physical RAM are is used for : RDS/RBDS when register TXT27.RDS_ON=1 or for CC when TXT21.CC=1, else for Teletext • Teletext page area = 10K
Philips Semiconductors
• At PowerOnReset automatically initialised to 20H (= “space” char.)
Mainstream Tv Solutions - 10-2003 - Hercules presentation 3-12
Display RAM:
RESTRICTED, contains NDA items
“busy clearing”
• SW can clear a section ⇒ set TXT9.CLEAR MEMORY=1, pointed by TXT15.BLOCK, TXT15.MICRO_BANK , then set TXT13.PAGE CLEARING=1 and HW does the clearing • Data Capture will clear a page when: - a NEW page header is acquired - the erase bit C4 is set
While the hardware is busy clearing a RAM-page, it should not be accessed. SW should wait until hardware resets bit “PageClearing-busy”.
Philips Semiconductors
• Auto-clear at POR ⇒ TXT13.PAGE CLEARING=1 signals:
Mainstream Tv Solutions - 10-2003 - Hercules presentation 3-13
Display RAM Page Clearing:
RESTRICTED, contains NDA items
(Flash module 1)
( + Test ROM + redundancy )
• 14K x 16 bits Character Pixel ROM plus 2K look-up tables
(Flash module 2)
( + redundancy )
• Programmable ROM: - industrially via Parallel programming - via serial ISP (In-System-Programming)
(14 pins needed) (High-speed I2C-bus)
Flash module 1 holds: - Program ROM = 6 large sectors of 128 pages of 256 bytes - Packet 26 ROM = 1 small sector of 16 pages of 256 bytes - Test ROM = 1 small sector Flash module 2 holds: - Character ROM = 1 large sector - Lookup tables for efficient storage of character sets
Philips Semiconductors
• 128 ( / 256) Kbytes Program ROM plus 4KByte of Packet X-26 ROM
Mainstream Tv Solutions - 10-2003 - Hercules presentation 3-14
Embedded Flash-ROM:
Check ROM size: 4 base sets and/or 4 twisted sets. No. of fonts??
For Parallel programming a page is accessed as 128 words of 16-bit. For ISP programming via I2C-bus as 256 words of 8-bit (= easier because I2Cbus is byte-oriented). The number of character fonts that can be stored in Character ROM, depends on the Font sizes used by the software. The 14K x 16 bit character Pixel ROM allows : - in 12x10 matrix (or 12x9) storage of ??? character fonts - in 12x16 matrix (or 12x13) storage of ??? characters. With DRCS the number of characters can be further extended, limited only by the available program ROM. Fore-ground and back-ground can both be selected independently from two palettes of 8 colours out of 4096 possible colours (4K).
RESTRICTED, contains NDA items
96K
128K
160K
192K
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
32K
64K
96K
128K
160K
Upper 32KB 8000H 7FFFH
ROMBK2/1/0
Common 32KB 0000H
• Extension above 64KB by ROM-bank switching (via SFR, supported by Keil C51 compiler)
ROMBK 000 001 010 011 100 101 110 111
0 to 32K Common Common Common Common Common Reserved Reserved Reserved
32K to 64K Bank0 Bank1 Bank2 Bank3 res. Bank4 res. Reserved Reserved Reserved
The ROM bank switching is supported by several commercial compilers. A future extension beyond 128 or 192K is possible. The SFR ROMBK is located at address FBH.
Mainstream Tv Solutions - 10-2003 - Hercules presentation 3-15
FFFFH
64K
Philips Semiconductors
Standard 80c51 = 64KB
Program-ROM bank switching:
RESTRICTED, contains NDA items
I2C-bus:
SDA
HW-I2C
WISP, WIC32
10E 10E
ISP FLASH
SSD
470E 470E
Other
I2C
slaves
• The HardWare I2C-bus (Master/Slave-Transmitter/Receiver) runs at – Normal/Fast mode @ 12kHz .. 384kHz – High speed mode @ 128kHz .. 2.084MHz
• I2C can be disconnected from outside-world. Internally it connects: – – – –
TextControlGraphics µ-processor TV processor Digital Sound processor ISP (In-circuit Serial Programming) of FLASH memory blocks
The duty cycle of the I2C-bus SCL clock output can be selected according “STANDARD” of “FAST” mode by bit F/S in SFR FSBIR. The maximum clock speed is set: - in F/S mode via SFR FSBIR - in Hs mode via SFR HSBIR GTV Function: ri2c_SetRuntimeSpeed
Mainstream Tv Solutions - 10-2003 - Hercules presentation 3-16
SCL
Philips Semiconductors
I2C interface
80c51
PC
TV chassis
Eeprom
470E 470E
TV processor
3k3
3k3
+3.3V
RESTRICTED, contains NDA items
Split I2C-bus: SCL SDA
HW-I2C
10E 10E
ISP FLASH
SSD
470E 470E
Other
I2C
slaves
– Keep this safety-bus very short – Factory alignment data can be copied from HW to SW-bus, via a “softwarebridge” (= µC acts as I2C-slave on HW-bus and as I2C-Master on SW-bus) – µC-HW can be given any I2C Slave-address (but only ONE)
• Do not connect HW-I2C-bus permanently to other I/O pins: (like SW-I C) 2
– No extra safety anymore (then better connect all to only HW-I2C-bus) – Reset-polarity of most I/O pins (=low) may block HW-I2C communication (exception: special pins ??98 & 99 are high during reset)
The I2C-bus lines SDA & SCL will normally be quite long in a TV chassis. Series resistors must be added to protect the connected IC’s against energy pick-up, during flash-over of the picture tube or static discharges. A split-bus with very short connection between µC and Eeprom minimizes the chance that alignment data is destroyed by high-energy spikes. GTV Function: LibCoMa switch RI2C_SPLIT_BUS ri2c_2ndBusAddresses
Mainstream Tv Solutions - 10-2003 - Hercules presentation 3-17
2
Philips Semiconductors
PC IC of alignment-data, interface put Eeprom on a “split-bus”, using software I2C (on any pair of free I/O pins)
80c51
• For max. safety
TV chassis
Eeprom
SW -I2C
TV processor
3k3
3k3
3k3
3k3
+3.3V
RESTRICTED, contains NDA items
• Disconnect external I2C-bus pins • Initialize TVP + SSD (via HW-I2C-bus peripheral) • Connect external I2C-bus pins • Enable Remote Control Processor (RCP) • Initialize other I2C-bus slave devices
The first action after RESET should always be the definition of I/O pins like Power-On/Off, Volume and Mute. The micro processor communicates with the TV processor part via a standard I2C-bus protocol (Slave WRITE address 8AH). To eliminate the risk that other I2C-bus devices can disturb the communication to the TV processor part, we advice to disconnect the external I2C-bus pins during each of these transmissions. As start-up code we advice to use the BOOT code, supplied by Philips Semiconductors. This will take care of all necessary initializations. Disconnect external I2C pins by setting TXT21.bit1=0 (SFR B5H).
Philips Semiconductors
• Initialize internal µP registers
Mainstream Tv Solutions - 10-2003 - Hercules presentation 3-18
I2C start-up procedure:
RESTRICTED, contains NDA items
• Why ISP via I2C-bus ? – ZERO additional costs in TV chassis – Easy interface to a Personal Computer, programming SW called “WISP”
• Several I2C-bus speed-modes: – Normal (< 100kHz, rugged communication protocol) – Fast (< 400kHz, careful with capacitive bus-load) – High-speed (up to 2 MHz, adapted I2C-protocol)
Reload value HSBIR 0 1 2 3 4 5 6 : 31
Mod_Clock 12.288MHz Not allowed 2.048MHz 1.365MHz 1.024MHz 819kHz 688kHz 585kHz : 128kHz
ISP programming: During production of a TV chassis, the whole Flash-ROM can be used for TVFactory-SW. When the final destination is known, ISP can re-program the ROM with the End-Customer-SW. This allows maximum flexibility. Although ISP-programming takes < 10 seconds, the process can be speed-up by programming the non-variable part (Char, Pk26) before the IC is soldered-in (e.g. as part of a quality-check). Later during TV production the remaining blocks can be programmed via ISP. Other programming methods: In our Philips IC-Factory we can use other fast programming techniques. These methods can not be used in the end-application (need access to many pins & special pulse-sequences + levels).
Div 3 6 9 12 15 18 21 : 96
Philips Semiconductors
– Allow very late (re-) programming during TV-production – Easy software upgrade, e.g. after-sales-service – For true EMC tests, trial-runs etc.
Existing silicon + SW: limited to 1.2MHz??
• Why ISP ?
Mainstream Tv Solutions - 10-2003 - Hercules presentation 3-19
In System Programming:
RESTRICTED, contains NDA items
WISP
3k3
3k3
FLASH ISP
I2C
Hs-I2C
SCL
interface
SDA
10E
10E
10E
10E
Programmer
Low IN,MAX = 0.8V High IN,MIN = 2.0V LowOUT,MAX = 0.4V HighOUT,MIN = VddE - 0.4V
TV chassis
• Philips-ISP-software “WISP” drives several PC-to-I2C-bus interfaces: – “Single-Master” or “TraCII”, via Centronics parallel port (Normal / Fast mode) – “TraCII-XL”, via rugged USB-port (Normal / FAST / High-speed mode)
• Attention points for Hs-I2C mode:
(MAX speed = 2.048MHz)
– Minimize capacitive bus-load & cross-talk in chassis layout – Avoid collision with non-Hs-slaves: use high series resistor & Programmer’s impedance-switch to overrule non-Hs-compliant devices
ISP can be done at any I2C-bus speed (Normal / Fast / Hs-mode). High-speed-mode ISP programming: The series resistors to non-Hs-I2C-mode-compliant slave devices can be chosen higher, just enough to receive I2C data from the bus-master. During Hs-mode the Programmer-interface can set extra low driving impedance (switch), so that even when a slave tries to pull-down SDA/SCL, it can not disturb the Hs-communication.
Philips Semiconductors
USB
Other slaves
Picasso / Hercules
PC
470E 470E
80c51
Max. 2.048MHz
220E
+3.3V Hs
220E
+3.3V
Mainstream Tv Solutions - 10-2003 - Hercules presentation 3-20
WISP-SW & I2C programmer:
RESTRICTED, contains NDA items
Release I2C-bus Shut down all functions Use “WISP”
Make sure I2C is not blocked Disable what you can, for minimal heat dissipation Philips provided SW tool
Open Flash-lock
error
Erase Flash
Erase one or more sectors at a time
Write Flash
Write pages of 256 bytes
Verify Flash
Read CRC checksum
OK
Power-On-Reset
Hard-reset to resume normal mode
• ISP can not read-back the ROM, just a CRC-checksum (“MISR”)
Always check the internal I2C-bus is coupled & not blocked, prior to opening the Flash-lock. While the flash-lock is open, the 8051 core is forced to execute “NOP” instructions (= SW effectively standing still) “MISR” = Multiple Input Selection Register, a sort of checksum calculation
Philips Semiconductors
ISP programming
Mainstream Tv Solutions - 10-2003 - Hercules presentation 3-21
In System Programming:
RESTRICTED, contains NDA items
or alternative
= 10001010B=8AH = 10001110B=8EH
• StereoSoundDecoder = 10110000B=B0H (alternative not yet implemented:10110010B=B2H
• Flash-ISPENABLED
(=during I2C-Write; 8BH during Read) (if pin SVM not used & pulled high) (B1H during I2C-Read) (configured via micro controller)
= 01010010B=52H
(53H during I2C-Read)
• Micro ControllerRESERVED = 01100110B=66H
(67H during I2C-Read)
– – – –
Reserved in Philips’ I2C address allocation Free programmable by SW in SFR S1CON. Hardware can only be given ONE slave address Used by “Work-Bench” I2C-bus software
Philips Semiconductors
• TV-Processor
Mainstream Tv Solutions - 10-2003 - Hercules presentation 3-22
I2C-addresses:
RESTRICTED, contains NDA items
80c51 CPU
RAM • Universal Asynchronous Timers+Counters Receiver / Transmitter controlled by SFR’s: PCON, S0CON, S0BUF
UART Mode 0 1 2 3
Characteristic Serial 8-bit (LSB first) in or out via RxD, TxD outputs the shift clock 10-bit transmitted by TxD or received by RxD: start-bit=0, 8 data-bits (LSB first), stop-bit=1 11-bit transmitted by TxD or received by RxD: start-bit=0, 8 data-bits (LSB first), a 9th data-bit, stop-bit=1 Same as Mode-2
SSD
TV
UART I/O I2C SFR extensions TPWM
D/A
ADC
Baud rate = 1/6 of µC clock (12.288MHz) Timer1 overflow rate 1/32 or 1/64 of µC clock Timer1 overflow rate
• Mode 2+3 suitable for multi-processor communications: 9th data-bit can generate an interrupt
Mainstream Tv Solutions - 10-2003 - Hercules presentation 3-23
ROM
Philips Semiconductors
TXD RXD
Full duplex UART:
RESTRICTED, contains NDA items
• RCP = intelligent hardware filter to eliminate false bits, Software handles the RC protocol • Most RC protocols use “pulse-distance” modulation with a fixed “mark-to-space” ratio for “1” and “0” • Most protocols have a special start-bit timing: - RC-5 use bi-phase modulation, no real start-bit - RC-6 is 2x faster than RC-5, with start-bit
UOC-III has special low-power circuitry to achieve a low-power sleep-mode. To limit unnecessary wake-up’s on false infra-red RC-pulses, the RCP acts as a hardware filter. All infra-red RC-pulses are blocked until the first GOOD pulse (bit) is measured. Bit-decoding is done by software and the filters are programmable over a wide range. Therefore this RCP is compliant with all known commercial infra-red RC-protocols. GTV Function: rbsc_GetRemoteKey LibCoMa settings for RC5 and NEC protocol. Also any other High/Low time modulated protocol can be configured using LibCoMa (RBSC_REMOTECONTROL_RCP_XXX)
Philips Semiconductors
• RC-Processor = hardware to reduce the number of wake-up’s for the 80C51 core (from sleep mode)
Mainstream Tv Solutions - 10-2003 - Hercules presentation 3-24
Remote Control Processor (RCP):
RESTRICTED, contains NDA items
1
1
0
0
0
0
0
1
1
0
1
0
1 = LOW period timer A = HIGH period timer B 14 periods of 2tp = 14x2x889µs = 24.89ms,
Minimal Data-clean 3tp = 1.5 x bittime
C0
C1
C2
C3
C4
6 Control code bits
C5
S0
S1
S2
S3
5 System address bits
S4
Togglebit=1/0
Not-enlargedbit=1/0
Startbit=1
Interrupt
Command repetition = 64x2tp= 113.78ms
Japan code (at INT pin) : Start-bit 8tp
4tp
0 tp tp tp 3tp
1
0
0
1
1
0
0
1
0
0
Philips Semiconductors
1
Mainstream Tv Solutions - 10-2003 - Hercules presentation 3-25
RC5 bi-phase (at INT pin) :
Example: command 53DEC in system 0
RESTRICTED, contains NDA items
INT
A
B
Phase 1: IF INT goes high again before Cntr has reached AL THEN the LOW period is too short => exit ELSE count µC clocks in Cntr until it reaches AL, then reset Cntr Phase 2: IF INT does NOT go high before Cntr reaches AH THEN the LOW period is too long => exit ELSE copy Cntr value into result register RA and reset Cntr Phase 3: IF INT goes low again before Cntr has reached BL THEN the HIGH period is too short => exit ELSE count µC clocks in Cntr until it reaches BL, then reset Cntr Phase 4: IF INT does NOT go low before Cntr reaches BH THEN the HIGH period is too long => exit ELSE copy Cntr value into result register RB and reset Cntr generate an interrupt to wake the micro if micro can react within AL, then interrupt-latency = zero AL= 0.75 x tSHORTEST
AL Low Period
BL High Period
AH
BH
RA
RB
SW programs limiting values: AL = minimal LOW time AH = maximal LOW time minus AL BL = minimal HIGH time BH = maximal HIGH time minus BL End results in output registers: RA = LOW time minus AL RB = HIGH time minus BL
AH= 1.25 x tLONGEST - AL
75% 125% 75% 125%
Philips Semiconductors
Startpoint = RC-input pin INT goes low
Mainstream Tv Solutions - 10-2003 - Hercules presentation 3-26
RCP-Method (counter & comparator) :
RESTRICTED, contains NDA items
AL AH
1
NegEdge
BL BH
3
CDIV 1 (CDIV+1)
DAT
CDIV 2
DRCP
4
Comparator
3mm wide Guard Ring around the IC + direct components. The following slides describe the UOC-III in QPF128 package, mounted on Single-layer PCB material.
Philips Semiconductors
Do’s and don’ts with
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-8
RESTRICTED, contains NDA items
RESTRICTED, contains NDA items
• Single-sided PCB: extend ground-plane and connect via multiple tracks
6 8
92
Digital ground-plane
Xtal 12
89
Analogue-plane 81
18
“ground-plane” under IC, locally extended outside pinning
VIF 28 SIF
68
• Keep Digital & Analogue currents away from each other, decouple locally
1. All time bases are calibrated to the Xtal (max. 30ppm). The oscillator design has tunable capacitors inside to improve accuracy of the clock (no external capacitors). This improves system performance of: NICAM decoding, Colour catching, sync locking, OSD, Teletext, C.C. decoding etc. 2. The space under the IC should be filled with a ground plane. If you need to cross this with a signal, it is best to put a jumper in the signal wire. Avoid using jumpers or zero Ohm SMD’s in a ground connection. These have higher inductance than a thick copper track. 3. Connect all ground pins to the copper plane under the IC. 4. Components that need ground reference, should all be connected to the ground-plane, or to local extensions of it. These extensions should be kept free from other currents, to allow really “clean” grounding.
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-9
G u a r d R i n g
95
Philips Semiconductors
• Low impedance between ground pins = ground plane
1
101
• Leave Xtal floating, use no external capacitors
121
Ground references:
40
Untill ES7.2D: add 2x 6p8
125
??
RESTRICTED, contains NDA items
+VDDA
ZA
+VDDC
ZC
+VDDP
LC,EXT
ZP CP CC CA CA,LF
• Parallel ground wires = less inductance = better reference • Extra coil in digital VDDCore ⇒ effective on-chip decoupling
Ground connections: The voltage reference inside the IC is connected via several parallel bonding wires. The resulting inductance is low enough to avoid ground-bounce by ACcurrents (all I/O pins would start radiating). Supply, VDDPeripheral and VDDAnalogue: Analogue circuitry needs good, external decoupling, both HF and LF. Supply, VDDCore: Digital circuitry produces wide-band noise. On-chip decoupling helps to shortcircuit this inside the IC. Don’t put an external capacitor CC direct at pin VDDC, because this will route more of the digital noise outside the IC. Better increase the series inductance with LC,EXT because: LC,EXT limits extern AC currents, ALSO through ground connection !! (= less ground-bounce by switching of core circuitry) (Voltage model: larger L in supply = less voltage over small L in ground) The supply-bounce will of course increase, but pure digital circuitry is quite immune for that (practice value: LC,EXT = 2.2 µH to 15µH). Conclusion: an external coil can make on-chip decoupling more effective.
Philips Semiconductors
+VDD
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-10
Grounding & supply:
RESTRICTED, contains NDA items
• First 390Ω at pin 41, then 100nF to ground
A modulation of the IF-PLL loop-filter voltage, will automatically cause a frequency modulation. Via the SAW filter’s Nyquist slope, a PM-to-AM (Phase Modulation to Amplitude Modulation) conversion takes place. This results in a visible modulation of the CVBS output. Between the resistor and the capacitor, we have a good monitoring point of the IF-PLL loop filter voltage. That’s why the capacitor is connected to ground and not the resistor. Use only a high Ohmic probe, otherwise you may influence the IF-PLL too much.
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-11
IF-PLL loop filter
Philips Semiconductors
• Pin 41 is sensitive for disturbances. Any modulation can be visible on the screen
40 PLLIF
IF-PLL loop filter decoupling:
RESTRICTED, contains NDA items
SAW
Main Ground
Integrated IF-AGC time constants
24
LPF
25 IF inputs
41
0o IF AGC
28
VCO
IF-PLL Loop Filter
90o
V/I IF Ground
40
• Pin 28 is ground for SAW filter pin 3 (to internal IF circuitry) • The lF-PLL loop filter is connected as short as possible, with a separate track to ground pin 40 • Pin 18 and 40 must have a short connection (via ground plane)
The Application Manual gives details which ground pins are used as reference for certain circuits. In all cases it is best to connect ALL ground pins to a ground plane under the IC.
Philips Semiconductors
18
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-12
IF-PLL loop filter:
RESTRICTED, contains NDA items
• Improper decoupling ⇒ - horizontal jitter - disturbed vertical deflection - etc. 12
• BOTH capacitors to same ground near pin 18 • Take care that NO digital currents can flow via pin 18 (will disturb Bandgap grounding)
18 19 = SECPLL 20 = Bandgap
• SECAM-PLL needs 220nF decoupling to neighbour pin 18, use low-leakage type
Band-Gap pin 19 needs 2.2 uF low-frequency decoupling plus 10 nF highfrequency decoupling. If these two capacitors are connected to different grounds, all voltage differences will be injected into the Band-Gap reference voltage. The SECAM PLL decoupling capacitor should be a “low leakage” type. Otherwise black-level offsets on the U and V signals can occur, depending on temperature, humidity etc. Static offset can be visible, mostly in B-Y. This can now be compensated via bits SB01..0. (Secam B-Y Offset adjustment)
Philips Semiconductors
• Bandgap = reference for many functions Decouple pin 20 both HF & LF
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-13
Band gap & SECAM-PLL decoupling:
RESTRICTED, contains NDA items
• DecDig = 2.5V can be used to control a 1.8V supply ⇒ add series resistor to keep decoupling local ⇒ add 2.2uF for loop stability
12 14 = DecDig 18
The DecDig pin 14 decouples an internal voltage of 2.5V. This voltage can be used to make a self-controlled 1.8V supply. Via software it is possible to enable a feedback from three 1.8V supply inputs towards the DecDig 2.5V output. During standby mode of the video processor, the DecDig pin is pulled low (< 0.4V at max 1mA sink current).
Philips Semiconductors
• Internal digital supply pin 14 should be decoupled to pin 12 via minimal 220nF
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-14
Digital decoupling:
RESTRICTED, contains NDA items
95 92
6 8
89
12
18
28 ONE connection Low inductance
81
68 40
• Single point grounding must have LOW inductance
Local reference ground
Double Layer PCB: All critical components can best be mounted under QFP package and grounded to the ground-plane. Single Layer PCB: The grounding of direct components can NOT be made to the ground-plane. For proper grounding of critical components like phi-1/2, bandgap etc., a separate ground structure is necessary. This should be connected to the ground plane under the IC, via as many connections as possible. For single-layer layout this will certainly cost some board space. Guard Ring: The IC-ground should be grounded via ONE point only, near the tuner and IF path. When ALL currents are kept local, there will be hardly any current through the connection towards the Guard Ring. Still it is important to give this connection the lowest possible inductance, to avoid problems with flashes (surges, discharge tests etc.).
Philips Semiconductors
101
121
1
• Guard-Ring around high impedant zone
125
Guard Ring
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-15
One connection of IC-ground to Guard Ring:
RESTRICTED, contains NDA items
92
6 8
89
12
• Guard-Ring must have low impedance
81 18
69 68 40
28
• Comb filter VDDCOMB only to pin 68, no shared currents
B G R Ibl
12µA Iblack-return
The RGB cable that goes to the CRT panel (picture tube) is always long and will act as antenna for disturbances. The three RGB outputs can be equipped with filters, but the ground connection can NOT. Therefore it is best to lead this to the Guard Ring. Make sure the Guard Ring is low Ohmic, otherwise ground currents can be super-imposed on the small measurement currents (12uA) of the black current stabilization loop (CCC). This can show as loop instability. The Comb-Filter supply input pin 69 must be decoupled to ground pin 68. Since this is quite noisy, we advice to route pin 68 only to the ground-plane.
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-16
95
Philips Semiconductors
101
1
121
• Iblack return needs clean path
125
CRT-panel ground to Guard ring:
RESTRICTED, contains NDA items
12 ϕ2 ϕ1
• Dominant for sync performance
16 = Phi2 17 = Phi1 18
VIF 28 SIF
The two phase loops are very sensitive, to get a good sync performance. This also means that the phi-1 and phi-2 components need a good, clean ground.
Philips Semiconductors
• Clean grounding at pin 18
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-17
Phi1 & Phi2 loop grounding:
RESTRICTED, contains NDA items
12 ϕ2 ϕ1
• Keep vertical reference components very close to the IC
18
VIF 26 = VsCap 27 = Iref 28 SIF
The vertical ramp capacitor and the current reference resistor demand a clean, separate grounding to pin 18. Disturbance on these reference components can easily be visible as “line pairing” on the screen. The human eye is very sensitive to this kind of effects (up to -60dB).
Philips Semiconductors
• Clean grounding at pin 18
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-18
Vertical reference components:
RESTRICTED, contains NDA items
• Disturbance, picked up by deflection cable runs through V-amplifier, into pins 22+23 • Neutralize parasitic coupling to VIF by decoupling Vdrive A/B pin 22+23 at pin 18 and use series resistors
12 ϕ2 ϕ1
18
V-Amplifier
V-deflection
22 = VdrB 23 = VdrA VIF 28 SIF
The connecting wires to the vertical deflection coils are long. They can easily pick up disturbances, so the outputs of the vertical amplifier should be equipped with filter chokes plus capacitors. The large output transistors have large capacitive coupling to the amplifier’s substrate. So HF disturbance can “walk-through” the vertical amplifier, into the vertical drive lines. These are located next to the SAW filter inputs, so pins 22 & 23 need to be decoupled near the IC. At the position where the vertical drive lines cross the Guard Ring, it is best to put 1k Ohm series resistors. If the drive lines are long, it may be better to add a second filter stage. Keep the tracks between series resistors and pins 22,23 short to minimise parasitic coupled “body” to the VIF lines.
Philips Semiconductors
• Vertical drive = long lines ⇒ add series resistors
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-19
Vertical driver decoupling:
RESTRICTED, contains NDA items
12 ϕ2 ϕ1
• Leave pin 28 floating
18
(= internally connected to GND pin 40) VIF 28 SIF
“Method 1”
The tuner output is normally 75 Ohm. After the SAW filter the impedance is higher (2 kOhm), so it is logical to put the SAW filter as close as possible to the One-Chip. To avoid differential pick-up, it is best to route the IF leads completely symmetrical. Even for an a-symmetrical tuner output, the wiring should be kept symmetrical. The ground wire should be grounded near the signal source, so at the tuner. The SAW filter substrate pin 3 should be grounded to the One-Chip pin 28, via a clean, separate path. The tuner should be connected to the IC main ground pin 18. Try to minimize the total loop surface of IF lines and ground connections. In a-symmetrical application, SAW filter pin 2 must be grounded (for optimal trap performance, according manufacturer).
Philips Semiconductors
• SAW filter substrate (pin 3) via clean grounding at pin 28
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-20
SAW filters and IF leads:
RESTRICTED, contains NDA items
12 ϕ2 ϕ1
• Compromise: single-point grounding Symmetrical around IF path
18
VIF
• You can connect pin 28 to the IC ground plane, but ONLY after EMCvalidation was proven OK
switch
28 SIF
“Method 2”
Try to keep the total loop surface of IF lines and ground connections minimal. A large “body” will pick-up more disturbance than a small one. Method 2: Switch able SAW filters are usually driven form an a-symmetrical tuner. SAW pin 2 has to be switched to either pin 1 or pin 3. This means we can NOT use the SAW filter as separator (see “Method 1”) between Guard-Ring and IF ground pin 28. The alternative is to route the ground all around the IF-area. The vertical reference components can now be connected differently, but try to keep the SAW filter substrate (pin 3) free from modulation. Use as many parallel ground connections as possible. Grounding of pin 28: First verify that no unwanted currents can flow through pin 18. If this is OK, then it is safe to connect pin 28 to the ground plane.
Philips Semiconductors
• Keep IF-area as small as possible
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-21
Switch able SAW filters and IF leads:
RESTRICTED, contains NDA items
Tuner
PC
RF: Video SAW: PC-CC
SC
PC
CC
Low Z
IF:
PC
CC
No shared currents
IF Gnd
IF Gnd
Injected disturbance
In Europe an EMC test (EN55020, Conducted-Current Immunity 26.. 30MHz) needs special attention: when a SECAM-L1 transmitter is tuned and the injected disturbing frequency is at: FIF - chroma. The SAW filter suppression at 29.5 MHz is about 35dB. The video part demodulates this unwanted lower side-band to base-band, were disturbs the Colour Carrier demodulation. This will be visible, so the SAW filter application is very important (you can’t filter away this disturbance anymore). Keep layout and track impedances symmetrical (even with a-symmetrical tuner). Any a-symmetry makes the signal less immune to common-mode disturbance. The SAW filter pins inevitably have parasitic capacitance to the SAWsubstrate. This capacitive path bypasses the SAW. Therefore the substrate should have a low-impedance ground connection, preferably near the IF inputs (SAW IN = 75 Ohm, SAW OUT = 2 kOhm). The track must not share currents that generate (over the track impedance) a disturbance voltage between SAW-ground and IF-circuitry-ground. We advice to connect the IC-ground to the tuner, close to the IF leads.
55.7
40.4
38.3
Symmetrical IF inputs
33.9
Injected disturbance
29.5
f 40
28
4.43
PC-CC
Philips Semiconductors
CC Each pin of a SAW has some substrate capacitance. This bypasses the filter-curve unless substrate is grounded very well
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-22
SAW filter grounding, SECAM-L1:
RESTRICTED, contains NDA items
IF path:
1 + Tuner
“Method 1”
75
Z13
2k
Z23 Z43
Z53
5
24
4
25
3
28 UOCIII
1 ground connection: make use of Common-Mode rejection
+
+
“Method 2” 2 ground tracks, symmetrical ground around IF circuitry
Method 1: We advice to connect the main ground pin 18 to the tuner. Keep this ground a bit close to the IF leads to minimize the loop area for magnetic coupling. Method 1 clearly shows that currents, injected at the tuner metal housing will NOT flow through the SAW filter grounding. When the IF tracks are symmetrical, we can now use the Common-Mode rejection of the SAW filter to “isolate” the tuner from the IC. Method 2: It is difficult obtain perfect symmetry. When the SAW filter performance is critical, the tuner output amplifier should have the same ground reference as the IF input amplifier. BUT: by connecting the ground via the SAW filter, ALL other IC currents will ALSO flow through this path. To avoid IF disturbance, it is best to route TWO ground tracks, next to the IF lines. Both ground tracks must be connected: - near the tuner, - under the SAW filter, via its pin 3 - near the IC and to pins 28 and 18 Magnetic pick-up can be minimized by twisting the IF lines half ways, (SMD jumper) between SAW filter and IF inputs (2kΩ) this can be very effective.
Philips Semiconductors
+
SAW 2
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-23
40
RESTRICTED, contains NDA items
+
SAW 2 1 + Tuner
75
Z13
2k
Z23 Z43
Z53
5
24
4
25
3
28 Hercules
40
+ A
24 25
B +
Switch 28
For switchable SAW filters, surrounding ground is a MUST
Single ended “asymmetrical” tuners should be connected to the SAW filter via a symmetrical pair of IF tracks, routed close together. For optimal filtering, SAW pin 1 should be IF-input and pin 2 ground. For applications with a switchable SAW filter, a grounding near the IF path is even more important. Usually an a-symmetrical tuner is used, to minimize the switching components. The switch is in the IF signal path: it either short-circuits filter “A” or “B”. It is obvious that the return-ground from SAW to tuner has to be routed close to the IF track. Just like in “Method-2” on the previous slide, it is best to embed IF, SAW and the complete switching circuitry between ground tracks. Remarks: - If the (capacitive) load of SAW plus switch is high (>12pF), an amplifier/buffer is necessary in the IF signal. - The command line of the switch should have a blocking impedance for IF (& HF) frequencies, near the SAW filter. A transistor is NOT a blocking impedance so a base resistor (47k) should be added.
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-24
40
Philips Semiconductors
Asymmetrical tuners:
RESTRICTED, contains NDA items
R1
Tuner
4 2
Switch
IF1
A
B
5
Band switch diode BA782
IF2
A
high
(= less capacitance to IF lines)
+5V Tuner
L2
C2
Digital switch
R1
L1
switch diode conducting • Use coil L1 (makes SAW & switch “Ohmic”) to couple DC-switching
B
low
R2
• Enough forward current to make
L1
tuner IF output = less components • Enough reverse voltage to have low capacitance of switch diode
R2
+5V Tuner
R3
• Minimal parasitic capacitances on
IF >3mA
3
R4 C1
The Tuner IF output stage can usually drive up to 20pF capacitive load. With two switch able filters (VIF+SIF SAW) plus wiring you can easily exceed this capability. Therefore a coil L1 to ground is added, that will annihilate the capacitive load and give a more “Ohmic” impedance. Coil L1 now allow us to put DC-switching voltages on the IF-line without adding capacitive load to it (parasitic capacitances of components). Coil L1 is permanently AC-grounded via capacitor C1. Note: Although the switching transistor could be directly driven from an I/O port, we add a second transistor + high Ohmic base resistor. This avoids EMC injection into the SAW filter grounding. Make sure that the +5V has a series choke plus proper decoupling (C2) to the IF ground. The series choke has to block EMC injection via the supply.
Philips Semiconductors
+5V
E.g VIF: K7257M or SIF: K9653D
VR >3V
Tuner
1
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-25
SAW filter switch @ 5V:
RESTRICTED, contains NDA items
6 8 Xtal 12
⇒ Solve crosstalk issues in chassis
18
⇒ Re-connect after evaluation
95 92
“ground-plane” under and outside pinning Guard-Ring around high-impedant zone
89
B G R Ibl
81
28 SIF
40 PLLIF
VIF
• Connect 28 to ground-plane after validation
101
1
121
provision to split ground-planes into digital and analogue part
125
• In first layout:
68
Single Point Grounding
It is best to start a new layout with the ground plane and the Guard Ring. During the layout phase, e.g. series resistors can be used to jump over the Guard Ring. In this way the copper area, spent for better grounding can be “hidden” under the components. Thus minimizing the extra PCB area for the Guard Ring approach
Philips Semiconductors
Guard Ring
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-26
QFP-128 package on Single Layer:
RESTRICTED, contains NDA items
Ground strip under series resistor reduces parasitic parallel capacitance R
Line-up the series resistors, to minimise the parasitic capacitive coupling to long lines
• Always put a ground-plane under the IC, even on 2-layer PCB • Connect ALL ground pins to this Local Ground-plane • Route return-currents first to their GND pin and then to ground = keep both signals AND return currents separated
Even with double layer material a ground plane under the IC is still necessary. This assures that all ground pins share the same reference-potential. No currents should ever flow into one ground-pin, through the IC and then out via another ground-pin.During flashes (=high dI/dt) this might pull certain parts of the silicon below zero and cause malfunction. On a bi-layer we recommend to make the two IF connections between SAW filter and IC above each other. By carefully implementing a “twist” halfways, the EMC performance can be increased considerably. Especially in the range around the IF frequency (e.g. for BG: 33.4 .. 44.4MHz).
Philips Semiconductors
R
Local Groundplane
Ground Layer
Parasitic capacitor, parallel over R
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-27
SMD package on Bi-Layer:
RESTRICTED, contains NDA items
Local IC Ground
1.8V2 Local IC Ground
Layer1 = Signal 1.8V1 Power Plane
Every IC has it’s local Ground plane directly under the IC-body Layer2 is mainly used as ground layer, but locally as power plane
3.3V Power Plane
Keep layer3 as un-interrupted ground layer / shield
Layer2 = “GND” Layer3 = GND 5 V Power Plane
Layer4 = Signal
• Connect ALL IC-ground pins to the Local Ground-plane on Layer-1 • Route return-currents first to their GND pin and then to Layer-2
Philips Semiconductors
Component side
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-28
4 layer: Ground & Power structure
RESTRICTED, contains NDA items
QFP128
Signal1
3.3V Bulk decoupling capacitor close to IC
Local Ground Plane under IC
Gnd2
3.3V Power Plane under IC
Gnd3 Signal4
5V Power Plane under IC Ferrite Bead
5V
Ferrite Bead
3V3
Philips Semiconductors
5V Bulk decoupling capacitor close to IC
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-29
4 layer: decoupling capacitors
RESTRICTED, contains NDA items
ü2- VDDA+P well decoupled, VDDC via extra choke (no C on pin) ü3- Narrow Guard Ring around IC + direct components ü4- Blocking impedance in every line across Guard Ring ü5- Single-point grounding near IF (or symmetrical around IF tracks)
Above anything else, a good ground connection with low-impedance is needed. Feeding “strange” currents through the ground inside the IC may lead to unpredictable results (all references are made to ground). Pure digital circuitry like a micro-core - with On-Chip decoupling - can handle quite some supply bounce. Use this property to limit radiation: put a coil in the core supply BEFORE decoupling it. Reserve a small capacitor directly on the pin, but do not mount this unless the supply bounce is too high. For C18 process the max Vdd-peak = 2.4V. The Guard Ring + blocking impedance's are the hardware equivalent of a “fire-wall” in computer networks. The IF part is the most delicate one. Therefore we give it the best possible ground reference.
Philips Semiconductors
ü1- All ground pins direct to ground plane under IC
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-30
Five absolute MUSTs:
RESTRICTED, contains NDA items
– pin 3,4,5,14,15,20,38,45,47,69,82,90,91,93,94,100,117,118,124
• Loop filter components close : Secam pin19; IF pin 41; Phi1,2 pin 16,17 • In principle, try to route decoupling capacitor to ground pin: – – – – – – – – – – –
pin 3,4 to pin 2 pin 12 to pin 88 pin 89 to pin 90 pin 91,93,94 to pin 92 pin 100 to pin 101 pin 110 to pin 121 pin 124 to pin 125 pin 82 to pin 81 pin 69 to pin 68 pin 14 to pin 12 pin 15,16,17,19,20 and pin 22,23 and pin 26,27 to pin 18
• Keep digital currents away from DECBG decoupling pin 20 to pin 18
Philips Semiconductors
• VIF,SIF SAW short ground track to pin 28. Short & symmetrical tracks to pin 29,30 & 24,25 • Xtal as close as possible via symmetrical, short tracks • All 100nF/220nF decoupling capacitors very close to belonging ground and supply pin
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-31
Summary of grounding:
RESTRICTED, contains NDA items
• A complete TV system, more than just a demo-board • Made by Philips Semiconductors to: - Eliminate potential problems before customers get ICs - Evaluate IC, Hard- and Soft-ware - Have a realistic reference TV - Small-Signal “Plug-In” allows quick comparison between various IC concepts (e.g. UOCII versus UOCIII Hercules)
The UocSuperBig TV receiver has its small-signal part on a Plug-in module, that contains just the IC and its surrounding components. This enables evaluation of several IC-concepts in the same environment. Test results are significant for customer implementations, because the USB layout is as “realistic” as possible. The Plug-in module hardly affects system performance, especially not when the connectors are skipped and the Plug-in is directly soldered onto the USB chassis. The USB-receiver can be used as a “system-level” reference design.
Philips Semiconductors
An application example:
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-32
Reference Receiver “USB”
RESTRICTED, contains NDA items
Audio
Filter
GreenChipTM
Vertical
Driver Line Transistor
East-West Transistor
Tuner
TDA8357
SAW
Mains
LOT / FBT
• Large components & heat sinks determine floor plan
If you start building a receiver, you always start with the large components. 1. The Line Fly-Back Transformer is usually at the PCB edge because of focus & VG2 alignment and mechanical stability (e.g. drop-test) 2. Scart plugs need to be accessed from the rear side 3. The tuner should be far away from the FBT, to avoid self-locking (receiving own H-deflection). 4. The SAW filter is shortly connected between tuner and VIF/SIF inputs The rest of the PCB is for Vertical, Audio and Power Supply.
Philips Semiconductors
Rectified Mains Capacitor
SMPS
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-33
Mechanical floor plan of a receiver:
RESTRICTED, contains NDA items
Small area on Power Ground Rectified Mains Capacitor
Audio
SMPS
Filter
GreenChipTM
TDA8357
Low Impedance structure
SAW
Driver
Vertical
CRT Supply
IC
Mains
Tuner
Line Transistor
East-West Transistor
CRT LOT / FBT
• Keep Guard-Ring area SMALL !
This ground pattern is in accordance with the Guard Ring philosophy. The ground strip at the rear side is used to short-circuit radiation, picked up between antenna cable and mains power cord (safety caps). For HF disturbances, the mains filter and the SMPS transformer are easily bypassed. To avoid unwanted coupling to the UOC, the central “back-bone” in the ground pattern can be used as a barrier. Suppression filters at the secondary side of the SMPS can be grounded to this structure.
Philips Semiconductors
High Impedance structure
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-34
Ground floor plan of a receiver:
RESTRICTED, contains NDA items
Coupling capacitor holds DC-clamp voltage
These components suppress energy from discharges
DC-clamp current into < 300Ω 100E
100E
Inside IC circuits are DC-coupled
68p
100p
Sparc gap
75E
100n
Line Impedance Termination
Example: video input with DC-clamp
• Separate ground currents (IC-ground from AV-inputs) including shield grounds • Advice for first layout: (minimise risk) reserve 68pF from each (audio &) video input to IC-ground (close to IC) – Reduces risk of cross-talk (HF-pick-up, video-to-video, video-to-audio etc.) – After test phase evaluation some capacitors may be deleted
Philips Semiconductors
DC-clamp circuit
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-35
Minimise Audio-Video crosstalk:
RESTRICTED, contains NDA items
• Capacitive
Horizontal Deflection
coupling via cables
D.U.
RGB
R4 +8V R5
C3
R1
Aquadag
Focus
R2
Grid-2
FBT/LOT
H
C2
Grid-1
Video Amp.
D2
V
D1
Cathodes
C1
Filament
R3
spark gaps
+Vs
IC
Anode
Anti-crackling layer
CRT Supply
A good ground floor plan is essential for a TV set to survive Picture-Tube flashes. But also wiring and component-choice play a role. Picture Tube: (hard-flash or soft-flash type) The PT has a capacitance (1..3nF, 30kV) between aquadag and anode. A flash discharges this capacitance to the electrodes in the gun. A hard flash PT can reach peaks up to 500A, a soft flash type has a resistive layer that limits to 90A,~300 Ω. Video CRT amplifier: (limiter resistors R1,R2 & protection diodes D1) spark-gaps limit the max flash voltage and can be integrated in the picturetube socket or on the PCB. A super soft flash will not open spark-gaps and can last quite long. When such a flash is dumped (via D1) into a supply capacitor (C1), this must be able to absorb almost all energy out of the PT. EHT, deflection: The (vertical) deflection coils are capacitively coupled to the PT (even more with anti-crackling layer). A flash can short-circuit the line-output stage, while unexpected large currents can flow out of C2 (~½nF). Guard Ring and cables: Any “body” is capacitively coupled to the flash, so select the position of connectors and cables very carefully. Keep currents away from the IC.
Philips Semiconductors
EHT Vertical Deflection
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-36
Flash precautions:
RESTRICTED, contains NDA items
0V 1.5V 3.3V
+8V 10k
3.3V
Software Low + Open Drain High + Open Drain High + Push Pull
1.5k +3V
3.3V 47k
3V + Config
Sw
-
47k
1 Out
1k
High High 47k
Mid Mid
Mid
47k
+
Low Low
0.5V -
High
47k 47k
Low
3-level decoder
Open collector output buffers
• Less lines needed for switch functions • 3-levels by switching between Open-Drain and Push-Pull • SW can change I/O configuration per pin, at any moment
3.3V Config
Config
Low Out
Open-Drain, low
3.3V
3.3V
Config
Mid Out
3.3V
High Out
Open-Drain,
float
Push-Pull, high
Philips Semiconductors
Level
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-37
Simple 3-level decoder:
RESTRICTED, contains NDA items
5V compatible, 4mA sink
47k
3k3
VST tuner Lo Mid Hi
4k7 4k7 4k7
I III IV
4k7
• Only one transistor for +5 Volt tuner band switching
The band-switch inputs of a VST tuner usually have internal pull down resistors of 4.7kOhm. With 5V tuner types, a band-switch is activated when the input pin is above 4.5V. This specification can not be met by a micro controller that is running at 3.3V. But since the digital UOC outputs are 5V tolerant, we can add pull-up resistors of 3.3kOhm to +8V. Together with the 4.7kOhm pull-down this gives a “high” level of 5V.
Philips Semiconductors
Px.x Px.x
3k3
+8V 3k3
Hercules
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-38
Cheap 3-Band switch for VST tuner:
RESTRICTED, contains NDA items
CC
4.43
IF1 IF2 2
3.58
3 38.9 = K7252M Euro 38.0 = K72xxM China 45.75= K72xxM USA
38.9
4 5
VIF1 VIF2
+8V
4.43 33.9 38.9
2
1k8
4 5
4k7
38.9
PC
1 L1
3
4 5
VIF1 VIF2
K3953M / 53D
3.58 3
K72xx SC 5.5 .. 6.5
1
1k8
10k
10k
CC
PC
4 5
SIF1 SIF2
4.5
2 3
SC 5.5 .. 6.5
1
10k
UV1316 / 1336
SW
CC 1
4.43 2
PC
SC
Hybrid Analogue + DVB
10k
1
1k8
IF
1k8
4k7
+8
Quasi-Split Sound
4 5
SIF1 SIF2
L1 : 40.4
2 3
K9656?D
K96xx
38.9 = K7257M+K9653D Euro 38.0 = K7262M+K9655D China
1
8MHz 36.15
2 3
4 5
X6966M
SAW filter types: X72xxX = Video & Inter-carrier SAW, simplified switching (5 pins: switch= pin 2 to pin 1 or pin 2 to GND pin 3) X96xxX = Audio SAW, simplified switching (compared to X94xxX / X95xxX) X35xxX = Combined QSS sound & video in 5 pin package XxxxxD = SIP5D low-profile package (high density packaging)
Type numbering e.g.: G 19 84 M TV standard: G = B/G B = Australia J=I K = D/K or BG..DK L = L + L1 M = M/N USA N = M Japan
Family Number
Package: M = SIP5K D= SIP5D K = DIP10K L = DIP18D
Philips Semiconductors
Inter-Carrier Sound
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-39
Switchable SAW filters:
RESTRICTED, contains NDA items
SAW Filters
I2C
Peri
AGC
VIF
Audio
Audio Amplifiers 16:9 110o
AudioOUT
M/M
• Very compact design
RGB
TDA120xx “Hercules”
IBLACK
VIF Second Sound IF FM demodulator Source Switching Sound Control Sync Processing Geometry Control PAL/SECAM/NTSC RGB Processing Micro controller 32 .. 192K ROM 1 .. 2K RAM Teletext Closed Captioning On Screen Display RDS/RDBS Stereo processing
Guard
TDA6108A 3x RGB Amplifier (80)
V-drive
CVBSMON
RGB/YPRPB
Audio Y/CVBS C
Keyb
TDA8359
V
DC Vertical Amplifier
BeamCurr +12V
H-drive Flyback +8V
+36V
BU2508DF Horizontal Deflection & EHT
+3.3V Stby
+115V
TEA1507
H EHT
DeGauss
GreenChip SMPS
24.576MHz
I2C
PCA8521 RC-5 Transmitter
I2C-2
IR
• Mono or stereo
PCF85116 2Kb EEPROM EA99009
Philips Semiconductors
UV1316 PLL Tuner
• NTSC-M-N, PAL-M-N-BG-I-DK, SECAM-BG-DK
LS
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-40
Global Traveler: LS
RESTRICTED, contains NDA items
1n
E
Comp
Comp
VGUARD
ZCOMP i COM + ½i VERT
400 200 150 100
IDRIVEB
1n
< 560
i COIL
LDEFL D VFEEDBACK
A
i COM - ½i VERT
9 VOUTA 7
1n
RCON
00H 1FH 3FH VA
1
< 560
B
RCOMP
InA
2
InB
5
Gnd
2k2
IDRIVEA
2k2
IDRIVEA,B (µA)
700 650 600
3 V = +13V P
8
100E 10k
VGUARD
2k7
+ RDAMP RMEAS
4 C
VOUTB
TDA10xxx TDA8357/59
• Vertical Shift easily set via DC offset
The improved vertical amplifiers TDA8357 & TDA8359 (2 & 3A) have: • Higher LVD-MOS IC process voltage 68V (was 60V for bipolar 8351) • Better SOAR because DMOS has no secondary breakdown • Lower dissipation and lower scan voltage (e.g. +13V , was +16V) • Improved reliability: homogenous heat distribution across the device • Reduced dissipation at end of flyback (add zenerdiode + resistor) The required input biasing plus the conversion from current into voltage is done via two fixed resistors RCON of 2.2kΩ. The gain of the vertical amplifier can be selected by RMEAS. • Max. peak current (while VA = 3FH) out of IDRIVEA or B is :
ICOM+¼ IVERT,MAX = 400 + 300 = 700µA • Input voltage at pins 1 and 2 should remain below 1.6 Volt :
700µA x 2.2kΩ = 1.54 Volt • Nominal (VA=1FH) differential voltage between InA,B or over RMEAS is:
950µA x 2.2kΩ = 2.1 Volt • RCOMP must be calculated (see data sheet), voltage of ZCOMP=VP. • IDRIVE pins max. output voltage = 2.5V ⇒ series resistors < 560E
Philips Semiconductors
6 V FLYB = +36V
4.5V
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-41
DC-coupled Vertical Deflection :
RESTRICTED, contains NDA items
Horizontal Drive +3.3V Pulses
+VB
RDR
TD + D1
LLEAK
CF
TDR
IC
ϕ2-loop H-flyback
Pulse shaper
LP
EHT, VFOCUS , VG2 Beam Current, EHT tracking
+VB
CDIV +8V
FBT
LH
+5V, +8V, +13V, +36V
CS
CB
Linearity correction
Scan-rectified secondary voltages
• Low voltage start-up from 3.3V • 5V (IC), 13V & 36V (Vertical Deflection) scan-rectified
How to set-up the horizontal deflection stage ? • Determine necessary (scan) current through LP and LH (data sheets) • Find amplification factor of T1 at this current (e.g. BU2508DF at IC=2A gives 6x current amplification) • Calculate the base current for T1 ( [2A / 6] + [0.7V / 47Ω] = 330 + 15 = 345mA) • Divide it by the voltage ratio of the driver transformer (e.g. “10:1” with 345mA gives 35mA) • Collector current of TDR will roughly be double this current (2 x 35 = 70mA) • Make sure TDR gets enough base current to drive this collector current • Adapt RDR with a given supply voltage so that TD gets its calculated base drive current
Philips Semiconductors
Hor. Driver
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-42
Horizontal Deflection:
RESTRICTED, contains NDA items
+5V 47k
82k
EHT
Hercules 32 EHT
100k 1n
27k
IBEAM
+8V 83
6k8
BCL
Ringing
220k 47n
Only ONE long line
33u
13
2n2 1k8
100
10k
8
VGUARD
TDA8359 Guard
VGUARD ↑ 3.60V and ↓ 3.45V All EHT & beam current via pull-up Anti-ringing filter close to FBT (large currents) EHT compensation fast, average BCL is slow High-impedance = EMI-blocking in long connection line 10k
• • • • •
A line FlyBack Transformer (LOT or FBT) produces severe “beta” ringing, up to several MHz. This unwanted (large) current must be short-circuited close to the FBT. The transistor-integrator for BCL gives a “fast-attack” and “slow-decay” for too high beam current. Further it enables sharing ONE (long) line over the PCB with the EHT compensation input. The vertical guard pulse should be connected to the VGUARD input. Make sure that the (long) VGUARD line is sufficiently “blocked” The vertical pulse should go >3.60V and return 4µ7 capacitor is directly connected at the BCL pin (no resistor in between), otherwise the Peak-White-Limiter can start oscillating (typical rhythm of 2 µs periods, see Peak-White-Limiter function).
Philips Semiconductors
Overvoltage detector
FBT / LOT
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-43
Beam Current limiting:
RESTRICTED, contains NDA items
1.7 0.8
2.8 1.7 0.8
2.8 1.7 0.8
BCL below 2.8V : Start CONTRAST reduction
BCL below 1.7V (CBS=0) or below 2.4V (CBS=1) : Start BRIGHTNESS reduction
BCL below 0.8V : Blank RGB outputs
• Reducing CON & BRI limits max. beam current
(e.g. 1.5mA)
When the Beam Current increases, the voltage on pin BCL decreases. As the BCL voltage drops below 2.8V V, first the CONTRAST will be reduced (no loss of visible video). If this is not enough to limit the Beam Current, the BCL voltage can drop further. Below 2.4 V (bit CBS=1) or 1.7V (CBS=0), also the BRIGHTNESS will be reduced. This can push the low-intensity part of the video below blacklevel. Below 0.8 V the RGB outputs are forced to blanking level (= slightly below “black” level).
Philips Semiconductors
2.8
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-44
BCL voltage:
RESTRICTED, contains NDA items
= R2
0 0 Tuning [Volt]
30
0 Duty Cycle [%] 100
0 Duty Cycle [%] 100
400 0
Tuning [Volt]
30
Non-linear PWM Integrator
[MHz]
Frequency
850 [MHz]
Frequency
850
7
400 0 Duty Cycle [%] 100
The characteristic of a tuner is dominated by a varicap (= capacitance of a reverse biased diode). If we increase the tuning voltage linearly, the tuned frequency changes by an “S” shaped curve. In e.g. the UHF band the tuning steepness will vary between 35 and 3.5MHz/Volt when tuning from low to high frequency. The tuning resolution varies by a factor 10. For accurate VST tuning, a linear translation from “duty-cycle” to frequency would be ideal. In other words: the same “kHz/step” irrespective of high or low position in the band. We achieve this by using a “non-linear” integrator for the 14-bit tuning PWM DAC. By selecting different charge and discharge time constant, we can modify the translation from duty-cycle to voltage. When we multiply this with the tuner steepness characteristic, the maximum steepness reduces (28MHz/V) and the minimum increases (7MHz/V). Important is, that the steepness variation reduces from 10 to a factor 4. End result: - more linear translation from duty-cycle to frequency - more constant tuning resolution (better than 50kHz/step) - no need to compensate tuning curve in software
Philips Semiconductors
28 R1
[MHz/V]
3.5
+33V
Steepness
X
Vtune [Volt]
30 [MHz/Volt]
Steepness
35
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-45
Improved resolution for VST:
RESTRICTED, contains NDA items
FIF
FRF
SAW
PC SC 50 .. 850MHz
U.O.C IF in
FIF Tuner
SC
PC
HF Osc
IF Osc
AGC
AGC out AGC
FRF+FIF
• IF-PLL can only “see” what comes through the SAW • Tuning up makes AGC react first on PC
An off-air antenna signal FRF is mixed in the tuner with a local oscillator (FRF+FIF) to a fixed Intermediate Frequency FIF. The value of FIF depends on the market area (local laws, EMC relaxations) : - Japan = 58.75MHz - America & other NTSC countries = 45.75MHz - China = 38.0MHz - All others = 38.9MHz The IF signal is filtered by a Surface-Acoustic-Wave filter, that passes only the desired channel bandwidth around FIF (selectivity). The filter should always be close to the U.O.C., because the SAW is the only frequencyselective component in the whole IF path. In the U.O.C. the IF signal is first “gain-controlled” (IF-AGC), then mixed with an IF oscillator to “base-band” video. The audio carrier is removed in a sound trap. The amplitude of the resulting CVBS signal is used to close the loop for the tuner AGC (and IF-AGC). This gives a constant CVBS signal at variable antenna levels (FRF). Search-tuning can best be done in upward direction, so that the AGC loops can settle on the Picture Carrier (see next slide).
Philips Semiconductors
SC
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-46
Search-tuning with IF-PLL:
RESTRICTED, contains NDA items
• For weak transmitters the catching range is only 1 MHz - Conclusion: coarse tuning step size < 1 MHz (advice: 800kHz) • Stepping high to low gives AGC jump + locking on SC • Stepping low to high gives earliest locking on PC
The free-running frequency of the IF-PLL oscillator is calibrated exactly to the chosen IF frequency (using Xtal reference). The catching range of the IF-PLL is 2MHz, symmetrical around FIF (without taking SAW filter characteristic into account). When searching for a weak transmitter signal, the SAW filter attenuation above FIF will limit the catching range to about 1MHz. The software searchtuning algorithm should take care that tuning “steps” are always smaller than this worst-case 1MHz. Search tuning can best be done from low to high RF frequency. For searchtuning-down, the IF-PLL will lock on the Sound Carrier. Just before the Picture Carrier enters the SAW filter, it falls in the “neighbour” sound channel trap of the SAW filter (-60dB). This will cause large jumps in the AGC. Software should allow extra delay time to let this stabilize, before evaluating Sync Lock and AFC information.
Philips Semiconductors
Catching range = 2 MHz (+/- 1MHz)
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-47
Search-tuning with IF-PLL:
RESTRICTED, contains NDA items
3MHz takes about 30ms Large jump takes ..60ms Tuner spec: osc.lock < 150ms
Tuner spec: 110dBµVMAX
Osc
iAGC
-18dB
350mVRMS =1VP-P
IF
40dB Tuner AGC Small jump takes 7 frames) else skip unwanted signal Check CD3..0=1,0,1,0 (=SECAM) else skip false lock 4. Store in Eeprom, upon first recall: determine standard, Auto-following, re-store in Eeprom (TV & tuner are warm)
During a SECAM-L search, the system can sometimes give false lock on Negative-modulated transmitters. Sensitivity for this is reduced by STM=1 plus an additional check for SECAM colour ident. Make sure that before checking IVWF=1, the synchronisation has had at least 7 frames times stable signal (e.g. 160ms). After IVWF=1 you can immediately demand that chroma should have detected SECAM too (takes about 40ms).
Philips Semiconductors
1
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-50
Tuning algorithm for SECAM-L:
RESTRICTED, contains NDA items
Sound Mute
Video Blanking Fast Vertical catching
Vertical-sync IF PLL calibration
2
3
> 40ms pre-mute
RBL (or via OSD)
4
5 500ms post-mute
Limit this to max 350ms
NCIN
Automatic Following Horizontal-sync
1
Long post-Mute avoids glitches while “zapping”
SL IVW/F IFLF
Change tuning
Station found, Start sound & colour acq. Picture stable Switch-On IF-calibration only during channel-change
• Long post-mute avoids sound glitches while “zapping” • < 350msMAX is experienced as “immediately” • Keep IF-calibration off; only enable (IFLF=0) during channel-change
Audio pre-mute (soft) should be effective 40ms (~25Hz) before changing the tuning. This avoid plops during program or source switching. Video blanking (RBL=1) is postponed to the latest possible moment, to keep the visible transition short. 350ms gives a “sticky” feeling of the remote control. If it takes >350ms to lock on the new station, we advice to remove the picture blanking (RBL=0). RBL-blanking is internally synchronised to the vertical-retrace. As alternative SW can use a black OSD screen to blank the video. This has the advantage that possible OSD will not blink. As soon as SL=1 is found, the speed-up for vertical catching must be disabled (NCIN=0), otherwise bits IVW and IVWF will not work. Automatic following (AFC) should begin immediately after SL=1, to cancel temperature effects in the tuning system. Switch-On IF calibration (IFLH=0) after video blanking. Release it (IFLH=1) after SL=1 and before un-blanking the video. Fast settling of the AVL (auto-volume-leveling) after changing channel or source, is achieved by setting AVLM=1 during the audio Mute period.
Philips Semiconductors
Mute audio, fetch new Eeprom data
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-51
Program switching:
RESTRICTED, contains NDA items
minimal current when LOW Output-A
Output-B
minimal current when HIGH
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• Always maintain 3.3VSTBY (needed for I/O pins & necessary for infrared receiver) • Determine best output level for each I/O pin (advice to design for “low”) • Carefully determine SW delays between switching power circuits (take-over-time, avoid glitches …)
Philips Semiconductors
+
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-52
Lowest Power during TV-standby:
RESTRICTED, contains NDA items
– Last tuned program number – All analogue settings – On/off status of the TV
• Refresh the backup only when: – Something has changed in the current status – Remote control and local keyboard were “silent” for > 20 seconds
• Don’t overwrite Eeprom bytes that have not changed • Expected life-time for Eeprom with 105 erase/write cycles: – Average 10 refresh-overwrites per hour – Average 3 hours per day = (105 / (10*3)) / 356 = 9.13 years
• After RESET, software reloads the backup-copy from Eeprom and the TV continues as it was before
Philips Semiconductors
• Keep backup-copy in Eeprom of:
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-53
Make your SW reset-proof:
The ultimate TV design: Powering attractive TV products ! Philips Semiconductors - BL Mainstream Tv Solutions
Philips Semiconductors
III UOC “Hercules”
Mainstream Tv Solutions - 10-2003 - Hercules presentation 4-55
RESTRICTED, contains NDA items
