Sensors and Actuators A 125 (2006) 411–414

InP dies transferred onto silicon substrate for optical interconnects application M. Kostrzewa a,∗ , L. Di Cioccio a , M. Zussy a , J.C. Roussin a , J.M. Fedeli a , N. Kernevez a , P. Regreny b , Ch. Lagahe-Blanchard c , B. Aspar c a

CEA-DRT-LETI/DIHS-CEA/GRE, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France b Ecole Centrale de Lyon, LEOM, UMR CNRS 5512, 69134 Ecully Cedex, France c TRACIT Technologies, Zone Astec, 15 rue des Martyrs, 38054 Grenoble Cedex 9, France Received 20 May 2005; received in revised form 24 July 2005; accepted 24 July 2005 Available online 7 October 2005

Abstract We bonded quantum well InP dies on a photonic layer transferred on silicon CMOS processed wafer using direct molecular bonding. This approach is suitable for new applications, viz., photonics on silicon, 3D packaging and integrated sensors. The chips are diced from a bulk substrate and bonded directly onto a silicon substrate without any organic nor metallic adhesive layer. A thin silicon dioxide layer can be added on both assembled surfaces to enhance bonding quality. After bonding, the dies can mechanically be thinned down to 20 ␮m and chemically etched. The InAsP quantum well stack of the InP dies keeps its optoelectronics features and performances after being transferred onto a silicon substrate. © 2005 Elsevier B.V. All rights reserved. Keywords: Semiconductor materials; Molecular bonding; Optical interconnects

1. Introduction Recently, it was demonstrated [1,2] that optical interconnects could decrease power consumption and power dissipation in integrated circuit (IC), could eliminate delays in the clocksignal distribution, decrease the number of the metallic layers and finally increase the IC features and performances, especially in terms of maximal operating frequency. Fig. 1 presents one of the possible configuration of the optical interconnection (OI). The on-chip optical sources and detectors are coupled to a symmetrical waveguide. The optical signal is guided from source to receiver which converts the optical signal to an electrical one and provides to local electrical network. In this configuration the optical interconnects replace some part of very long global interconnects [3]. The optical devices can be based on the III–V materials alloys. However, because of the different lattice mismatch, the direct III–V epitaxy on silicon is not possible. Facing to this

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0924-4247/$ – see front matter © 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.sna.2005.07.023

inconvenient, we are looking for other alternatives integration techniques. The assembly using microsolders metallic bumps could be useful in the optical coupling of photonic devices and optical waveguides [4]. This involves the deposition of solder bumps on either the electronic or photonic IC, then alignment and bonding, usually using thermocompression. The optical coupling between optical device and waveguide can be realized thanks to micromirrors reflecting the light from laser diode to the optical waveguide [5]. However, this technology demands a realization and assembly of a metal coated micromirrors before flip-chip bonding. The use of BCB (benzocyclobutene) was also developed for assembling different optical devices on silicon. Roelkens et al. [6] and Christiaens et al. [7] demonstrated that a thin BCB spin coated layer is optically transparent and that the optical coupling between an optical device and silicon dioxide waveguides can be easily realized. However, this technique has a main inconvenient, a BCB refractive index (n = 1.55) is slightly higher compared to the SiO2 (n = 1.45). This implies an intrinsic reflection at the semiconductor/polymer interface and a reduced efficiency due to butt-coupling loss.

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Fig. 2. InP-on-silicon molecular wafer-to-wafer bonding. Fig. 1. Optical point-to-point interconnect configuration.

Spin on Glass SOG can also be used as a bonding material. Lin et al. [8] has obtained a heterogeneous structure comprising VCSEL-like structures which consist of GaInAs or InP cavities and Al-oxide/Si distributed Bragg reflectors successfully bonded to silicon substrate. However, a spin coating technique involves an adhesive material deposition on a whole substrate surface. This particularity could be harmful if we wish to locally integrate dies on the circuit with MEMS, sensors or other devices on the same substrate. Additionally, both BCB and SOG approaches do not fulfill to the front end of the line integration constraints. To overcome theses problems we propose the wafer bonding approach as a promising way to obtain monolithically integrated III–V optoelectronic devices onto silicon and to satisfy the requirements of optical interconnects. Jalaguier et al. [9] have demonstrated the feasibility of InP-on-silicon full wafer molecular bonding. Using the mentioned technology, we succeed in the fabrication of the HEMT structures, the photonic crystal fabrication and optical links [10]. A new technological challenge is also to integrate the chips of different semiconductor materials on one common silicon substrate to combine different functions and integrate different devices like power, optical, radio frequency and bio-electronic devices on one substrate. The molecular bonding technology could be also used in three-dimensional packaging of dies (dieto-die bonding). For this purpose, the integration of dies of different materials including germanium, gallium nitride and others semiconductors on one common substrate for the advanced System On Chip application [11] are considered. In this paper we present the adaptation of molecular bonding technology to bond the InP dies on a silicon substrate. 2. Results 2.1. InP-on-silicon dies molecular bonding The initial heterostructure containing an InAsP quantum well (QW) is grown by solid source molecular beam epitaxy on epi-ready semi-insulating InP(1 0 0) 2 in. substrate. First of all a 200 nm thick InP buffer layer was made to achieve perfect growth conditions. After that, a 300 nm thick In0.53 Ga0.47 As etch-stop layer was grown lattice-matched on the InP substrate. Finally, a 6 nm thick InAs0.65 P0.35 strained quantum well confined in 200 nm thick InP barriers was grown.

Before dicing, a 10–15 nm thick SiO2 layer is deposited on the III–V epitaxial structure using electron cyclotron resonance plasmas (ECR) in order to reinforce the adhesion between the III–V semiconductor and silicon dioxide on a silicon substrate. The dies are obtained by a mechanical dicing of 360 ␮m thick InP substrate. The surface of separated dies is cleaned and finally bonded on silicon substrate. The 1 ␮m thick layer of thermally grown SiO2 on the silicon wafer acts as a bonding layer. The SiO2 surface is polished to reach a low roughness and then cleaned. Thanks to this preparation, the bonding of the both InP/SiO2 and Si/SiO2 materials is similar to the Si/SiO2 on Si/SiO2 bonding which is a spontaneous molecular bonding of the hydrophilic type between the two carefully cleaned surfaces. A complete physical model of such a molecular bonding was proposed and presented by Stengl et al. [12] and G¨osele et al. [13]. Fig. 2 presents InP on silicon bonding configuration, via oxide layers. This bonding assures a good adhesion even at a room temperature. However, it is reinforced by an annealing at 200 ◦ C. The minimal die size we have bonded is 1 mm × 1 mm. An optobonder Pick&Place equipment can be used to report the InP dies. Over 90% of prepared dies was successfully bonded on the Silicon wafer. The advantages of using a Pick&Place apparatus are: to allow an alignment of the bonded dies and second, to control the vertical force applied by the Pick&Place head on the die during bonding. Even if the full wafer molecular bonding is spontaneous and do not demand the force application, we found, that in the case of the die-to-wafer bonding technique, we need to apply a slight force on the reported die to reach the successful bonding. Mechanical thinning of the bonded dies was then performed down to 20 ␮m thick without degrading the remaining bonded material quality. The SEM images present that no bending of the reported die is observed after bonding and thinning (Fig. 3). The quality of bonding interface was checked by infrared imaging: no defect was relevated. Furthermore, we demonstrated the compatibility of bonding strengths with mechanical actions such a grinding, polishing and dicing, as bonded dies were submitted to those technological steps without suffering any damage. Further thinning can be performed using a selective chemical etching; the remaining thickness of the InP substrate and the sacrificial InGaAs layer can be chemically back-etched by different chemical solutions [14]. The final thickness of the reported die with a QW can be reduce down to 256 nm (2 nm × 120 nm thick InP barriers + 6 nm thick QW + 10 nm thick ECR oxide). The

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Fig. 3. SEM images of a 20 ␮m thick InP die on silicon substrate.

Fig. 4. Optical image of a 256 nm thick InP die containing an InAsP quantum well bonded on a silicon substrate (a) and its PL cartography (b).

reported QW layer keeps its optical quality. Fig. 4 presents the optical view of an ultra thin InP die and corresponding photoluminescence (PL) cartography at 1.514 ␮m. The intensity is homogenous on the whole die surface. The maximal peak wavelength and the peak width at half maximum did not change after the bonding and the thinning process. So these technological procedures do not induce any significant strain or stress in the reported structure and do not deteriorate the optical properties of the reported dies. 2.2. Dies bonding on processed wafers We demonstrated also the feasibility of direct molecular bonding of the 200 ␮m thick InP dies (including QW) on the optical layer transferred on CMOS processed 200 mm of diameter wafer (Fig. 5). As a matter of fact, the optical layer was composed of waveguides processed on a SOI wafer and then transferred on a CMOS wafer using the wafer-to-wafer bonding process [15,16]. Finally, the backside of SOI substrate was removed and the relieved oxidized surface (SOI buried oxide layer) was cleaned. Then, InP dies have been placed on specific

Fig. 5. The InP dies bonded on 200 mm Silicon CMOS processed substrate with transferred optical layer. The dies were thinned down to 200 ␮m before bonding.

spots on the CMOS wafer. Fig. 6a shows an optical view from an InP die bonded on CMOS wafer with an optical layer and Fig. 6b shows an in-plane view presenting the optical waveguides transferred on CMOS wafer.

Fig. 6. 1.2 mm × 1.2 mm, 200 ␮m thick InP die bonded on optical layer transferred on a CMOS substrate (a) and optical waveguides on CMOS (b).

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3. Concluding remarks In this work focus on the optical interconnect application, we successfully demonstrated the bonding of the individual InP dies on CMOS processed wafer. The InAsP quantum well stack of the InP dies keeps its optoelectronics features and performances. This achievement paves the way for the introduction of various dies on a CMOS wafer for System on Chip (SoC).

[15] B. Biasse, M. Zussy, B. Giffard, B. Aspar, M. Bruel, Transfert de circuits SOI sur substrat transparent par adh´esion mol´eculaire, VII Journ´ees Nationales de Micro´electronique et Opto´electronique, Egat, France, 1999. [16] H. Moriceau, F. Fournel, O. Rayssac, A. Soubie, B. Bataillou, B. Aspar, Overview on some recent advances in wafer bonding technologies, in: Proceedings of the Sixth International Symposium on Semiconductor Wafer Bonding: Science, Technology and Applications, ECS Proc. PV 2001-27, 2001.

Acknowledgments

Biographies

This paper is a part of a study dedicated to PICMOS project partially supported by the EU under contract FP6-2002-IST-1002131-PICMOS. The authors thank E. Jalaguier, S. Pocas, P. Perreau, Ch. Kopp and the whole LTFC laboratory (LETI, CEA, Grenoble) for helpful discussions.

Marek Kostrzewa was born in Poland in 1975. He graduated in electronics and telecommunication science from Technical University of Lodz. He received the PhD from Ecole Centrale de Lyon in France in 2003. He joined the CEA-LETI, Grenoble in 2003, his research interests are in the field of molecular bonding of semiconductors materials.

References [1] D.A.B. Miller, Physical reasons for optical interconnection, Int. J. Optoelectron. 11 (1997) 155–168. [2] D.A.B. Miller, Optical interconnects to silicon, IEEE J. Select. Top. Quant. Electron. 6 (6) (2000). [3] I. O’Connor, F. Gaffiot, in: E. Macii (Ed.), On-Chip Optical Interconnect for Low-power in Ultra Low-Power Electronics and Design, Kluwer, 2004. [4] A.V. Krishnamoorthy, K.W. Goossen, Optoelectronic-VLSI: photonics integrated with VLSI circuits, IEEE J. Select. Top. Quant. Electron. 4 (6) (1998). [5] H. Takahara, Optoelectronic multichip module packaging technologies and optical input/output interface chip-level packages for the next generation of hardware systems, IEEE J. Select. Top. Quant. Electron. 9 (2) (2003) 443–451. [6] G. Roelkens, D. Van Thourhout, R. Baets, Ultra-thin benzocyclobutene bonding of III–V dies onto SOI substrate, Electron. Lett. 41 (9) (2005) 65–66. [7] I. Christiaens, G. Roelkens, K. De Mesel, D. Van Thourhout, R. Baets, Thin-film devices fabricated with benzocyclobutene adhesive wafer bonding, J. Lightwave Technol. 23 (2) (2005) 517–523. [8] H.C. Lin, K.L. Chang, G.W. Pickrell, K.C. Hsieh, K.Y. Cheng, Low temperature wafer bonding by spin on glass, J. Vac. Sci. Technol. B 20 (2) (2002) 752–754. [9] E. Jalaguier, B. Aspar, S. Pocas, J.F. Michaud, M. Zussy, A.M. Papon, M. Bruel, Transfer of 3 in. GaAs film on silicon substrate by proton implantation process, Electron. Lett. 34 (4) (1998) 408–409. [10] E. Jalaguier, L. Di Cioccio, M. Kostrzewa, M. Zussy, P. Perreau, S. Pocas, N. Kernevez, C. Seassal, P. Regreny, P. Rojo-Romeo, M.P. Besland, J.L. Leclercq, G. Grenet, G. Hollinger, O. Marty, J.M. Chatelanaz, X. Wallaert, III–V layers transfer onto silicon and applications, in: Proceedings of the ICAST 2004, Chamonix, France, 2004. [11] M. Kostrzewa, L. Di Cioccio, M. Zussy, J.C. Roussin, J.M. Fedeli, N. Kernevez, P. Regreny, Die-to-wafer molecular bonding for optical interconnects and packaging, in: Proceedings of the 15th European Microelectronics and Packaging Conference and Exhibition, Brugge, Belgium, 2005. [12] R. Stengl, T. Tan, U. Gosele, A model for the silicon wafer bonding process, Jpn. J. Appl. Phys. 28 (1989) 1735. [13] U. G¨osele, Y. Blum, G. K¨astner, P. Kopperschmidt, G. Kr¨auter, R. Scholz, A. Schumacher, St. Senz, Q.-Y. Tong, L.-J. Huang, Y.-L. Chao, T.H. Lee, Fundamental issues in wafer bonding, J. Vac. Sci. Technol. A17 (4) (1999). [14] M. Kostrzewa, P. Regreny, M.P. Besland, J.L. Leclercq, G. Grenet, P. Rojo-Romeo, G. Hollinger, E. Jalaguier, P. Perreau, H. Moriceau, O. Marty, High quality epitaxial growth on new InP/Si substrate, in: Proceedings of the IPRM 2003, Santa Barbara, USA, 2003.

L´ea Di Cioccio was born in Meaux, France. She received the degree in engineering from the INSA in Rennes, in 1985 and the same year succeeded the DEA in microelectronics and physico-chemistry of Paris VII. She received the degree of doctor es science in 1998 on “II–VI compounds (grown by MBE) TEM characterization”. She joined the CEA-LETI, Grenoble in 1989. She is in charge of the 3D and heterogeneous integration development as project leader. Her research interests are in the field of molecular bonding of semiconductors materials. Marc Zussy was born in Orange, France in 1968. He joined the CEA-LETI, Grenoble in 1992. He is in charge of the CMP and grinding application development for wafer bonding purpose. His research interests are in the field of Molecular Bonding of dissimilar materials. Jean-Claude Roussin was born in 1947 in France. He joined the CEALETI, Grenoble in 1974. He works in the field of molecular bonding and development of GaNOI substrates. Jean-Marc Fedeli received his electronics engineer diploma from INPG Grenoble in 1978. Then he developed at the CEA-LETI different magnetic memories and magnetic components as project leader, group leader, and program manager. In 2000, he joined Memscap Company in charge of the development of RF-MEMS. Since 2002, at the CEA-LETI, he is leading all the photonic on CMOS projects. Nelly Kernevez received her Engineer degree in 1981 and PhD degree in Physics in 1983 in Institut National Polytechnique de Grenoble. She joined CEA in 1984 as project leader of Nuclear MagneticResonance sensors development in partnership with French and US Navy, she managed the industrial transfer to Sextant Avionique. In 1994 she became in charge of Solidification Process Laboratory. Since 2002 she is the leader of the Film and Circuits Transfer Laboratory in LETI, managing the common laboratory with SOITEC, initiating innovative substrates development as GeOI, GaNOI. Philippe Regreny was born in France in 1967. He graduated in materials science from Rennes University. He received his PhD in electronics from Ecole centrale de lyon in 1997. He is now a research engineer at LEOM/CNRS, Ecole Centrale de Lyon, Ecully, France. His current research interests concern epitaxial growth of III–V semiconductor compounds and their integration on silicon. Chrystelle Lagahe-Blanchard graduated from INSA Toulouse in “Material Physics”. She received her PhD from INP Grenoble in “Genie des Mat´eriaux” in 2000. After 2 years at LETI as Research Engineer, she joined TRACIT as Development Engineer. Bernard Aspar is CEO of TRACIT Technologies. He graduated from ISIM Montpellier in “Material Science” and received his PhD from Languedoc University, Montpellier, France in 1991. He then joined CEA-LETI to work on SOI material development in collaboration with SOITEC. At LETI, he managed the laboratory on “transfer of thin films and circuits” specialized in layer transfer on various support (“from SOI material up to 3D devices”).