Du microprocesseur au microcontrôleur De l’ordinateur au système embarqué

Hervé BOEGLEN

Plan 1. Introduction 2. Technologie des SoC-FPGA 3. Technologie ARM 4. L’écosystème Arduino 5. Exemples

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1. Introduction Trois niveaux de performance SoC-FPGA

µP embarqué

µC

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1. Introduction Evolution de l’électronique depuis 1948

2011 : Intel Core I7 2600K, 32nm : Die : 216mm2 1,16 x 109 transistors !

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1. Introduction La loi de Moore

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1. Introduction La densité de puissance

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1. Introduction Les systèmes numériques aujourd’hui :

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1. Introduction La conception des systèmes numériques :

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1. Introduction Les cibles logicielles et matérielles : Les cibles logicielles (=µP, µC, DSP)

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1. Introduction Les µP :

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1. Introduction Les µC :

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1. Introduction Les µC :

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1. Introduction Les Digital Signal Processors (DSP) :

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1. Introduction Les Digital Signal Processors (DSP) :

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1. Introduction En résumé sur les cibles logicielles : • Avantages : – Flexibilité: il suffit de modifier le programme pour modifier l’application – Simple à mettre en œuvre grâce à la programmation de haut niveau (langage C) (possibilité de grande abstraction par rapport au matériel) – Temps de conception courts et coûts de conception faibles – Prix de revient faible

• Inconvénients : – Faibles performances (consommation de puissance, vitesse de fonctionnement, puissance de calcul, etc,) à cause d’une architecture séquentielle (une opération à la fois, ou quelques unes dans le cas superscalaire) et de trop nombreux accès à la mémoire (instructions + données) 15/119

1. Introduction  Les cibles matérielles spécialisées (ASIC) :

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1. Introduction  Les différentes cibles matérielles :

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1. Introduction  ASIC full custom :

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1. Introduction  ASIC standard cell :

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1. Introduction  ASIC gate array:

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1. Introduction  ASIC gate array:

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1. Introduction  Circuit configurable (ici FPGA) :

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1. Introduction  Le marché des FPGA : Xilinx

58%

31%

Altera

11%

All Others

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1. Introduction  ASIC vs FPGA:

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1. Introduction  De 1997 à 2005 : évolution des coûts

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1. Introduction  Temps de conception comparés :

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1. Introduction  Conclusion ASIC : • Avantages : – – – – –

Haute intégration, Hautes performances (vitesse, consommation), Coûts unitaires faibles en production de masse Personnalisation Sécurité industrielle

• Inconvénients : – – – – –

Prix du 1er exemplaire, Pas d’erreur possible Non-flexible High time to market Fabrication réservée aux spécialistes (fondeurs), 27/119

1. Introduction  Conclusion FPGA : • Avantages : – – – –

Possibilité de prototypage, Low time to market Adaptabilité aux évolutions futures (reconfiguration) Flexibilité

• Inconvénients : – Intégration limitée, – Moins performant qu’un ASIC – Prix unitaire élevé en production de masse

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1. Introduction  Mais les méthodes de conception évoluent car : • Toujours plus d’intégration (SoC) • Les FPGA sont de plus en plus performants et de moins en moins chers, • Les FPGA remplacent peu à peu les ASIC…

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2. Technologie des SoC-FPGA

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2. Technologie des SoC-FPGA What is an FPGA ?  Field Programmable Gate Array  Gate Array Two-dimensional array of logic gates Traditionally connected with customized metal Every logic circuit (customer) needs a custommanufactured chip

 Field Programmable Customized by programming after manufacture One FPGA can serve every customer

 FPGA: re-programmable hardware

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2. Technologie des SoC-FPGA Basic Internals of an FPGA Logic Element

Logic Element

Logic Element

Logic Element

Logic Element

Logic Element

Logic Element

Logic Element

Logic Element

Each logic element is programmed to to implement the desired function Programmable Connections

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2. Technologie des SoC-FPGA FPGA Logic Element  Look-Up Table (LUT) + register + extra … LUT A B

0 Out

0 0

0

1

SRAM Cell Out

0 1 A B

 FPGAs typically use 4-input or larger LUTs  Cyclone family (low cost): 4-inputs  Stratix II: Adaptive Logic Module implements 4 – 6 input LUTs efficiently 33/119  Virtex 5: 6 inputs

2. Technologie des SoC-FPGA Connecting the Logic y LE z f I/O Pads I/O Pad

x

FPGA

 Logic elements implement the pieces of the circuit  Now hook them up with the programmable routing

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2. Technologie des SoC-FPGA Programmable Routing  Programmable switches connect fixed metal wires  Choose pattern so any logic element can connect to any other In2 Logic Block SRAM cell

In1

Out

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2. Technologie des SoC-FPGA Modern, mid-size FPGA – 2S60 I/O Channels with External Memory Interface Circuitry

Adaptive Logic Modules

High-Speed I/O Channels with DPA

M512 Block

Digital Signal Processing (DSP) Blocks

M4K Block

M-RAM Blocks

High-Speed I/O Channels with Dynamic Phase Alignment (DPA) I/O Channels with External Memory Interface Circuitry

Phase-Locked Loops (PLL) 60,440 Equivalent Logic Elements 2,544,192 Memory Bits

90nm Stratix II 2S60

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2. Technologie des SoC-FPGA

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2. Technologie des SoC-FPGA

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2. Technologie des SoC-FPGA

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2. Technologie des SoC-FPGA FPGA-SoC SDR platform

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2. Technologie des SoC-FPGA

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2. Technologie des SoC-FPGA

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2. Technologie des SoC-FPGA

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2. Technologie des SoC-FPGA

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2. Technologie des SoC-FPGA

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2. Technologie des SoC-FPGA 400MHZ max mais traitement parallèle ! Exemple soit à réaliser : • Réalisation logicielle à 400MHz : 7 cycles machine = 17,5 ns

• Réalisation matérielle : temps de traversée des portes = 2 ns

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2. Technologie des SoC-FPGA Attention on travaille par défaut en virgule fixe !

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2. Technologie des SoC-FPGA Attention on travaille par défaut en virgule fixe !

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2. Technologie des SoC-FPGA Attention on travaille par défaut en virgule fixe !

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2. Technologie des SoC-FPGA Attention on travaille par défaut en virgule fixe !

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2. Technologie des SoC-FPGA Attention on travaille par défaut en virgule fixe !

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2. Technologie des SoC-FPGA Une multiplication coûte de la ressource

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2. Technologie des SoC-FPGA Techniques d’implémentation spécifiques Exemple : FIR

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2. Technologie des SoC-FPGA Techniques d’implémentation spécifiques Exemple : FIR

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2. Technologie des SoC-FPGA Techniques d’implémentation spécifiques Exemple : FIR

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2. Technologie des SoC-FPGA Software & Development Tools Quartus Prime  All Stratix, Arria & Cyclone Devices  APEX II, APEX 20K/E/C, Excalibur, & Mercury Devices  FLEX 10K/A/E, ACEX 1K, FLEX 6000 Devices  MAX II, MAX 7000S/AE/B, MAX 3000A Devices

Quartus Prime Lite Edition  Free Version  Not All Features & Devices Included • See www.altera.com for Feature Comparison 56/119

2. Technologie des SoC-FPGA

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2. Technologie des SoC-FPGA

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2. Technologie des SoC-FPGA

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2. Technologie des SoC-FPGA

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2. Technologie des SoC-FPGA

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2. Technologie des SoC-FPGA

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2. Technologie des SoC-FPGA

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2. Technologie des SoC-FPGA

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2. Technologie des SoC-FPGA

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2. Technologie des SoC-FPGA SoCKit

Specifications

FPGA Cyclone V SX SoC—5CSXFC6D6F31C8NES 119K LEs, 41509 ALMs 5140 M10K memory blocks 6 FPGA PLLs and 3 HPS PLLs 2 Hard Memory Controllers 3.125G Transceivers ARM®-based hard processor system (HPS) 800 MHz, A Dual-Core ARM Cortex™-A9 MPCore™ Processor 512 KB of shared L2 cache 64 KB of scratch RAM Multiport SDRAM controller with support for DDR2, DDR3, LPDDR1, and LPDDR2 8-channel direct memory access (DMA) controller Memory 1GB (2x256MBx16) DDR3 SDRAM on FPGA 1GB (2x256MBx16) DDR3 SDRAM on HPS 128MB QSPI Flash on HPS Micro SD Card Socket on HPS EPCQ256 Flash on FPGA IO USB 2.0 OTG (ULPI interface with micro USB type AB connector) USB to UART (micro USB type B connector) 10/100/1000 Ethernet VGA, LCD Audio Switches, buttons, LEDs G sensor (HPS) , Temp. sensor (FPGA) 66/119

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2. Technologie des SoC-FPGA DE1-SoC

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3. Technologie ARM La société 

ARM founded in November 1990

 Advanced RISC Machines



Company headquarters in Cambridge, UK

 Processor design centers in Cambridge, Austin, and Sophia Antipolis  Sales, support, and engineering offices all over the world



Best known for its range of RISC processor cores designs

 Other products – fabric IP, software tools, models, cell libraries - to help partners develop and ship ARM-based SoCs



ARM does not manufacture silicon



Over 30 billion ARM® technology based chips shipped to date 68/119

3. Technologie ARM  ~4 Billion ARM® Processors Each Year

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3. Technologie ARM  Communauté ARM

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3. Technologie ARM  Processeurs pour l’embarqué

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3. Technologie ARM  Processeurs pour applications

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3. Technologie ARM  Evolution de l’architecture v4 Halfword and signed halfword / byte support System mode Thumb instruction set (v4T)

v5 Improved interworking CLZ Saturated arithmetic DSP MAC instructions Extensions: Jazelle (5TEJ)

v6 SIMD Instructions Multi-processing v6 Memory architecture Unaligned data support Extensions: Thumb-2 (6T2) TrustZone® (6Z) Multicore (6K) Thumb only (6-M)

v7 Thumb-2 Architecture Profiles 7-A Applications 7-R - Realtime 7-M Microcontroller

 Note that implementations of the same architecture can be different  Cortex-A8 - architecture v7-A, with a 13-stage pipeline  Cortex-A9 - architecture v7-A, with an 8-stage pipeline

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3. Technologie ARM  Architecture ARMv7 : profils 

Application profile (ARMv7-A)

 Memory management support (MMU)  Highest performance at low power 

Influenced by multi-tasking OS system requirements

 TrustZone and Jazelle-RCT for a safe, extensible system  e.g. Cortex-A5, Cortex-A9



Real-time profile (ARMv7-R)

   



Protected memory (MPU) Low latency and predictability ‘real-time’ needs Evolutionary path for traditional embedded business e.g. Cortex-R4

Microcontroller profile (ARMv7-M, ARMv7E-M, ARMv6-M)

   

Lowest gate count entry point Deterministic and predictable behavior a key priority Deeply embedded use e.g. Cortex-M3

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3. Technologie ARM  Quelle est l’architecture de mon processeur ?

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3. Technologie ARM  Quelle est l’architecture de mon processeur ?

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3. Technologie ARM  Architecture ARMv7 : profils A et R 

Application profile (ARMv7-A)  Memory management support (MMU)  Highest performance at low power  Influenced by multi-tasking OS system requirements  e.g. Cortex-A5, Cortex-A8, Cortex-A9, Cortex-A15



Real-time profile (ARMv7-R)  Protected memory (MPU)  Low latency and predictability ‘real-time’ needs  Evolutionary path for traditional embedded business  e.g. Cortex-R4, Cortex-R5 77/119

3. Technologie ARM  Exemple Cortex-A9 

ARMv7-A Architecture

 Thumb-2, Thumb-2EE  TrustZone support



Variable-length Multi-issue pipeline

 Register renaming  Speculative data prefetching  Branch Prediction & Return Stack

  

64-bit AXI instruction and data interfaces TrustZone extensions L1 Data and Instruction caches

 16-64KB each  4-way set-associative

 Optional features:    

PTM instruction trace interface IEM power saving support Full Jazelle DBX support VFPv3-D16 Floating-Point Unit (FPU) or NEON™ media processing engine 78/119

3. Technologie ARM  Exemple Cortex-A15 (Samsung Galaxy S4)   

1-4 processors per cluster Fixed size L1 caches (32KB) Integrated L2 Cache

 512KB – 4MB



System-wide coherency support with AMBA 4 ACE



Backward-compatible with AXI3 interconnect Integrated Interrupt Controller



 0-224 external interrupts for entire cluster

 

CoreSight debug Advanced Power Management

 Large Physical Address Extensions (LPAE) to ARMv7-A Architecture  Virtualization Extensions to ARMv7-A Architecture

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3. Technologie ARM  Modèle de programmation 

ARM is a 32-bit load / store RISC architecture

 The only memory accesses allowed are loads and stores  Most internal registers are 32 bits wide  Most instructions execute in a single cycle



When used in relation to ARM cores

 Halfword means 16 bits (two bytes)  Word means 32 bits (four bytes)  Doubleword means 64 bits (eight bytes)



ARM cores implement two basic instruction sets

 ARM instruction set – instructions are all 32 bits long  Thumb instruction set – instructions are a mix of 16 and 32 bits 



Thumb-2 technology added many extra 32- and 16-bit instructions to the original 16bit Thumb instruction set

Depending on the core, may also implement other instruction sets

   

VFP instruction set – 32 bit (vector) floating point instructions NEON instruction set – 32 bit SIMD instructions Jazelle-DBX - provides acceleration for Java VMs (with additional software support) 80/119 Jazelle-RCT - provides support for interpreted languages

3. Technologie ARM  Modes du processeur 

ARM has seven basic operating modes

Exception modes

 Each mode has access to its own stack space and a different subset of registers  Some operations can only be carried out in a privileged mode Mode

Description

Supervisor (SVC)

Entered on reset and when a Supervisor call instruction (SVC) is executed

FIQ

Entered when a high priority (fast) interrupt is raised

IRQ

Entered when a normal priority interrupt is raised

Abort

Used to handle memory access violations

Undef

Used to handle undefined instructions

System

Privileged mode using the same registers as User mode

User

Mode under which most Applications / OS tasks run

Privileged modes

Unprivileged 81/119 mode

3. Technologie ARM  Les registres User mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc)

IRQ

FIQ

Undef

Abort

SVC

ARM has 37 registers, all 32-bits long A subset of these registers is accessible in each mode Note: System mode uses the User mode register set.

r13 (sp) r14 (lr)

r8 r9 r10 r11 r12 r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

spsr

spsr

spsr

spsr

spsr

cpsr

Current mode

Banked out registers

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3. Technologie ARM  Les bases du jeu d’instructions 

The ARM Architecture is a Load/Store architecture

 No direct manipulation of memory contents  Memory must be loaded into the CPU to be modified, then written back out



Cores are either in ARM state or Thumb state

 This determines which instruction set is being executed  An instruction must be executed to switch between states



The architecture allows programmers and compilation tools to reduce branching through the use of conditional execution

 Method differs between ARM and Thumb, but the principle is that most (ARM) or all (Thumb) instructions can be executed conditionally.

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3. Technologie ARM  Instruction de traitement de données 

These instructions operate on the contents of registers

 They DO NOT affect memory arithmetic ADC

manipulation

SUB

logical SBC RSB RSC

move

BIC

ORR

MVN

AND

EOR

MOV

(has destination register)

ADD

comparison

CMN

CMP

TST

TEQ

(set flags only)

(ADDS)

(SUBS)

(ANDS)

(EORS)

ORN



Syntax: {}{S} {Rd,} Rn, Operand2



Examples:

 ADD r0, r1, r2  TEQ r0, r1  MOV r0, r1

; r0 = r1 + r2 ; if r0 = r1, Z flag will be set ; copy r1 to r0

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3. Technologie ARM  Transfert de données en accès simple 

Use to move data between one or two registers and memory LDRD STRD Doubleword LDR STR Word LDRB LDRH LDRSB LDRSH

STRB STRH

Memory

Byte Halfword Signed byte load Signed halfword load Rd



31 Upper bits zero filled or sign extended on Load

0

Syntax:

 LDR{}{} Rd,  STR{}{} Rd,



Example:

 LDRB r0, [r1]

; load bottom byte of r0 from the ; byte of memory at address in r1

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3. Technologie ARM  Qu’est-ce que NEON ? 

NEON is a wide SIMD data processing architecture

 Extension of the ARM instruction set (v7-A)  32 x 64-bit wide registers (can also be used as 16 x 128-bit wide registers)



NEON instructions perform “Packed SIMD” processing

 Registers are considered as vectors of elements of the same data type  Data types available: signed/unsigned 8-bit, 16-bit, 32-bit, 64-bit, single prec. float  Instructions usually perform the same operation in all lanes Source Source Registers Registers Dn

Elements

Dm

Dd

Lane

Operation Destination Register 86/119

3. Technologie ARM  Processeurs Cortex MPCore 

Standard Cortex cores, with additional logic to support MPCore

 Available as 1-4 CPU variants



Include integrated

 Interrupt controller  Snoop Control Unit (SCU)  Timers and Watchdogs

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3. Technologie ARM  Architecture ARMv7 : profil M 

v7-M Cores are designed to support the microcontroller market

 Simpler to program – entire application can be programmed in C  Fewer features needed than in application processors



Register and ISA changes from other ARM cores

 No ARM instruction set support  Only one set of registers  xPSR has different bits than CPSR



Different modes and exception models

 Only two modes: Thread mode and Handler mode  Vector table is addresses, not instructions  Exceptions automatically save state (r0-r3, r12, lr, xPSR, pc) on the stack  Different system control/memory layout  Cores have a fixed memory map  No coprocessor 15 – controlled through memory mapped control registers

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3. Technologie ARM  Exemple Cortex M3  ARMv7-M Architecture  Thumb-2 only

 Fully programmable in C  3-stage pipeline  von Neumann architecture    

Optional MPU AHB-Lite bus interface Fixed memory map 1-240 interrupts  Configurable priority levels  Non-Maskable Interrupt support  Debug and Sleep control

 Serial wire or JTAG debug  Optional ETM 89/119

3. Technologie ARM  Jeu de registres R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12

R15 (PC)



Registers R0-R12

 General-purpose registers



R13 is the stack pointer (SP) - 2 banked versions



R14 is the link register (LR)



R15 is the program counter (PC)



PSR (Program Status Register)

 Not explicitly accessible  Saved to the stack on an exception  Subsets available as APSR, IPSR, and EPSR

PSR

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3. Technologie ARM  Organisation mémoire External Private Peripheral Bus E00F_FFFF E00F_F000

ROM Table FFFF_FFFF

UNUSED 512MB

E004_2000 E004_1000

System

ETM TPIU

(XN) E000_0000

E004_0000 1GB E003_FFFF

External Peripheral

RESERVED E000_F000 E000_E000

A000_0000

NVIC RESERVED

E000_3000 E000_2000 E000_1000 E000_0000

FPB DWT

1 GB

External SRAM

ITM

Internal Private Peripheral Bus

6000_0000 512MB

Peripheral 4000_0000

512MB

SRAM 2000_0000

512MB

Code

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3. Technologie ARM  ARM SoC ARM core deeply embedded within an SoC CoreSight interface



Design can have both external and internal memories

 Varying width, speed and size – depending on system requirements



Can include ARM licensed CoreLink peripherals

 Interrupt controller, since core only has 

 

two interrupt sources Other peripherals and interfaces

Can include on-chip memory from ARM Artisan Physical IP Libraries Elements connected using AMBA (Advanced Microcontroller Bus Architecture)

DMA Port

Clocks and Reset Controller

(XN) FLASH

ARM Processor core

AMBA AXI

 External debug and trace via JTAG or

DEBUG nIRQ nFIQ

CoreLink Interrupt Controller Other CoreLink Peripherals Custom Peripherals

External Memory Interface

SDRAM On chip memory

AMBA APB



APB Bridge

ARM based SoC

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3. Technologie ARM  ARM SoC : smartphone

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3. Technologie ARM  Exemple système AMBA (Advanced Microcontroller Bus Architecture)

APB (Advanced Peripheral Bus)

High Performance ARM processor High Bandwidth External Memory Interface

AHB (Advanced High performance Bus)

High-bandwidth on-chip RAM

UART Timer APB Bridge Keypad

DMA Bus Master

High Performance Pipelined Burst Support Multiple Bus Masters

PIO

Low Power Non-pipelined Simple Interface

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3. Technologie ARM  Outils de développement

Software Tools  DS-5

  



JTAG Debug and Trace Development Platforms  DSTREAM

 Fast Models  Versatile Platform baseboards



 Keil MCU development boards  Keil µVision simulator

Application Edition Linux Edition Professional Edition

MDK: Keil Microcontroller Development Kit

ULINK

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3. Technologie ARM  Outil DS-5 Professionnel 

Integrated solution, professionally supported and maintained

 End-to-end development, from SoC bring-up to application debug



Powerful ARM compiler

 Best code size and performance



Intuitive DS-5 debugger

 Flexible graphical user interface  DSTREAM probe with 4GB trace buffer

DS-5 Eclipse Compiler IDE

Streamline

Device Configuration Database Simulation



Debugger

Hardware Debug

Fast SoC simulation models

 Develop in a controlled environment  Examples and applications



Streamline performance analyzer

 System-wide analysis of Linux and Android systems

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3. Technologie ARM  Development Kits 

Low cost tools for ARM7, ARM9, Cortex-M and Cortex-R4 MCUs

 Extensive device support for many devices  Core and peripheral simulation  Flash support



Microcontroller Development Kit (MDK)

 IDE, optimized run-time library, KEIL RTX RTOS  ARM Compiler  Realtime trace (for Cortex-M3 and Cortex-M4 based devices)



Real-Time Library

 KEIL RTX RTOS + Source Code  TCP networking suit, Flash File System, CAN Driver Library, USB Device Interface

 

Debug Hardware Evaluation boards

 

Separate support channel See www.keil.com

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3. Technologie ARM  Exemple pour moins de 13$ :

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3. Technologie ARM  Exemple pour moins de 15€ : STM32F4 Discovery

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3. Technologie ARM  Le projet Raspberry PI

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3. Technologie ARM  Le projet Raspberry PI :

Raspberry PI Model B+

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3. Technologie ARM  Le projet Raspberry PI : caractéristiques RPI 3 :

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SoC Broadcom BCM2835 “High Definition Embedded Multimedia Application Processor.” Uses ARM1196JZF-S(ARM v6) J- Jazelle bytecode Z- Trust zone F- Floating point S-Synthesizable core. AMBA-3 improves memory bus performance.

OS -mainly linux based OS. Linux or Windows 10 IoT. Fedora , Archlinux & Debian . Most recommended Debian ,Because it supports python programming language.

OS and Programming language

Raspberry Pi Versions of Kernels are available Fedora-Pidora Debian-Raspbian

3. Technologie ARM  Démo Raspberry Pi Linux PIXEL

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4. L’écosystème Arduino  Arduino Uno :

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5. Exemples  Applications :

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5. Exemples  Applications :  SoC FPGA : TERASIC SPIDER

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5. Exemples  Applications :  SoC FPGA : TERASIC SPIDER

 Vidéo

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5. Exemples  Applications :  ARM Cortex M : Drone FPV 100% logiciel libre

FPV youtube Drone speed 111/119

5. Exemples  Applications :  ARM Cortex M : Drone

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5. Exemples  Applications :  Boucle de contrôle

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5. Exemples  Applications :  Carte contrôleur : SP Racing F3

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5. Exemples  Applications :  Propulsion : moteurs et contrôleurs brushless (flashés avec BLHELI)

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5. Exemples  Applications :  Retour vidéo

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5. Exemples  Applications :  Radiocommande : FRSKY Taranis OPENTX, X4R-SB et retour télémétrie

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5. Exemples  Applications :  Logiciels de configuration

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5. Exemples  Drone 250 FPV

Démo 119/119

TEST  Questions :  1. Quelles sont les différences entre un microprocesseur et un microcontrôleur  2. Qu’est-ce qu’un ASIC ?  3. Qu’est-ce qu’un FPGA ?  4. Qu’est-ce qu’un SoC ?  5. ARM est une société qui fabrique des microprocesseurs. Vrai ou Faux ?  6. On peut faire tourner un système d’exploitation comme Linux sur un ARM Cortex M. Vrai ou Faux ?  7. Le Raspberry Pi est un mini ordinateur qui utilise un ou plusieurs cœurs ARM. Vrai ou Faux ?  8. L’Arduino Uno est un système à microprocesseur. Vrai ou Faux ?  9. Dans l’écosystème Arduino qu’est-ce qu’un shield ?  10. Qu’est-ce qu’un serveur VNC ? 120/119