MC33078, MC33079 Low Noise Dual/Quad Operational Amplifiers The MC33078/9 series is a family of high quality monolithic amplifiers employing Bipolar technology with innovative high performance concepts for quality audio and data signal processing applications. This family incorporates the use of high frequency PNP input transistors to produce amplifiers exhibiting low input voltage noise with high gain bandwidth product and slew rate. The all NPN output stage exhibits no deadband crossover distortion, large output voltage swing, excellent phase and gain margins, low open loop high frequency output impedance and symmetrical source and sink AC frequency performance. The MC33078/9 family offers both dual and quad amplifier versions and is available in the plastic DIP and SOIC packages (P and D suffixes).
http://onsemi.com MARKING DIAGRAMS DUAL
MC33078P AWL YYWWG
PDIP−8 P SUFFIX CASE 626
8
1
1
Features
• • • • • • • • • • • •
8
Dual Supply Operation: $5.0 V to $18 V
8
Low Voltage Noise: 4.5 nV/ ǸHz Low Input Offset Voltage: 0.15 mV Low T.C. of Input Offset Voltage: 2.0 mV/°C Low Total Harmonic Distortion: 0.002% High Gain Bandwidth Product: 16 MHz High Slew Rate: 7.0 V/ms High Open Loop AC Gain: 800 @ 20 kHz Excellent Frequency Stability Large Output Voltage Swing: +14.1 V/ −14.6 V ESD Diodes Provided on the Inputs Pb−Free Packages are Available
8 1
14 PDIP−14 P SUFFIX CASE 646
14 1
14
R2 Q9
Q5
Neg
Pos
J1 Amplifier Biasing
D3
Q11
R7
C2 Q8
Q3 D4
Z1
Q1
R1
D2
C1
R3
R4 Q7
R6
MC33079DG AWLYWW 1
A WL, L YY, Y WW, W G or G
= Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package
C3 R9
Q6 Q2
SOIC−14 D SUFFIX CASE 751A
VCC
Q4
MC33079P AWLYYWWG
1
1
Q3
1
33078 ALYW G
QUAD
14
D1
SOIC−8 D SUFFIX CASE 751
Q10
Q12
Vout
ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet.
R5 VEE
Figure 1. Representative Schematic Diagram (Each Amplifier)
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 7
1
Publication Order Number: MC33078/D
MC33078, MC33079 PIN CONNECTIONS
Output 1
DUAL
QUAD
CASE 626/751
CASE 646/751A
1
8 VCC − 1 +
2 Inputs 1
VEE
3
7 Output 2 − 2 +
4
Output 1 Inputs 1
6
VCC
Inputs 2 5
Inputs 2
(Dual, Top View)
Output 2
1
14
2
13
*
1 3 )
* ) 12
4
4
11
5
) 10 3 * 9
)2 6 *
Output 4
7
8
Inputs 4 VEE Inputs 3 Output 3
(Quad, Top View)
MAXIMUM RATINGS Rating
Symbol
Value
Unit
VS
+36
V
VIDR
Note 1
V
Input Voltage Range
VIR
Note 1
V
Output Short Circuit Duration (Note 2)
tSC
Indefinite
sec
Supply Voltage (VCC to VEE) Input Differential Voltage Range
Maximum Junction Temperature
TJ
+150
°C
Storage Temperature
Tstg
− 60 to +150
°C
ESD Protection at any Pin MC33078 MC33079
− Human Body Model − Machine Model − Human Body Model − Machine Model
Vesd
600 200 550 150
V
Maximum Power Dissipation
PD
Note 2
mW
Operating Temperature Range
TA
−40 to +85
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Either or both input voltages must not exceed the magnitude of VCC or VEE. 2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 2).
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MC33078, MC33079 DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.) Characteristics
Symbol |VIO|
Input Offset Voltage (RS = 10 W, VCM = 0 V, VO = 0 V) (MC33078) TA = +25°C TA = −40° to +85°C (MC33079) TA = +25°C TA = −40° to +85°C Average Temperature Coefficient of Input Offset Voltage RS = 10 W, VCM = 0 V, VO = 0 V, TA = Tlow to Thigh
DVIO/DT
Input Bias Current (VCM = 0 V, VO = 0 V) TA = +25°C TA = −40° to +85°C
IIB
Input Offset Current (VCM = 0 V, VO = 0 V) TA = +25°C TA = −40° to +85°C
IIO
Common Mode Input Voltage Range (DVIO = 5.0 mV, VO = 0 V)
VICR
Large Signal Voltage Gain (VO = $10 V, RL = 2.0 kW) TA = +25°C TA = −40° to +85°C
AVOL
Min
Typ
Max
− − − −
0.15 − 0.15 −
2.0 3.0 2.5 3.5
−
2.0
−
− −
300 −
750 800
− −
25 −
150 175
±13
±14
−
90 85
110 −
− −
Unit mV
mV/°C nA
nA
V dB
Output Voltage Swing (VID = $1.0V) RL = 600 W RL = 600 W RL = 2.0 kW RL = 2.0 kW RL = 10 kW RL = 10 kW
VO + VO − VO + VO − VO + VO −
− − +13.2 − +13.5 −
+10.7 −11.9 +13.8 −13.7 +14.1 −14.6
− − − −13.2 − −14
V
Common Mode Rejection (Vin = ±13V)
CMR
80
100
−
dB
Power Supply Rejection (Note 3) VCC/VEE = +15 V/ −15 V to +5.0 V/ −5.0 V
PSR
80
105
−
dB
+15 −20
+29 −37
− −
− − − −
4.1 − 8.4 −
5.0 5.5 10 11
Output Short Circuit Current (VID = 1.0 V, Output to Ground) Source Sink
ISC
Power Supply Current (VO = 0 V, All Amplifiers) (MC33078) TA = +25°C (MC33078) TA = −40° to +85°C (MC33079) TA = +25°C (MC33079) TA = −40° to +85°C
ID
3. Measured with VCC and VEE differentially varied simultaneously.
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mA
mA
MC33078, MC33079 AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.) Characteristics
Symbol
Min
Typ
Max
Unit
SR
5.0
7.0
−
V/ms
GBW
10
16
−
MHz
Unity Gain Bandwidth (Open Loop)
BW
−
9.0
−
MHz
Gain Margin (RL = 2.0 kW) CL = 0 pF CL = 100 pF
Am
− −
−11 − 6.0
− −
Phase Margin (RL = 2.0 kW) CL = 0 pF CL = 100 pF
fm
− −
55 40
− −
Slew Rate (Vin = −10 V to +10 V, RL = 2.0 kW, CL = 100 pF AV = +1.0) Gain Bandwidth Product (f = 100 kHz)
Deg
CS
−
−120
−
dB
Power Bandwidth (VO = 27 Vpp, RL = 2.0 kW, THD $ 1.0%)
BWp
−
120
−
kHz
Total Harmonic Distortion (RL = 2.0 kW, f = 20 Hz to 20 kHz, VO = 3.0 Vrms, AV = +1.0)
THD
−
0.002
−
%
Open Loop Output Impedance (VO = 0 V, f = 9.0 MHz)
|ZO|
−
37
−
W
Differential Input Resistance (VCM = 0 V)
Rin
−
175
−
kW
Differential Input Capacitance (VCM = 0 V)
Cin
−
12
−
pF
Equivalent Input Noise Voltage (RS = 100 W, f = 1.0 kHz)
en
−
4.5
−
nV/ √ Hz
Equivalent Input Noise Current (f = 1.0 kHz)
in
−
0.5
−
P, D MAXIMUM POWER DISSIPATION (mW)
Channel Separation (f = 20 Hz to 20 kHz)
dB
2400 I, IB INPUT BIAS CURRENT (nA)
800
2000
MC33078P & MC33079P
1600 MC33079D
1200 800 MC33078D
400 0 −55 −40 −20
VCM = 0 V TA = 25°C 600
400
200
0
0 20 40 60 80 100 120 140 160 TA, AMBIENT TEMPERATURE (°C)
0
Figure 2. Maximum Power Dissipation versus Temperature
5.0
10 15 VCC, | VEE |, SUPPLY VOLTAGE (V)
20
Figure 3. Input Bias Current versus Supply Voltage
1000
2.0 VCC = +15 V VEE = −15 V VCM = 0 V
800
V, IO INPUT OFFSET VOLTAGE (mV)
I, IB INPUT BIAS CURRENT (nA)
Hz√pA/
600 400
200 0 −55
−25
0 25 50 75 TA, AMBIENT TEMPERATURE (°C)
100
VCC = +15 V VEE = −15 V RS = 10 W 1.0 VCM = 0 V AV = +1
Unit 2 0
Figure 4. Input Bias Current versus Temperature
Unit 3
−1.0
−2.0 −55
125
Unit 1
−25
0 25 50 75 TA, AMBIENT TEMPERATURE (°C)
100
125
Figure 5. Input Offset Voltage versus Temperature
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I, IB INPUT BIAS CURRENT (nA)
600 VCC = +15 V VEE = −15 V TA = 25°C
500 400 300 200 100 0 −15
−10
−5.0
0
5.0
10
15
VCM, COMMON MODE VOLTAGE (V)
V ICR , INPUT COMMON MODE VOLTAGE RANGE (V)
MC33078, MC33079 VCC −0 VCC −0.5
VCC −1.5 Voltage Range VEE +1.5 VEE +1.0
VEE +0 −55
VCC −5.0
125°C 125°C 25°C
VEE +5.0 VEE +3.0 VEE +1.0
−55°C 0
1.0
2.0
3.0
I, CC SUPPLY CURRENT (mA)
75
100
4.0
VCC = +15 V VEE = −15 V RL < 100 W VID = 1.0 V
Sink 40 Source
30
20
10 −55
Figure 9. Output Short Circuit Current versus Temperature
±15 V
VCM = 0 V RL = ∞ VO = 0 V
±10 V
±5.0 V
7.0 6.0
MC33079
5.0
±15 V
4.0
±10 V
MC33078
±5.0 V ±4.0 V
−25
Supply Voltages
0 25 50 75 TA, AMBIENT TEMPERATURE (°C)
100
125
50
Figure 8. Output Saturation Voltage versus Load Resistance to Ground
8.0
0 −55
50
0 25 50 75 TA, AMBIENT TEMPERATURE (°C)
9.0
2.0 1.0
25
RL, LOAD RESISTANCE TO GROUND (kW)
10
3.0
0
Figure 7. Input Common Mode Voltage Range versus Temperature
VCC = +15 V VEE = −15 V
25°C
−25
TA, AMBIENT TEMPERATURE (°C)
| I|, SC OUTPUT SHORT CIRCUIT CURRENT (mA)
VCC −3.0
−VCM
VEE +0.5
CMR, COMMON MODE REJECTION (dB)
Vsat , OUTPUT SATURATION VOLTAGE (V)
−55°C
VCC = +3.0 V to +15 V VEE = −3.0 V to −15 V DVIO = 5.0 mV VO = 0 V
VCC −1.0
Figure 6. Input Bias Current versus Common Mode Voltage
VCC −1.0
+VCM
100
D VCM
140 120
CMR = 20Log
100 80 60 40
Figure 10. Supply Current versus Temperature
− ADM + D VCM D VO
D VO × ADM
VCC = +15 V VEE = −15 V VCM = 0 V DVCM = ±1.5 V TA = 25°C 1.0 k
10 k 100 k f, FREQUENCY (Hz)
1.0 M
Figure 11. Common Mode Rejection versus Frequency
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125
160
20 100
125
−25
10 M
140
DVO/ADM
+PSR = 20Log
120
DVCC
DVO/ADM
−PSR = 20Log
DVCC DVCC
+PSR
100
GWB, GAIN BANDWIDTH PRODUCT (MHz)
PSR, POWER SUPPLY REJECTION (dB)
MC33078, MC33079
−
ADM
DVO
+
80
−PSR
VEE
60 40 VCC = +15 V VEE = −15 V TA = 25°C
20
0 100
1.0 k
10 k 100 k f, FREQUENCY (Hz)
30
20
10
0
10 M
1.0 M
RL = 10 kW CL = 0 pF f = 100 kHz TA = 25°C
0
20
20
20 TA = 25°C
15 VO , OUTPUT VOLTAGE (Vp)
GWB, GAIN BANDWIDTH PRODUCT (MHz)
15
Figure 13. Gain Bandwidth Product versus Supply Voltage
15
10 VCC = +15 V VEE = −15 V f = 100 kHz RL = 10 kW CL = 0 pF
5.0
0 −55
−25
0 25 50 75 TA, AMBIENT TEMPERATURE (°C)
RL = 10 kW RL = 2.0 kW
5.0 0 −5.0
RL = 2.0 kW
−10 RL = 10 kW
−15 100
−20
125
VO − 0
A, VOL OPEN LOOP VOLTAGE GAIN (dB)
30 25 20 VCC = +15 V VCC = −15 V RL = 2.0 kW AV = +1.0 THD ≤ 1.0% TA = 25°C
10 5.0 10
100
1.0 k 10 k 100 k f, FREQUENCY (Hz)
1.0 M
5.0 10 15 VCC |VEE| , SUPPLY VOLTAGE (V)
20
Figure 15. Maximum Output Voltage versus Supply Voltage
35
15
VO +
10
Figure 14. Gain Bandwidth Product versus Temperature
VO , OUTPUT VOLTAGE (Vpp )
10
VCC |VEE| , SUPPLY VOLTAGE (V)
Figure 12. Power Supply Rejection versus Frequency
0
5.0
110
100
90
80
10 M
RL = 2.0 kW f ≤ 10 Hz DVO = 2/3 (VCC −VEE) TA = 25°C
0
Figure 16. Output Voltage versus Frequency
5.0 10 15 VCC |VEE| , SUPPLY VOLTAGE (V)
Figure 17. Open Loop Voltage Gain versus Supply Voltage
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20
110
50
105
| Z|, Ω O OUTPUT IMPEDANCE ()
VCC = +15 V VEE = −15 V RL = 2.0 kW f ≤ 10 Hz DVO = −10 V to +10 V
100
95
90 −55
−25
0
25
50
75
CS, CHANNEL SEPARATION (dB)
20 10
AV = 1000
125
AV = 10
100 k
Figure 19. Output Impedance versus Frequency
Drive Channel VCC = +15 V VEE = −15 V RL = 2.0 KW DVOD = 20 Vpp TA = 25°C
150 140
MC33079 100 W
10 kW −
120
VOM
+ 100 W
DVOA
CS = 20 Log
DVOM
100 10
100
1.0 k f, FREQUENCY (Hz)
10 k
VCC = +15 V VEE = −15 V VO = 1.0 Vrms TA = 25°C
0.1
VO
+
2.0 kW
0.001
100 k
10
100
1.0 k f, FREQUENCY (Hz)
10 k
100 k
Figure 21. Total Harmonic Distortion versus Frequency
10
SR, SLEW RATE (V/μ s)
AV = 100 RA
0.05
Vin
Vin = 2/3 (VCC −VEE) TA = 25°C
9.0
AV = 1000
0.1
− +
10 kW VO 2.0 kW
AV = 10 AV = 1.0
0.005
−
0.01
1.0
0.01
10 M
1.0
Figure 20. Channel Separation versus Frequency
VCC = +15 V VEE = −15 V 0.5 f = 2.0 kHz TA = 25°C
AV = 1.0
1.0 M
Figure 18. Open Loop Voltage Gain versus Temperature
Measurement Channel
THD, TOTAL HARMONIC DISTORTION (%)
10 k
AV = 100
f, FREQUENCY (Hz)
MC33078
110
30
TA, AMBIENT TEMPERATURE (°C)
160
130
100
VCC = +15 V VEE = −15 V VO = 0 V TA = 25°C
40
0 1.0 k
THD, TOTAL HARMONIC DISTORTION (%)
A, VOL OPEN LOOP VOLTAGE GAIN (dB)
MC33078, MC33079
Falling
8.0 7.0
Rising
6.0 5.0 4.0
−
3.0
DVin
2.0
+
VO 2.0 kW
1.0 0.001
0
1.0
2.0
3.0 4.0 5.0 6.0 7.0 VO, OUTPUT VOLTAGE (Vrms)
8.0
0
9.0
4
Figure 22. Total Harmonic Distortion versus Output Voltage
6
8 10 12 14 16 VCC |VEE| , SUPPLY VOLTAGE (V)
18
Figure 23. Slew Rate versus Supply Voltage
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20
VCC = +15 V VEE = −15 V DVin = 20 V
8.0
Falling Rising 6.0 − DVin
4.0
2.0 −55
−25
VO
+
2.0 kW
0 25 50 75 TA, AMBIENT TEMPERATURE (°C)
100
120 100 80
40 135 20
Phase
25°C
20
−55°C
8.0
30 125°C
125°C
6.0
40
4.0
50 VCC = +15 V VEE = −15 V VO = 0 V
0
e, nV/ √ Hz n INPUT REFERRED NOISE VOLTAGE ()
1
25°C
−55°C
60
1.0 M
10
DVin
125°C VO
+
25°C
CL
−55 °C
60 40 VCC = +15 V VEE = −15 V DVin = 100 mV
0 10
70 1000
100
100
1.0 k
10 k
CL, OUTPUT LOAD CAPACITANCE (pF)
CL, OUTPUT LOAD CAPACITANCE (pF)
Figure 26. Open Loop Gain Margin and Phase Margin versus Load Capacitance
Figure 27. Overshoot versus Output Load Capacitance
10 VCC = +15 V VEE = −15 V TA = 25°C
50 30 20
10 8.0 5.0
Voltage
3.0 2.0
Current
1.0 100
180 10 M
Gain
100 80
10
1.0 k 10 k 100 k f, FREQUENCY (Hz)
20
1.0 k
10 k
0.1 100 k
Vn, REFERRED NOISE VOLTAGE nV/ ( √ Hz)
2.0
100
−
80 os, OVERSHOOT (%)
CL
10
10
φ m, PHASE MARGIN (DEGREES)
VO
+ 2.0 kW
10
100
in, INPUT REFERRED NOISE CURRENT ( pA/ √ Hz )
A, m OPEN LOOP GAIN MARGIN (dB)
12 Vin
90
Figure 25. Voltage Gain and Phase versus Frequency
0 −
Phase Gain
Figure 24. Slew Rate versus Temperature
14
45
60
0 1.0
125
0 VCC = +15 V VEE = −15 V RL = 2.0 kW TA = 25°C
φ, EXCESS PHASE (DEGREES)
SR, SLEW RATE (V/s) μ
10
A, VOL OPEN LOOP VOLTAGE GAIN (dB)
MC33078, MC33079
1000
100
VCC = +15 V VEE = −15 V f = 1.0 kHz TA = 25°C Vn(total) = Ǹ(inRs)2 ) en2 ) 4KTRS
10
1.0 10
100
1.0 k
10 k
100 k
1.0 M
f, FREQUENCY (Hz)
RS, SOURCE RESISTANCE (W)
Figure 28. Input Referred Noise Voltage and Current versus Frequency
Figure 29. Total Input Referred Noise Voltage versus Source Resistance
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MC33078, MC33079 14
Am, GAIN MARGIN (dB)
12 R1
8.0 6.0 4.0 2.0 0
60
Gain
10
R2
50
Phase − +
φ m , PHASE MARGIN (DEGREES)
70
40
VO
30
VCC = +15 V VEE = −15 V RT = R1 +R2 AV = +100 VO = 0 V TA = 25°C
20 10 10
100
1.0 k
10 k
0 100 k
RT, DIFFERENTIAL SOURCE RESISTANCE (W)
V, O OUTPUT VOLTAGE (5.0 V/DIV)
V, O OUTPUT VOLTAGE (5.0 V/DIV)
Figure 30. Phase Margin and Gain Margin versus Differential Source Resistance
VCC = +15 V VEE = −15 V AV = −1.0 RL = 2.0 kW CL = 100 pF TA = 25°C
t, TIME (2.0 ms/DIV)
t, TIME (2.0 ms/DIV)
Figure 32. Non−inverting Amplifier Slew Rate
e, n INPUT NOISE VOLTAGE (100 nV/DIV)
Figure 31. Inverting Amplifier Slew Rate
V, O OUTPUT VOLTAGE (5.0 V/DIV)
VCC = +15 V VEE = −15 V AV = +1.0 RL = 2.0 kW CL = 100 pF TA = 25°C
VCC = +15 V VEE = −15 V RL = 2.0 kW CL = 100 pF AV = +1.0 TA = 25°C
t, TIME (200 ms/DIV)
VCC = +15 V VEE = −15 V BW = 0.1 Hz to 10 Hz TA = 25°C
t, TIME (1.0 sec/DIV)
Figure 33. Non−inverting Amplifier Overshoot
Figure 34. Low Frequency Noise Voltage versus Time
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MC33078, MC33079 0.1 mF
10 W
100 kW − 2.0 kW
+
D.U.T. +
1/2
4.7 mF
4.3 kW
MC33078 − 100 kW
Voltage Gain = 50,000
22 mF Scope ×1 Rin = 1.0 MW
2.2 mF 110 kW
24.3 kW 0.1 mF
Note: All capacitors are non−polarized.
Figure 35. Voltage Noise Test Circuit (0.1 Hz to 10 Hzp−p)
ORDERING INFORMATION Device MC33078D
Package SOIC−8
MC33078DG
SOIC−8 (Pb−Free)
MC33078DR2
SOIC−8
MC33078DR2G MC33078P
Shipping †
SOIC−8 (Pb−Free)
98 Units / Rail
2500 / Tape & Reel
PDIP−8
MC33078PG
PDIP−8 (Pb−Free)
MC33079D
SOIC−14
MC33079DG
SOIC−14 (Pb−Free)
MC33079DR2
SOIC−14
MC33079DR2G
SOIC−14 (Pb−Free)
MC33079P
PDIP−14
MC33079PG
PDIP−14 (Pb−Free)
50 Units / Rail
55 Units / Rail
2500 / Tape & Reel
25 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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MC33078, MC33079 PACKAGE DIMENSIONS PDIP−8 P SUFFIX CASE 626−05 ISSUE L
8
NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
5
−B− 1
4
F −A−
NOTE 2
L
C J
−T−
N
SEATING PLANE
D H
M
K
G 0.13 (0.005)
M
T A
M
B
M
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DIM A B C D F G H J K L M N
MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC −−− 10_ 0.76 1.01
INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC −−− 10_ 0.030 0.040
MC33078, MC33079 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AH
−X−
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07.
A 8
5
S
B 1
0.25 (0.010)
M
Y
M
4
−Y−
K
G C
N
DIM A B C D G H J K M N S
X 45 _
SEATING PLANE
−Z−
0.10 (0.004) H
D 0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050 SCALE 6:1
mm Ǔ ǒinches
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8 _ 0.25 0.50 5.80 6.20
INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244
MC33078, MC33079 PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE P
14
8
1
7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
B
A F
L
N
C
−T− SEATING PLANE
H
G
D 14 PL
J
K
0.13 (0.005)
M M
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DIM A B C D F G H J K L M N
INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 −−− 10 _ 0.015 0.039
MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 −−− 10 _ 0.38 1.01
MC33078, MC33079 SOIC−14 CASE 751A−03 ISSUE H
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
−A− 14
8
−B−
P 7 PL 0.25 (0.010)
M
7
1
G
−T− D 14 PL 0.25 (0.010)
T B
S
A
DIM A B C D F G J K M P R
J
M
K M
F
R X 45 _
C
SEATING PLANE
B
M
S
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
SOLDERING FOOTPRINT* 7X
7.04
14X
1.52 1 14X
0.58
1.27 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MC33078/D