C unless otherwise specified

ANALOG PERIPHERALS. 10-bit, 100 ... Pipelined Instruction Architecture; Executes 70% of Instructions in ... DIGITAL PERIPHERALS .... A/D CONVERTER.
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C8051F017

Mixed-Signal 32KB ISP FLASH MCU PRELIMINARY

ANALOG PERIPHERALS 10-bit, 100 KSPS ADC ±1LSB INL No Missing Codes Programmable Throughput up to 100ksps 4 External Inputs; Programmable as Single-Ended or Differential Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5 Data Dependent Windowed Interrupt Generator Built-in Temperature Sensor (± 3°C) Two 12-bit DACs Voltage Output 10usec Settling Time Comparator 16 Programmable Hysteresis Values Configurable to Generate Interrupts or Reset Reference 2.4V; 15 ppm/°C External Reference Input VDD Monitor and Brown-out Detector ON-CHIP JTAG EMULATION On-Chip Emulation Circuitry Facilitates Full Speed, NonIntrusive In-Circuit Emulation Supports Breakpoints, Single Stepping, Watchpoints Inspect/Modify Memory and Registers Superior Performance to Emulation Systems Using ICE-Chips, Target Pods, and Sockets Fully Compliant with IEEE 1149.1 Specification $99 Emulation Kit (C8051F015DK)

8051-COMPATIBLE µC Core Pipelined Instruction Architecture; Executes 70% of Instructions in 1 or 2 System Clocks Up to 25MIPS Throughput with 25MHz Clock Expanded Interrupt Handler; Up to 22 Interrupt Sources MEMORY 2304 Bytes Data RAM 32k Bytes FLASH; In-System Programmable in 512 byte Sectors DIGITAL PERIPHERALS 8 Port I/O; All are 5V tolerant TM TM TM Hardware I2C /SMBus , SPI , and UART Serial Ports Available Concurrently 16-bit Programmable Counter/Timer Array with 5 Capture/Compare Modules (Each Configurable as an 8-Bit PWM) 4 General Purpose 16-bit Counter/Timers Dedicated Watch-Dog Timer; Bi-directional Reset CLOCK SOURCES Internal Programmable Oscillator: 2-to-16MHz External Oscillator: Crystal, RC,C, or Clock Can Switch Between Clock Sources on-the-fly; Useful in Power Saving Modes SUPPLY VOLTAGE ...................................................... 2.7V to 3.6V Typical Operating Current: 12mA @ 25MHz Multiple Power Saving Sleep and Shutdown Modes 32-Pin LQFP Package Temperature Range: –40°C to +85°C I2C is a trademark of Philips Semi.; SMBus is a trademark of Intel Corp.; SPI is a trademark of Motorola, Inc.

Port I/O Config. VDD VDD DGND DGND

AV+ AV+ AGND AGND

Digital Power

UART SMBus SPI Bus

Analog Power

PCA Timer 0 Timer 1

TCK TMS TDI TDO

JTAG Logic

Boundry Scan Emulation HW Reset

/RST

VDD Monitor, WDT XTAL1 XTAL2

External Oscillator Circuit Internal Oscillator

System Clock

8 0 5 1

32kbyte FLASH

Timer 2 Timer 3

256 byte SRAM 2048 byte XRAM

C SFR Bus o r e

Port 0 Latch Port 1 Latch Port 2 Latch

P 0

C R O S S B A R

D r v P 1 D r v

S W I T C H

P 2 D r v

Crossbar Config.

P 3

Port 3 Latch

D r v

Analog Config. & Control Clock & Reset Configuration

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7

ADC 100ksps (10-Bit)

Prog Gain

A M U X

AIN0 AIN1 AIN2 AIN3

TEMP

VREF

VREF

DAC0 (12-Bit)

DAC0

DAC1 (12-Bit)

DAC1

CP0

CP0+ CP0-

CP1

12.20.2000

C8051F017

Mixed-Signal 32KB ISP FLASH MCU PRELIMINARY

SELECTED ELECTRICAL SPECIFICATIONS TA = -40°C to +85°C unless otherwise specified. PARAMETER CONDITIONS MIN GLOBAL CHARACTERISTICS Analog Supply Voltage 2.7 Analog Supply Current Internal REF, ADC, DAC, Comparators all active Analog Supply Current with Internal REF, ADC, DAC, Comparators all analog sub-systems inactive disabled Digital Supply Voltage 2.7 Digital Supply Current with Clock=25MHz CPU active Clock=1MHz Clock=32kHz Digital Supply Current Oscillator not running (shutdown mode) VDD Data Retention Voltage RAM remains valid CPU & DIGITAL I/O Clock Frequency Range DC Port Output High Voltage IOH = -3mA, Port I/O push-pull VDD – 0.7 Port Output Low Voltage IOL = 8.5mA Input High Voltage 0.8 x VDD Input Low Voltage SMBus SCL Frequency SYSCLK = MCU system clock SPI Bus Clock Frequency SYSCLK = MCU system clock A/D CONVERTER Resolution 10 Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Throughput Rate Input Voltage Range 0 D/A CONVERTERS Resolution 12 Integral Nonlinearity Specified from Data Word 014h to FEBh Differential Nonlinearity Guaranteed Monotonic Offset Error Data Word = 014h Output Settling Time To ½ LSB of full-scale Output Voltage Swing 0 COMPARATOR Supply Current Response Time | CP+ – CP- | = 100mV Input Voltage Range -0.25 Input Bias Current -5 Input Offset Voltage -10 PACKAGE INFORMATION D MIN NOM MAX (mm) (mm) (mm) A

-

A1 0.05

E1 E

32

1

A b

A1 e

-

1.60

-

0.15

A2 1.35 1.40 1.45 b

A2

MAX

UNITS

3.6 0.8

V mA

5

µA

12 0.5 20 2

3.6

V mA mA µA µA

1.5

V 25

0.2 x VDD SYSCLK/8 SYSCLK/2

MHz V V V V MHz MHz

±1 ±1 100 VREF

bits LSB LSB ksps V

0.6

VREF- 1LSB

bits LSB LSB LSB µs V

(AV+) +0.25 +5 +10

µA µs V nA mV

±4 ±1 ±3 10

1.5 4 0.001

C8051F015DK DEVELOPMENT KIT ($99)

D1

PIN 1 IDENTIFIER

TYP

0.30 0.37 0.45

D

-

9.00

-

D1

-

7.00

-

e

-

0.80

-

E

-

9.00

-

E1

-

7.00

-