Agilent Compliance and Validation Solution for DDR 1, 2 and 3 with Infiniium Series Oscilloscope
Pascal GRISON Application Engineer Agilent Restricted
Page 1
Introduction to Double Data Rate (DDR) DDR DRAM is often referred to as DDR. DDR means Double-Data Rate and DRAM means Dynamic Random Access Memory [DRAM]. The advantages of DDR over its predecessor Single Data Rate (SDR) – Data transfer on both rising and falling clock edge, effectively doubling the data transfer bandwidth – Lower power consumptions with lower voltage swing DDR is by far the most popular memory technology used in the computing segment, used extensively in PC, servers, workstations etc. With the maturing of DDR manufacturing process, the cost has been driven down significant in recent years. DDR is also a common memory choice for embedded designs, consumer electronics, automobile and other system designs.
Page 2
Comparison for DDR 1, 2, 3 Specification DDR1
Operating Voltage Clock Frequency Data Transfer Rate Pin Count Package Backward Compatibility
1.8 – 3.3 V 100 – 200 MHz 200 – 400 MT/s 184 TSOP/BGA No
DDR2
1.8 V 200 – 400 MHz 400 – 800 MT/s 240 BGA No
DDR3
1.5 V 400 – 800 MHz 800 – 1600 MT/s 240 BGA No
Page 3
About DDR DRAM memory Memory Speed Roadmap
SDR Clock Synchronous •
DDR4 3.2 GT/s DDR3 1.6 GT/s
2008+
DDR 400 MT/s
DDR Double Data Rate, Differential Clock, Data Strobe (DQS), Delayed Locked Loop •
2010+
DDR2 800 MT/s
DDR2 On-Die Termination (ODT), Off-Chip Driver (OCD), Differential DQS •
2005 SDR 100 MT/s
Key New Technologies
2002
DDR3 Point-to-Point Data, Fly-by Addr/Cmd, Self-calibrated driver impedance and ODT •
2000
Impact on Design and Validation Clock Speeds reaching 1GHz Parallel buses reaching the speeds of serial technology Tighter timing margins require calibration and bus training for DRAM, controller, and analyzer capture Crosstalk, impedance, EMI, and jitter issues Noise susceptibility Probe load effects are critical
Benefits of good signal integrity Guarantees interoperability with different vendors Improved device performance More design margin
Page 4
DDR Specification defined by JEDEC DDR SDRAM Chip Specification
D D R 3 - 1 6 0 0 DDR Technology Designation
DDR Technology Generation
Data Transfer Rate (MT/s) Clock Rate is ½ Data Transfer Rate = 800 MHz
DDR DIMM Specification
P C 3 - 12800 DDR used in PC Designation
DDR Technology Generation
Memory Bandwidth (MB/s) Clock Rate (800) x 8 = 6400 MB/s
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Bandwidth Requirements for Key Memory Technologies Memory App
Signal Rate
Fundamental Freq
DDR1 DDR2 DDR3 DDR4 GDDR2 GDDR3 GDDR4 GDDR5
Up to 400MT/s Up to 800MT/s Up to 1.6GT/s Up to 3.2GT/s Up to 1.2GT/s Up to 1.8GT/s Up to 2.8GT/s Up to 5.6GT/s
200MHz 400MHz 800MHz 1600MHz 600MHz 900MHz 1400MHz 2800MHz
Rise Time Calculated Fastest Real Signal Tr/Tf Tr/Tf in JEDEC spec 500ps (10-90%) 800ps (10-90%) 288ps (10-90%) 350ps (10-90%) 120ps (10-90%) 180ps (10-90%) 90ps (10-90%) 70ps (10-90%) 120ps (10-90%) 250ps (10-90%) 70ps (10-90%) 130ps (10-90%) 45ps (10-90%) 70ps (10-90%) 50ps (10-90%) 30ps (10-90%)
Optimum Bandwidth
Most likely Material
600MHz 2GHz 4GHz 8GHz 3GHz 5GHz 9GHz 13GHz
FR4 FR4 FR4 FR4 FR4 FR4 FR4 FR4
JEDEC specifications do not specify the rise time and fall time specification for DDR and GDDR signals. The required oscilloscope bandwidth for characterization and validation is also not mentioned. Thus, it is advisable to determine the fastest rise time and fall time of your devices before to determine the required oscilloscope bandwidth. Although the calculated fastest rise and fall time might look aggressive for the silicon, actually real performance is much slower. This is due to the cheaper FR4 materials and connectors used in real product design and manufacturing. They are lower bandwidth and filter high frequency components. Page 6
Agilent’s JEDEC Participation From www.jedec.org member list Agilent participates actively in JEDEC working group. Perry Keller (Agilent) is the Chairperson for JEDEC validation and verification task group. He chairs the newly created JC-40.5 subcommittee on memory validation and test as well as the FBD Validation Task Group. The committee has the power to standardize test procedures and fixtures for all memory test. This committee overlooks the task groups on DDR3 Register Validation and Clock Reference boards, as well as DDR3 clock and jitter measurement procedures.
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DDR Challenges Engineers Starting up new DDR Designs will be facing several difficulties Design: Proper PCB Layout Transmission lines Impedance control Test for JEDEC Physical Layer Validation: 1)Electrical Access for non intrusive high bandwidth probing 2)Electrical, Timing, Clock Jitter Margins Analysis 3)Read/Write Eye Diagrams 4)DDR Complete JEDEC Physical Layer Validation
DDR Difficulty 1: Electrical Access for non intrusive high bandwidth probing Tx
Connector
Rx
PCI-Express, SATA, FB-DIMM
Rx
Serial Protocol Probing
Tx
Compliance to the standards is at the interface of the connector.
DDR 1, 2, 3
Memory Controller
DRAM
Clock (CLK) Strobe (DQS)
DDR Probing
Clock (CLK) Strobe (DQS)
Compliance is measured at the balls of the DRAM where JEDEC standard is defined. Keypoint is how can get electrical access to signals that connects though BGA Balls?
Data (DQ)
8 lines
Data (DQ)
Control
6 lines
Control
1)
Plan for Test ->Vias on Backside of PCB
Address
12 lines
Address
2)
Use DDR2/DDR3 BGA Interposers
Your DDR waveform can be distorted with a long probe accessory. It is desirable to use a probe with accessories specified at the end of the probe. All Agilent Probe Heads and Accessories are Specified.
DDR Difficulty 2: Timing (Jitter)
Timing margin
As DDR transfer rate becomes faster, timing margin becomes smaller. Jitter, especially clock jitter is extremely critical for interoperability.
There a lot of clock jitter spec in JEDEC. That means how important is clock jitter in DDR. This is a new technical challenge.
DDR Difficulty 3 : Read and Write Timing Strobe (DQS) Read Data (DQ) Write
Read and Write DDR Data (DQ) signals have a different timing compared to the Data Strobe (DQS). DQS and DQ edges are aligned for Read signals.DQS edge is 90deg phase shifted from the DQ edge for Write signals. And since the DQS and DQ are on the same bus, if you simply trigger on the DQS edge, you will get nested eye patterns. You can easily understand that it will be tough to make your validation with such eyes.
Read and Write separation is necessary to validate DDR signals with an oscilloscope.
4) DDR JEDEC Physical Layer Validation There is an addendum from Intel and Jedec, in which Electrical, Timing and Clock Jitter specifications are mentioned.
How Agilent Will Help You Solve these Challenges
Probing Solutions
Probing is an important consideration for DDR measurement. Since the JEDEC is specified at the balls of the DRAM BGA package, getting a good measurement can be a challenge. Many designs have vias or designed-in probe points but they do not always produce good signal integrity. Probing at the wrong locations could cause a lot of reflection or non-monotonic edges. The load of your probing system is also another important consideration. It can affect the signals on your system as well as what you measure.
Scope Probing These two screenshots are the same DDR2 400 waveform with the same oscilloscope. Only the probes used are different.
500MHz Passive Probe
1.5GHz Active Probe
The left one is not a good waveform with a big ISI. This is due to a difference in load capacity, 10pF for the passive probe, and only 0.1pF for the active probe (Agilent Infiniimax). It does not mean that active probe is always good. If you use a wrong accessory, such a long lead, your waveform can be distorted as the left one.
Your DDR waveform can be distorted with a long probe accessory. It is desirable to use a probe with accessories specified at the end of the probe. All Agilent Probe Heads and Accessories are Specified.
7GHz BW →1.2GHz BW
InfiniiMax Probe System for DDR I, II & III Analysis N5382A 12GHz differential browser probe head E2675A 5GHz differential browser probe head E2676A 6GHz single end browser probe head E2679A 6GHz single-end solder-in probe head E2678A 12GHz differential socket probe head
N5381A 12GHz differential solder-in probe head N2677A 12GHz differential solder-in probe head N5425/26A 12GHZ differential ZIF probe head
InfiniiMax combines high usability with unmatched performance. It is the only full bandwidth, full use model probing system on the market. Page 16
Introducing World’s First W2630A Series DDR2 and DDR3 BGA Probe Adapters DDR2 BGA Probe Adapter for Scope and Logic Analyzer
DDR3 BGA Probe Adapter for Scope
Key Features and Benefits: Easiest way to access your DDR signals Superior signal integrity probing for most accuracy in measurement Compatible with scope and logic analyzer probes
W2631-34A
W2635-36A
Price: $1,999 (for a kit of 4 probes)
Price: $1,500 (for a kit of 10 probes)
Lead Time: 4 weeks (estimate)
Lead Time: 3 weeks Page 17
Key Feature: BGA Probe Adapters Compatible with parametric and protocol measurements Waveform / Data Analysis with Logic Analyzer
InfiniiMax Probes
DDR2 and DDR3 BGA Probe Adapters
E5384A & E5826/7A LA Cable Adapters
Parametric Measurement with Infiniium Scopes
Compatible with our scope and logic analyzer probes Page 18
Key Feature : Easiest way to access your DDR signals No designated probe points
DDR2 BGA Probe Adapter
Probe Here
Probe Here
Where to probe? Probe Here
High density board
Probe Here
DDR3 BGA Probe Adapter
DDR2 and DDR3 BGA probe adapters provide signal access points. Page 19
Agilent DDR Probing Solution Solder-in Probe is mainstream for DDR measurement • Both highest bandwidth and usability. • Reachable a very narrow space. Cost reduction with a Zero Insertion Force Probe Lead free solder-in probe. • Economical, ten ZIF tip at the same price as E2677A. • 12GHz, 7GHz, 4GHz bandwidth. •
E2677A Solder-in Probe Head
New Generation DRAM Probing: BGA Probe Adaptor • Inserted between PCB and DRAM. • Used with solder-in or ZIF probes. • Isolating resistors inside the probe. W2635A, W2636A DDR3 BGA Probe Adapter W2631A, W2632A, W2633A, W2634A DDR2 BGA Probe Adapter
N5425A Probe Head
N5426A ZIF Tip
Concept of the BGA Probe Adaptors Probe Here
Probe Here
DRAM
DDR2/3 BGA Probe PCB Embedded Resistors
BGA Probe Adopters are soldered-in between the DRAM and PCB. • Provide direct signal access to clock, DQS, DQ, Addr and Cmd at the BGA balls. • Embedded resistors (150Ohm) inside the BGA probes isolate the probe loading and prevent impact on the signal integrity. • Eliminates reflections from mid-bus probing methods. • Eliminates board space and trace routing required for traditional probing methods. •
Highest Signal Integrity for DDR DRAM Probing. First JEDEC true compliant DDR probing solution, as the JEDEC spec are defined at the DRAM ballout.
Usage of BGA Probe Adopters For Scope Connect the solder-in head or ZIF tip to The solder pads of the BGA probe adopters.
Logic Analyzer
For Logic Analyzer (DDR2 Only) Connect the dedicated cable to the flexible wing of the BGA probe adopter.
Comparison: Traditional vs BGA Probing Scope: You must think about where to probe. • There are some signals you cannot probe because of the design of your board. •
Logic Analyzer: You must prepare special probing points for LA at the design phase.
•
Scope, Logic Analyzer: You don’t need to look for probing points. • You can access most of the DDR signals. • You don’t need to prepare probing points for LA, you can mount the BGA probe only after troubles. •
The biggest merit of BGA probe adopter is that you can probe the signals even after troubles.
Measurements with BGA Probe Adapter (Scope) Traditional Probing (ex: at the trough hole)
BGA Probe Adapter
DDR3
DDR2
The BGA Probe Adopters don’t impact your DDR waveform.
DDR2 and DDR3 BGA Probe Model Number DDR2 BGA Probe Adapter for Logic Analyzer and Scope W2631A
DDR2 x16 BGA command and data probe (4 units)
W2632A
DDR2 x16 BGA data probe (4 units)
W2633A
DDR2 x8 BGA command and data probe (4 units)
W2634A
DDR2 x8 BGA data probe (4 units)
E5384A
46-ch single-ended ZIF probe for x8/x16 DRAM BGA probe connect to 90-pin LA cable
E5876A
46-ch single-ended ZIF probe for x16 DRAM data only BGA probe connect to 90-pin LA cable
E5877A
46-ch single-ended ZIF probe for 2 x8 DRAM data only BGA probe connect to 90-pin LA cable
1130/60A
InfiniiMax probe amplifier
N5424A/25A
ZIF probe head and tips
N5381A
Solder-in probe head
DDR3 BGA Probe Adapter for Scope W2635A-010
x8, 10 mm width DDR3 BGA probe adapter for x4 and x8 DRAM package (10 units)
W2635A-011
x8, 11 mm width DDR3 BGA probe adapter for x4 and x8 DRAM package (10 units)
W2636A-010
x16, 10 mm width DDR3 BGA probe adapter for x16 DRAM package (10 units)
W2636A-011
x16, 11 mm width DDR3 BGA probe adapter for x16 DRAM package (10 units)
1130/60A
InfiniiMax probe amplifier
N5424A/25A
ZIF probe head and tips
N5381A
Solder-in probe head
Page 25
Measurements with BGA Probe Adapter (Logic Analyzer) Device with BGA probe adapter mounted EyeScan screen
Eyes are open enough
DDR Decode (listing screen)
Logic Analyzer Solutions for DDR2 SO-DIMM FUTUREPLUS FS2337 SO-DIMM Interposer Reliable support up to 667MT/s Operation at 800MT/s need to be evaluated on your system Neeed 4 E5378A Samtech Probes to connect to Agilent Logic analyzer The FS2337 probe is has 2 parts, the Upper board and the Lower board. Because SODIMM connectors have 2 different orientations, Standard (STD) and Reverse (RVS), the probe has to be designed to fit into either target connector orientations, so there are Upper and Lower boards provided for each orientation. Additionally, because SODIMM applications are typically spaced constrained there are 2 different heights of the STD and RVS Lower boards provided in order to give the user some flexibility around taller components on the target board.
Wide Temperature and Wide Tips Spacing Solutions N5450A InfiniiMax Extreme Temperature Cable Extension Solution with Gore Cable Extension specially developed for InfiniiMax Perfect solution for the environmental chamber testing Agilent exclusive solution with 36 inches long (92cm) reach Two Different Operating Temp depending of the probe head N5381A solder-in: -55 to +150°C E2677A solder-in: -25 to +80°C
N5451A InfiniiMax Long Wire ZIF Tip Wider span than standard ZIF Tip to probe signal like DDR system Two different wire length: 7 mm (>6GHz) and 11 mm (>4.5GHz)
New Innovative Methods to Separate Read and Write Signals Separating read and write signals on the same bus is another huge challenge. Most validation engineers use the control signals to trigger on the Read or Write operations. However, limited scope channels are sometimes not enough to trigger and analyzing the signal integrity at the same time. Also, it is difficult to get a stable trigger. Engineers need to spend a lot time to fine tune the trigger setup and end up doing a lot of single shot acquisition to get the desirable signal.
Why you need to separate Read and Write? Scope triggers on DQS signal with both read and write cycles
DQS
DQ
DQ read and write cycles overlap each other. You cannot differentiate them.
The Read and Write signals overlap, difficult for any measurements. Read and Write Separation is necessary.
Current Methods and Challenges Preamble Width Trigger •
JEDEC spec on preamble width is loosely defined.
•
Not able to separate Read or Write when their widths are the same.
Trigger On Higher Signal Amplitude •
•
At times, the Read signal is larger than Write or vice-versa. Trigger at larger signal amplitude signal. Difficult to trigger if both Read and Write amplitudes are very close.
Mixed Signal Oscilloscope (with logic channels) Perfect solution to trigger on control signals for Read or Write operation. • MSO has lower analog bandwidth. Thus, it is not very suitable for higher data rate DDR There is nosuch perfect hardware trigger method for DDR Read and Write Separating. signals as DDR2 and DDR3. DDR waveforms change a lot between devices • Limited scope channels for high-end scopes. and also vary with probing points even for the same device. •
Use InfiniiScan to separate read and write signals There is no rule how to use the zones to separate the read or write signals. It depends on the silicon characteristics and DIMM loading which shows distinctive difference between the read and write signals.
High Impedance State DQS read or write normal bits
DQS read or write normal bits High impedance state
DQS read or write preamble bit
Use InfiniiScan ““Zone Zone Qualify Qualify”” to trigger on Read and Write distinctive waveform pattern. Page 32
Key Feature: Infiniiscan Read-Write Separation
Write Separation
Read Separation
Read and Write separation made easy with InfiniiScan ““Zone Zone Qualify Qualify”” Page 33
Measurements become easy after Read/Write separation
Jitter
Vswing
Using Histogram for parameter measurement is recommended、because with histogram the scope counts the number of dots itself. With markers, the measurement result can be subjective, and lack of repeatability.
Manual Measurement of Setup Time/Hold Time DDR Setup Time (tDS) and Hold Time (tDH) must be measured with particular thresholds.
1.15V 0V
Tresh voltage for DDR2 Setup Time (tDS) DQS: Vref=0V DQ: Vac=1.15V
Result = Marker delta time
For DDR2 Hold Time (tDH), DQS thresh is Vref=0V and DQ thresh is Vdc=1.025V
Automated DDR1/2/3 Measurements Separating the Read and Write bursts is just the beginning. Engineers then have to spend a lot of time on the work bench, manually making measurements on the signals. With so many test parameters to cover, there are limited number of times that a test parameter than can be repeated. Thus, a full characterization cannot be done. Also, the results have to manually recorded and formatted to a test report. Shouldn’t engineers be spending their time on more important matters?
Features of the DDR 1, 2 and 3 Applications Automated clock, electrical and timing measurements based on JEDEC spec or customizable speed for embedded designs, saving you precious time and effort.
Automated scope adjustment to handle variations in signal amplitude or user configurable signal thresholds for Vref, Vih and Vil parameters, giving you plenty of flexibility.
Ability to repeat measurements based on user settings with complete statistical results and worst case screenshots capture. Automated your measurements and analysis even when you are not there.
Results summary which includes margin analysis on how far the device comes to passing or failing the test.
Automatically generates a HTML test report for archiving and sharing result with others.
Tests Covered by DDR1, 2 and 3 Applications The DDR test application supports 2 test modes Compliance mode for JEDEC supported speed grade DDR1 Standard supported: JEDEC JESD79E Supported speed grades: 200, 266, 333, 400 DDR2 Standard supported: JEDEC JESD79-2C and Intel DDR2 JEDEC Addendum Supported speed grades: 400, 533, 667, 800 DDR3 Standard supported: JEDEC JESD79-3 Supported speed grades: 800, 1066, 1333, 1600
Advanced Debug mode for non standard speed grade in embedded designs User customizable speed grade. The app will adjust itself to user input speed grade.
Compliance and Advanced Debug Mode
Compliance Mode provides compliance measurements according to JEDEC speed grade. The results will be compared with the JEDEC test limits that will tell whether your device passes or fails the specification.
Advanced Debug Mode provides compliance test to Custom Data Rate. This feature is important for embedded design which is not operating at JEDEC speed grade. User can key in any desirable values. This mode supports use defined eye analysis as well.
Customization on Voltage Thresholds The app has flexibility to customize the voltage threshold settings. This is required because: Different DRAM vendors might have different voltage threshold spec. Embedded design might apply different threshold per design requirement. The DDR application will take the user input values for clock, electrical and timing measurements.
Automatically Repeat Measurements MultiTrial Run feature enables the selected tests to be repeated as many times as user wants.
The app will provide a statistical results of all the repeated measurements. User can specify the number of worst case results and screenshots to be captured as well.
Customizable Mask for Eye-Diagram Analysis
In Advanced Debug mode, user can make eye-diagram analysis of DDR signals with user customizable mask. The DQ signal is folded to an eye according to the DQS edge, providing accurate eye analysis.
Setting Up the DDR App for Measurements - 1 Select the DDR speed grade.
Selecting the tests.
Configure the apps before the measurements.
Setting Up the DDR App for Measurements - 2 Making sure you have made the right connections to your device and scope. User can choose to repeat the measurements. Run the tests.
Result summary page. Includes margin analysis on how close your device passes of fails the spec.
Example of Automated Measurements Eye-Diagram Analysis
Write Preamble Width
DQ Setup Time
Falling Edge Slew Rate
Automated HTML Report Generation
The app automatically generates a HTML report for sharing with others or result archiving purpose.
DDR1 Application Tests Parameters Specification JESD79E DDR1 SDRAM Specifications Table 6: Electrical Characteristics and DC Operating Conditions (page 45) Table 7: AC Operating Conditions (page 46) Table 8: Low Power DDR SDRAM Electrical Characteristics (page 46) Table 13: Input Slew Rate for DQ, DQS and DM (page 54) Table 20: AC Overshoot/Undershoot Specification for Address and Control Pins (page 55) Table 21: Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins (page 55) Table 11: Electrical Characteristics and AC Timing Part A: DDR333, DDR266, DDR200 Devices (page 50) Part B: DDR400A, DDR400B, DDR400C (page 51) Table 12: AC Timing Variations for DDR333, DDR266 and DDR200 Devices (page 52)
Test Items Vih(dc), Vil(dc), Vin(dc) Vih(ac), Vih(dc), Vid(ac), Vix(ac) Vih, Vil, Vin, Vid(dc), Vid(ac), Vix, Vihd(dc), Vild(dc), Vihd(ac), Vild(ac), Voh, Vol DCSLEW Maximum peak amplitude for overshoot area, Maximum peak area for undershoot area, Maximum overshoot area above VDD, Maximum undershoot area below GND Maximum peak amplitude for overshoot area, Maximum peak area for undershoot area, Maximum overshoot area above VDD, Maximum undershoot area below GND tAC, tDQSCK, tDQSQ, tQH, tDQSS, tDSS, tDSH, tHZDQ, tHZDQS, tLZDQ, tLZDQS, tWPRE, tWPST, tRPRE, tRPST, tDQSH, tDQSL, tDS(base), tDH(base), tIS(base), tIH(base) tAC, tDQSCK, tCK
Advanced Debug Mode All Tests in Compliance Mode Ringing Tests
User Defined Speed Grade User Defined for High/Low State
DDR2 Application Tests Parameters Specification Intel DDR2 667/800 JEDEC Specifications Addendum Rev 1.1 Clock and duty cycle spec (page 15)
Test Items
tCK(avg), tJIT(per), tJIT(cc), tERR(2per), tERR(3per), tERR(4per), tERR(5per), tERR(610), tERR(11-50), tCH(avg), tCL(avg), tJIT(duty)
JESD79-2C DDR2 SDRAM Specifications Table 19 – Input DC logic level (page 58) Vih(dc), Vil(dc) Table 20 – Input AC logic level (page 58) Vih(ac), Vil(ac) Table 21 – AC input test conditions (page 58) Vswing(max), SLEWr, SLEWf Table 22 – Differential input AC logic level (page 59) Vid(ac), Vix(ac) Table 23 – Differential AC output parameters (page 59) Vox(ac) Table 24 – AC overshoot/undershoot specification for Maximum peak amplitude for overshoot area, Maximum peak area for undershoot address and control pins: A0-A15, BA0-BA2, CS, RAS, area, Maximum overshoot area above VDD, Maximum undershoot area below VSS CAS, WE, CKE, ODT (page 59) Table 25 – AC overshoot/undershoot specification for Maximum peak amplitude for overshoot area, Maximum peak area for undershoot clock, data, strobe and mask pins: DQ, (U/L/R)DQS, area, Maximum overshoot area above VDDQ, Maximum undershoot area below VSSQ (U/L/R)DQS, DM, CK, CK (Page 60) Table 41 – Timing parameters by speed grade (DDR2 tAC, tDQSCK, tDQSQ, tQH, tDQSS, tDSS, tDSH, tHZDQ, tHZDQS, tLZDQ, tLZDQS, 400, 533, 667 & 800) (Page 73) tWPRE, tWPST, tRPRE, tRPST, tDQSH, tDQSL, tDS(base), tDH(base), tDS1(base), tDH1(base), tIS(base), tIH(base)
Advanced Debug Mode All Tests in Compliance Mode Eye-Diagram Test Ringing Tests
User Defined Speed Grade User Defined for DQ Read/Write User Defined for High/Low State
DDR3 Application Tests Parameters Specification JESD79-3 DDR3 SDRAM Specifications
Test Items
Table 26 – Single Ended AC and DC Input Levels (Page Vih(dc), Vil(dc), Vih(ac), Vih(dc) 103) Table 27 – Differential AC and DC input levels (Page 105) VIHdiff, VILdiff Table 28 – Cross Point Voltage for Differential Input Vix Signals (CK, DQS) (Page 105) Table 31 – Single Ended AC and DC Output Levels (Page Voh(dc), Vom(dc), Vol(dc), Voh(ac), Vol(ac) 109) Table 32 – Differential Output Slew Rate (Page 109) VOHdiff(ac), VOLdiff(ac) Table 34 – Output Slew Rate (Single-Ended) (Page 110) SRQse Table 36 – Differential Output Slew Rate (Page 111) SRQdiff Table 37 – AC Overshoot/Undershoot Specification for Maximum peak amplitude for overshoot area, Maximum peak area for undershoot Address and Control Pins (Page 113) area, Maximum overshoot area above VDD, Maximum undershoot area below VSS Table 38 – AC Overshoot/Undershoot Specification for Maximum peak amplitude for overshoot area, Maximum peak area for undershoot Clock, Data, Strobe and Mask (Page 114) area, Maximum overshoot area above VDDQ, Maximum undershoot area below VSSQ Table 66 – Timing Parameters by Speed Bin (Page 153) tCK(avg), tJIT(per), tJIT(cc), tERR(2per), tERR(3per), tERR(4per), tERR(5per), tERR(nper), tERR(nper2), tCH(avg), tCL(avg), tJIT(duty), tAC, tDQSCK, tDQSQ, tQH, tDQSS, tDSS, tDSH, tHZDQ, tHZDQS, tLZDQ, tLZDQS, tWPRE, tWPST, tRPRE, tRPST, tDQSH, tDQSL, tDS(base), tDH(base), tIS(base), tIH(base)
Advanced Debug Mode All Tests in Compliance Mode Eye-Diagram Test Ringing Tests
User Defined Speed Grade User Defined for DQ Read/Write User Defined for High/Low State
Two different kinds of Eye Patterns
Clock Recovered Eye
Traditional Eye
DQS DQ DQ
This is the manual method with Infiniiscan in p21-24.
This is the automated software method in p31.
What is the difference?
Traditional Eye Issue Trigger on DQS Fall Edge
DQS
DQ
With this method, each DQ eye is not written based on the DQS edge corresponding. Each DQS and DQ edge may have jitter from the trigger point, so DQ eyes can be more closed than they really are.
The Traditional Eye is not JEDEC compliant and not able to measure Setup/Hold Time accurately. And for Graphics Application, there is another problem…
Traditional Eye Issue The burst length for DRAM/CPU is usually 4 or 8, but for Graphics decoder, burst length can be over than 100. If you have different burst length mixed in your DDR waveform, you cannot make any measurement with the traditional eye. Traditional Eye
Short and Long bursts are mixed Long Burst
Short burst
For Graphics Application User, Clock Recovered Eye is indispensable.
Clock Recovered Eye Pattern
This clock recovery method is called Explicit Clock, and is one of the algorithm Agilent Eye Pattern software has.
Each DQ bit is cut off with its corresponding DQS, and next superimposed so as all the DQS edges come in the center.
This is JEDEC compliant way to make DQ Eyes.
XDRTMDRAM With Infiniiscan and Explicit Clock Recovery Algorithm, it is easy to make Read and Write separated Eyes for XDRTM DRMA too.
3.2Gbps clock DQ RQ8
Read and Write mixed
READ Eye Pattern
XDR DRAM is a high-speed memory with an interface capable of 4.0 GHz data rates. There is no DQS such as DDR DRAM. Flex Phase technology adjusts the setup/hold timing automatically and eliminates the need for trace length matching. XDR memory interfaces use Octal Data Rate (ODR), transferring 8 bits of data per clock cycle. ODR enables 3.2 GHz data rates with a 400 MHz clock, and 4.0 GHz data rates with a 500MHz clock. Clock Recovery Algorithm : Explicit Clock Multiplier, multiplied by 8. ( Agilent Only)
Debug Idea
Debugging problems with EZJIT tool EZJIT is a great tool to debug clock signal. Looking at the clock jitter frequency, user can understand what causes the clock jitter (noise) .
Comparing the jitter trend with some signals like power signal, you can find the root cause of clock jitter cause.
Power signal Clock Jiiter Trend
Clock Jiiter Trend
Clock Jiiter Spectrum
Check the frequencies of these peaks with markers.
In this case, the jitter trend period and the jitter Spectrum frequency was 1MHz. The problem was switching power supply.
Single-end measurement of Differential Signals Usually differential signals are measured with a differential probe, but sometimes it is good to check the positive and negative signals separately. In this case you can see that there is a common mode noise on the DQS signals, which you couldn’t know by looking at the differential DQS only.
DQS and /DQS
Differential mode Common mode
Crosspoint Voltage Measurement Crosspoint Voltage Measurement The vertical fluctuation results in timing jitter. If there is a skew between the differential pair, the crosspoints will go up and down alternately. If there is an offset, the crosspoints voltage will be different from the reference voltage.
Crosspoint function with UDF(User-Defined Function) You can use Inifiniiscan zone to get separately • Read DQS signals crosspoints • Write DQS signals crosspoints
You can analyze statistics of the crosspoint voltage with the Histogram function. In this case the histogram is checking the 6th crosspoint voltage.
Summary
Agilent is the test and measurement leader for DDR technology signal integrity measurements with:
Industry’s highest fidelity probing solutions for the most accurate measurement of DDR signals. New innovative methods to quickly and easily separate Read and Write signals which is not limited by scope analog input channels. Industry’s only complete DDR 1, 2 and 3 application packages for automated measurements and analysis. Active engagement and participation in JEDEC memory definition and test validation.
Tests Covered by DDR1, 2 and 3 Applications The DDR test application supports 2 test modes Compliance mode for JEDEC supported speed grade – DDR1 – Standard supported: JEDEC JESD79E – Supported speed grades: 200, 266, 333, 400 – DDR2 – Standard supported: JEDEC JESD79-2C and Intel DDR2 JEDEC Addendum – Supported speed grades: 400, 533, 667, 800 – DDR3 – Standard supported: JEDEC JESD79-3 – Supported speed grades: 800, 1066, 1333, 1600 Advanced Debug mode for non standard speed grade in embedded designs – User customizable speed grade. The app will adjust itself to user input speed grade. Note: Due to signal characteristics difference between DDR 1, 2 and 3 signals, the applications will not guarantee to work with different DDR generations. Page 60
U7233A DDR1 Full Compliance Package Model #:
U7233A
Infiniium Scope Models Supported: – 90000 Series – 80000 Series – 8000 Series Pre-requisite licenses: – N5414A InfiniiScan (for 80000/90000 Series) – N5415A InfiniiScan (for 8000 Series) Available Test Modes – Compliance Mode (JESD79E) – Clock, Electrical and Timing Parameters – Advanced Debug Mode (Custom Data Rate) – All tests from Compliance Mode – Ringing Test Page 61
N5413A DDR2 Compliance Test Application Model #:
N5413A
Infiniium Scope Models Supported: – 90000 Series – 80000 Series – 54850 Series Pre-requisite licenses: – E2688A Serial Data Analysis – N5414A InfiniiScan Available Test Modes – Compliance Mode (JESD79-2C, Intel Addendum) – Clock, Electrical and Timing Parameters – Advanced Debug Mode (Custom Data Rate) – All tests from Compliance Mode – Eye-Diagram Test – Ringing Test Page 62
U7231A DDR3 Full Compliance Package Model #:
U7231A
Infiniium Scope Models Supported: – 90000 Series – 80000 Series – 8000 Series Pre-requisite licenses: – N5414A InfiniiScan Available Test Modes – Compliance Mode (JESD79-3) – Clock, Electrical and Timing Parameters – Advanced Debug Mode (Custom Data Rate) – All tests from Compliance Mode – Ringing Test Page 63
New DDR Bundle – take advantage today! New DDR 1, 2 and 3 software bundle (N5459A) for oscilloscopes provides attractive savings! 1. N5459A software bundle option is now available for Infiniium oscilloscope users who are working on multiple DDR generations. 2. The new bundle option is available for $5,000 – priced at a significant discount compared to individual DDR software options. 3. N5459A allows you to get 3 licenses for DDRI/II/III and enables each compliance application
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DDR Resources DDR1 App Jumpstation and Datasheet: www.agilent.com/find/u7233a DDR2 App Jumpstation and Datasheet: www.agilent.com/find/n5413a DDR3 App Jumpstation and Datasheet: www.agilent.com/find/u7231a DDR Application Note: http://cp.literature.agilent.com/litweb/pdf/5989-6664EN.pdf
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Summary Agilent is the test and measurement leader for DDR technology signal integrity measurements with: Industry’s highest fidelity probing solutions for the most accurate measurement of DDR signals. New innovative methods to quickly and easily separate Read and Write signals which is not limited by scope analog input channels. Industry’s only complete DDR 1, 2 and 3 application packages for automated measurements and analysis. Active engagement and participation in JEDEC memory definition and test validation.
Agilent provides ““Superior Superior Probing for DDR Compliance Test and Debug Debug”” Page 66
FAQ #1
What is most challenging in DDR validation as compared to the other high speed serial standards today? Most of the standards today are differential transmitted such as USB and PCI-Express. However, DDR signals are single-ended so using good performance probe is critical to ensure measurement accuracy.
Is there other way to measure DDR signals without soldering probes on the device? No. This is the only way right now.
Does the JEDEC govern the compliance program like other standards such as USB or PCI-Express? No. DDR vendors themselves hold the responsibility to comply with the spec.
Your presentation focuses on separating read and writes cycles using the DQS and DQ signals, are there other signals we need to validate too? Yes. Other signals such as the clock, control and address have to be validated too. Our focus is on read and write signal because it is what many of the engineers found most challenging in their daily validation work.
Is there any plan in the near future to put MSO capability into your higher bandwidth scope? We have plans but not in the near future.
What test pattern do you need for DDR compliance? I have the capability to control my DDR device to transmit Readonly or Write-only cycles. It is not specified in the JEDEC spec. Ultimately, you will want to be able to look at real signals and determine whether it is performing to the spec. Analyzing the Read-only and Write-only won’t give you the full picture.
FAQ #2
What is the recommended bandwidth for DDR validation? We recommend 1GHz for DDR1, 4GHz for DDR2 and 6GHz for DDR3. But it depends on the signal’s fastest edge rate. Based on that, you can calculate the required bandwidth based on the scope bandwidth equation. The spec does not mention the minimum edge rate requirement or the scope bandwidth for compliance measurement.
Can the InfiniiScan zones be drawn on the DQ signal instead of DQS? Surely. It depends on the signal characteristics. It probably shows more distinctive difference on the DQ signal that you want to use it for read and write separation.
Can the app support different speed beside the speeds listed in the JEDEC spec? The DDR2 DRAM is used in my own DDR2 design. Yes, it is supported in the Advanced Debug mode since it is not compliance measurement. User can customize the speeds used in design.
Is the eye-analysis of the DQ signal referenced to the DQS edges? Yes. In fact, it uses the “Explicit Clock” recovery to fold the DQ bits based on the DQS edges.
Questions and Answers Contact Agilent France
[email protected] Téléphone: 0825 010 700
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