HIGH SPEED : fMAX = 79 MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 4024
DESCRIPTION The M74HC4024 is an high speed CMOS 7 STAGE BINARY COUNTER fabricated with silicon gate C2MOS technology. This devices is incremented on the falling edge (negative transition) of the input clock, and all its
DIP
SOP
TSSOP
ORDER CODES PACKAGE
TUBE
DIP SOP TSSOP
M74HC4024B1R M74HC4024M1R
T &R M74HC4024RM13TR M74HC4024TTR
outputs are reset to a low level by applying a logical high level on their reset input (CLEAR). All inputs are equipped with protection circuits against static discharge and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
1/10
M74HC4024 INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION PIN No
SYMBOL
1
CLOCK
2 12, 11, 9, 6, 5, 4, 3 8, 10, 13 7 14
CLEAR
Clock Input (HIGH to LOW, Edge-triggered) Reser Input (Active High)
Q1 to Q7 NC GND Vcc
NAME AND FUNCTION
Parallel Inputs Not Connected Ground (0V) Positive Supply Voltage
TRUTH TABLE CLOCK
CLEAR
OUTPUT STATE
X
H
ALL OUTPUTS = ”L”
L
NO CHANGE
L
ADVANCE TO NEXT STATE
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS Symbol V CC
Parameter Supply Voltage
Value
Unit
-0.5 to +7
V
VI
DC Input Voltage
-0.5 to VCC + 0.5
V
VO
DC Output Voltage
-0.5 to VCC + 0.5
V
IIK
DC Input Diode Current
± 20
mA
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Current
± 25
mA
ICC or IGND DC VCC or Ground Current PD
Power Dissipation
Tstg
Storage Temperature
TL
Lead Temperature (10 sec)
± 50
mA
500(*)
mW
-65 to +150
°C
300
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
2/10
M74HC4024 RECOMMENDED OPERATING CONDITIONS Symbol V CC
Parameter Supply Voltage
VI
Input Voltage
VO
Output Voltage
Top
Operating Temperature Input Rise and Fall Time
tr, tf
Value
Unit
2 to 6
V
0 to VCC
V
0 to VCC
V
-55 to 125
°C
VCC = 2.0V
0 to 1000
ns
VCC = 4.5V
0 to 500
ns
VCC = 6.0V
0 to 400
ns
DC SPECIFICATIONS Test Condition Symbol
VIH
V IL
VOH
VOL
II ICC
Parameter
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
Low Level Output Voltage
Input Leakage Current Quiescent Supply Current
Value TA = 25°C
VCC (V)
Min.
2.0 4.5 6.0 2.0 4.5 6.0
Typ.
Max.
1.5 3.15 4.2
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
1.5 3.15 4.2 0.5 1.35 1.8
Max.
1.5 3.15 4.2 0.5 1.35 1.8
Unit
V 0.5 1.35 1.8
V
IO=-20 µA
1.9
2.0
1.9
1.9
4.5
IO=-20 µA
4.4
4.5
4.4
4.4
6.0
IO=-20 µA
5.9
6.0
5.9
5.9
4.5
IO=-4.0 mA
4.18
4.31
4.13
4.10
6.0
IO=-5.2 mA
5.68
2.0
IO=20 µA
0.0
0.1
0.1
0.1
4.5
IO=20 µA
0.0
0.1
0.1
0.1
6.0
IO=20 µA
0.0
0.1
0.1
0.1
4.5
IO=4.0 mA
0.17
0.26
0.33
0.40
6.0
IO=5.2 mA
0.18
0.26
0.33
0.40
6.0
VI = VCC or GND
± 0.1
±1
±1
µA
6.0
VI = VCC or GND
4
40
80
µA
2.0
5.8
5.63
V
5.60
V
3/10
M74HC4024 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol
Parameter
tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (Qn - Qn+1) tPLH tPHL Propagation Delay Time (CLOCK -Q1) tPHL
fMAX
Propagation Delay Time (CLEAR - Qn) Maximum Clock Frequency
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
4/10
M74HC4024 TEST CIRCUIT
C L = 50pF or equivalent (includes jig and probe capacitance) R T = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1 : MINIMUM PULSE WIDTH (CLEAR) AND REMOVAL TIME (f=1MHz; 50% duty cycle)
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