TPS84620 9 mm × 15 mm × 2.8 mm
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SLVSA43A – OCTOBER 2010 – REVISED JANUARY 2011
4.5-V to 14.5-V Input, 6-A Synchronous Buck, Integrated Power Solution Check for Samples: TPS84620
FEATURES
1
•
2
• • • • • • • • • • • • • • • •
Complete Integrated Power Solution Allows Small Footprint, Low-Profile Design Efficiencies Up To 96% Wide-Output Voltage Adjust 1.2 V to 5.5 V, with 1% Reference Accuracy Optional Split Power Rail allows input voltage down to 1.7 V Adjustable Switching Frequency (480 kHz to 780 kHz) Synchronizes to an External Clock Adjustable Slow-Start Output Voltage Sequencing / Tracking Power Good Output Programmable Undervoltage Lockout (UVLO) Output Overcurrent Protection Over Temperature Protection Pre-bias Output Start-up Operating Temperature Range: –40°C to 85°C Enhanced Thermal Performance: 13°C/W Meets EN55022 Class B Emissions For Design Help Including SwitcherPro™ visit http://www.ti.com/tps84620
DESCRIPTION The TPS84620RUQ is an easy-to-use integrated power solution that combines a 6-A DC/DC converter with power MOSFETs, an inductor, and passives into a low profile, BQFN package. This total power solution allows as few as 3 external components and eliminates the loop compensation and magnetics part selection process. The 9×15×2.8 mm BQFN package is easy to solder onto a printed circuit board and allows a compact point-of-load design with greater than 90% efficiency and excellent power dissipation with a thermal impedance of 13°C/W junction to ambient. The device delivers the full 6-A rated output current at 85°C ambient temperature without airflow. The TPS84620 offers the flexibility and the feature-set of a discrete point-of-load design and is ideal for powering performance DSPs and FPGAs. Advanced packaging technology afford a robust and reliable power solution compatible with standard QFN mounting and testing techniques. SIMPLIFIED APPLICATION
PVIN PWRGD
VIN VIN
APPLICATIONS • • • • •
Broadband & Communications Infrastructure Automated Test and Medical Equipment Compact PCI / PCI Express / PXI Express DSP and FPGA Point of Load Applications High Density Distributed Power Systems
CIN
TPS84620
RT/CLK SENSE+ INH/UVLO SS/TR
100
RSET
STSEL AGND
85 Efficiency (%)
COUT
VADJ
95 90
VOUT
VOUT
PGND 80 75 70
UDG-10021
VOUT = 3.3 V fSW = 630 kHz
65 60
PVIN = VIN = 5 V PVIN = VIN = 12 V
55 50
0
1
2
3 4 Output Current (A)
5
6
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SwitcherPro is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
TPS84620 SLVSA43A – OCTOBER 2010 – REVISED JANUARY 2011
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1) over operating temperature range (unless otherwise noted)
Input Voltage
VALUE
UNIT
VIN
–0.3 to 16
V
PVIN
–0.3 to 16
V
INH/UVLO
–0.3 to 6
V
BOOT
–0.3 to 27
V
VADJ
–0.3 to 3
V
COMP
–0.3 to 3
V
PWRGD
–0.3 to 6
V
SS/TR
–0.3 to 3
V
STSEL
–0.3 to 3
V
RT/CLK
–0.3 to 6
V
BOOT-PH Output Voltage
0 to 7
V
PH
–1 to 20
V
PH 10ns Transient
–3 to 20
V
VDIFF (GND to exposed thermal pad)
–0.2 to 0.2
V
±100
µA
PH
Current Limit
A
PH
Current Limit
A
PVIN
Current Limit
A
±200
µA
RT/CLK
Source Current
Sink Current
COMP PWRGD
–0.1 to 5
Operating Junction Temperature
–40 to 125
Storage Temperature Mechanical Shock
Mil-STD-883D, Methed 2002.3, 1 msec, 1/2 sine, mounted
Mechanical Vibration
Mil-STD-883D, Methed 2007.2, 20-2000Hz
(1) (2)
2
mA (2)
°C
–65 to 150
°C
1500
G
20
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. See the temperature derating curves in the Typical Characteristics section for thermal information.
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TPS84620 www.ti.com
SLVSA43A – OCTOBER 2010 – REVISED JANUARY 2011
THERMAL INFORMATION TPS84620 THERMAL METRIC (1)
RUQ47
UNITS
47 PINS Junction-to-ambient thermal resistance (2)
qJA
(3)
13
qJCtop
Junction-to-case (top) thermal resistance
qJB
Junction-to-board thermal resistance (4)
yJT
Junction-to-top characterization parameter (5)
yJB
Junction-to-board characterization parameter (6)
5
qJCbot
Junction-to-case (bottom) thermal resistance (7)
n/a
(1) (2) (3) (4) (5) (6) (7)
9 6
°C/W
2.5
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
PACKAGE SPECIFICATIONS TPS84620 Weight Flammability MTBF Calculated reliability
UNIT 1.26 grams
Meets UL 94 V-O Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign
33.9 MHrs
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TPS84620 SLVSA43A – OCTOBER 2010 – REVISED JANUARY 2011
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ELECTRICAL CHARACTERISTICS over -40°C to 85°C free-air temperature, PVIN = VIN = 12 V, VOUT = 1.8 V, IOUT = 6A, CIN1 = 2x 22 µF ceramic, CIN2 = 68 µF poly-tantalum, COUT1 = 4x 47 µF ceramic (unless otherwise noted) PARAMETER
TEST CONDITIONS
IOUT
Output current
TA = 85°C, natural convection
VIN
Input bias voltage range
PVIN
Input switching voltage range
UVLO
VIN Undervoltage lockout
VOUT(adj)
VOUT
A
4.5
14.5
V
Over IOUT range
1.7 (1)
14.5
V
VIN = increasing
4.0 3.5
Output voltage adjust range
Over IOUT range
1.2
Set-point voltage tolerance
TA = 25°C, IOUT = 0A
Temperature variation
-40°C ≤ TA ≤ +85°C, IOUT = 0A
±0.3%
Line regulation
Over PVIN range, TA = 25°C, IOUT = 0A
±0.1%
Load regulation
Over IOUT range, TA = 25°C
±0.1%
Total output voltage variation
Includes set-point, line, load, and temperature variation
PVIN = VIN = 5 V IO = 3 A
VINH-H VINH-L
II(stby)
Inhibit Control
VOUT = 3.3V, fSW = 630kHz
90 %
VOUT = 2.5V, fSW = 530kHz
89 %
VOUT = 1.8V, fSW = 480kHz
87 %
VOUT = 1.5V, fSW = 480kHz
85 %
VOUT = 1.2V, fSW = 480kHz
83 %
VOUT = 3.3V, fSW = 630kHz
94 %
VOUT = 2.5V, fSW = 530kHz
92 %
VOUT = 1.8V, fSW = 480kHz
90 %
VOUT = 1.5V, fSW = 480kHz
88 %
VOUT = 1.2V, fSW = 480kHz
86 %
1.0 A/µs load step from 50 to 100% IOUT(max)
A
VOUT over/undershoot
60
INH < 1.1 V
-1.15
INH > 1.26 V
-3.4
Input standby current
INH pin to AGND
VOUT falling
fCLK
Synchronization frequency
VCLK-H
CLK High-Level Threshold
VCLK-L
CLK Low-Level Threshold
DCLK
CLK Duty cycle Thermal Shutdown
(1) (2) (3)
4
CLK Control
2 Good
94%
Fault
109%
Fault
91%
Good
106%
Thermal shutdown hysteresis
V mA mA
4
µA
0.3
V
560
kHz
480
780
kHz
2.0
5.5
V
0.8
V
400
480
20% Thermal shutdown
(3)
1.05
INH Hysteresis current
PWRGD Thresholds
mV Open
INH Input current
Over VIN and IOUT ranges, RT/CLK pin OPEN
mVPP µs
–0.3
I(PWRGD) = 2 mA
(2)
80
1.30
Switching frequency
±1.5%
V
Recovery time
Inhibit Low Voltage
PWRGD Low Voltage
(2)
V
11
Inhibit High Voltage
fSW
±1.0%
30
VOUT rising Power Good
5.5
93 %
20 MHz bandwith
4.5
3.85
VOUT = 5V, fSW = 780kHz
Overcurrent threshold Transient response
UNIT
Over IOUT range
VIN = decreasing
Output voltage ripple
MAX 6
Efficiency
ILIM
TYP
0
PVIN = VIN = 12 V IO = 3 A
h
MIN
160
80% 175
°C
10
°C
The minimum PVIN voltage is 1.7V or (VOUT+ 0.5V) , whichever is greater. VIN must be greater than 4.5V. The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external RSET resistor. This control pin has an internal pullup to the input voltage VIN. If it is left open circuit, the module operates when input power is applied. A small low-leakage ( 4.5 V VIN PVIN RUVLO1 INH/UVLO RUVLO2
UDG-10110
Figure 43. Adjustable PVIN Undervoltage Lockout, (VIN ≥4.5 V) Table 9. Standard Resistor Values for Adjusting PVIN UVLO, (VIN ≥4.5 V) PVIN UVLO (V)
24
2.0
2.5
3.0
3.5
4.0
4.5
RUVLO1 (kΩ)
68.1
68.1
68.1
68.1
68.1
68.1
RUVLO2 (kΩ)
95.3
60.4
44.2
34.8
28.7
24.3
Hysteresis (V)
300
315
335
350
365
385
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For higher PVIN UVLO voltages see Table UV for resistor values
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS84620
TPS84620 www.ti.com
SLVSA43A – OCTOBER 2010 – REVISED JANUARY 2011
Thermal Shutdown The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds 175°C typically. The device reinitiates the power up sequence when the junction temperature drops below 165°C typically.
Layout Considerations To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 44, shows a typical PCB layout. Some considerations for an optimized layout are: • Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal stress. • Place ceramic input and output capacitors close to the module pins to minimize high frequency noise. • Locate additional output capacitors between the ceramic capacitor and the load. • Place a dedicated AGND copper area beneath the TPS84620. • Isolate the PH copper area from the VOUT copper area using the AGND copper area. • Connect the AGND and PGND copper area at one point; near the output capacitors. • Place RSET, RRT, and CSS as close as possible to their respective pins. • Use multiple vias to connect the power planes to internal layers.
VOUT SENSE+ Via COUT2
COUT1 PGND RRT
CIN1
CIN2
AGND
PH RSET VIN/PVIN
SENSE+ Via CSS UDG-10132
Figure 44. Typical Recommended Layout Submit Documentation Feedback
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TPS84620 SLVSA43A – OCTOBER 2010 – REVISED JANUARY 2011
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EMI The TPS84620 is compliant with EN55022 Class B radiated emissions. Figure 45 and Figure 46 show typical examples of radiated emissions plots for the TPS84620 operating from 5V and 12V respectively. Both graphs include the plots of the antenna in the horizontal and vertical positions.
Figure 45. Radiated Emissions 5-V Input, 1.8-V Output, 6-A Load (EN55022 Class B)
26
Figure 46. Radiated Emissions 12-V Input, 1.8-V Output, 6-A Load (EN55022 Class B)
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Product Folder Link(s): TPS84620
TPS84620 www.ti.com
SLVSA43A – OCTOBER 2010 – REVISED JANUARY 2011
Changes from Original (October 2010) to Revision A
Page
•
Changed EN maximum voltage value from 3 V to 6 V ......................................................................................................... 2
•
Changed (corrected) resistor label from RRT to RSET on schematic ................................................................................... 17
•
Changed (corrected) minor typographical error on schematic ........................................................................................... 18
•
Changed (corrected) typographical error. ........................................................................................................................... 18
•
Changed (corrected) time axis division units label from 5 µs/div to 5 ms/div in Inhibit Turn-On waveform. ...................... 20
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Jan-2011
PACKAGING INFORMATION Orderable Device
Status
(1)
Package Type Package Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
Samples (Requires Login)
TPS84620RUQR
ACTIVE
B1QFN
RUQ
47
500
Green (RoHS & no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Add to cart
TPS84620RUQT
ACTIVE
B1QFN
RUQ
47
250
Green (RoHS & no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Add to cart
(1)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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