bq24650 www.ti.com

S LU S A 75 – JU L Y 2 0 1 0

Synchronous Switch-Mode Battery Charge Controller for Solar Power With Maximum Power Point Tracking Check for Samples: bq24650

FEATURES

1

•

APPLICATIONS • • • • •

Solar Powered Applications Remote Monitoring Stations Portable Handheld Instruments 12V to 24V Automotive Systems Current-Limited Power Source

LODRV

• •

16

15

14

13

VCC 1

12 REGN

PAS MPPSET 2

11 GND

bq24650 STAT1 3

10 SRP

TS 4

9 SRN 5

6

7

8

VFB

•

T he bq24650 supports a battery from 2.1V to 26V w ith V F B set to a 2.1V feedback reference. T he charge current is program m ed by sele ctin g an appropriate sense resistor. T he bq24650 is available in a 16 pin, 3.5! 3.5 m m 2 thin Q F N package.

PH

•

T he bq24650 charges the battery in three phases: pre-conditioning, constant current, and co n sta n t voltage. C harge is term inated w hen the cu rre n t reaches 1/10 of the fast charge rate. T he pre-charge tim er is fixed at 30 m inutes. T he bq24650 autom atically restarts the charge cycle if the battery voltage falls below an internal threshold and enters a low quiescent current sleep m ode w hen the in p u t voltage falls below the battery voltage.

TERM_EN

•

T he bq24650 offers a constant-fre q u e n cy synchronous P W M controller w ith high accuracy current and voltage regulation, ch a rg e preconditioning, charge term ination, and ch a rg e status m onitoring.

HIDRV

•

T he bq24650 is a highly integrated sw itch -m o d e battery charge controller. It provides inpu t vo lta g e regulation, w hich reduces charge current w h e n in p u t voltage falls below a program m ed level. W hen the input is pow ered by a solar panel, the input regulation loop low ers the charge current so that the so la r panel can provide m axim um pow er output.

VREF

• •

DESCRIPTION

BTST

• • •

Maximum Power Point Tracking (MPPT) Capability by Input Voltage Regulation Programmable MPPT Setting 5V-28V Input Solar Panel 600kHz NMOS-NMOS Synchronous Buck Controller Resistor Programmable Float Voltage Accommodates Li-Ion/Polymer, LiFePO4, Lead Acid Chemistries Accuracy – ±0.5% Charge Voltage Regulation – ±3% Charge Current Regulation – ±0.6% Input Voltage Regulation High Integration – Internal Loop Compensation – Internal Digital Soft Start Safety – Input Over-Voltage Protection – Battery Temperature Sensing – Battery Absent Detection – Thermal Shutdown Charge Status Outputs for LED or Host Processor Charge Enable on MPPSET Pin Automatic Sleep Mode for Low Power Consumption – V B A T , V C C > V U V L O , C E = LO W

5

µA

V C C > V B A T , V C C > V V C C LO W V , C E = H IG H , C harge done

5

µA

0.7

1

mA

2

3

mA

QUIESCENT CURRENTS T otal battery discharge current (sum of currents into V C C , B T S T , P H , S R P , S R N , V F B ), V F B ” 2.1V IB A T

B a tte ry discharge current (sum of currents into B T S T , P H , S R P , S R N , V F B ), V F B ” 2 .1V

V C C < V B A T , V C C > V U V L O (S LE E P )

V C C > V B A T , V C C > V U V L O , C E = LO W A d a p te r supply current (sum of current into V C C pin)

IA C

V C C > V B A T , V C C > V V C C LO W V , C E = H IG H , charge done V C C > V B A T , V C C > V V C C LO W V , C E = H IG H , C harging, Q g _ to ta l = 10nC [1]

25

mA

CHARGE VOLTAGE REGULATION VREG

F eedback regulation voltage

2.1

C harge voltage regulation accuracy IV F B

L eakage current into V F B pin

V

T J = 0°C to 85 °C

–0.5%

0.5 %

T J = – 40 °C to 125 °C

-0.7%

0.7 %

V F B = 2.1 V

10 0

nA

CURRENT REGULATION – FAST CHARGE V IR E G _C H G

S R P -S R N current sense voltage range

V IR E G _C H G = V S R P – V S R N

C harge current regulation accuracy

V IR E G _C H G = 40 m V

40 –3%

mV 3%

CURRENT REGULATION – PRE-CHARGE VPRECHG

P re ch a rg e current sense voltage range

V IR E G _P R C H G = V S R P – V S R N

P re ch a rg e current regulation accuracy

V IR E G _P R E C H = 4 m V

4 –25%

mV 25 %

CHARGE TERMINATION V TERM CHG

T erm ination current sense voltage range

V IT E R M = V S R P – V S R N

T erm ination current accuracy

V IT E R M = 4 m V

4 –25%

D eglitch tim e for term ination (both edges)

mV 25 %

100

tQ U A L

T erm ination qualification tim e

V B A T > V R E C H and I C H G < I T E R M

IQ U A L

T erm ination qualification current

D ischarge current once term ination is detected

ms

250

ms

2

mA

INPUT VOLTAGE REGULATION VMPPSET

M P P S E T regulation voltage

1.2

Input voltage regulation accuracy IM P P S E T

L eakage current into M P P S E T pin

V M P P S E T _C D

M P P S E T shorted to disable charge

V M P P S E T _C E

M P P S E T released to enable charge

–0.6%

V 0.6 %

V M P P S E T = 7 V , T A = 0 – 85 °C

1

µA

75

mV

175

mV

INPUT UNDER-VOLTAGE LOCK-OUT COMPARATOR (UVLO) V U V LO

A C under-voltage rising threshold

V U V LO _H Y S

A C under-voltage hysteresis, falling

M easure on V C C

3.65

3.85

4

V

350

mV

4.1

V

4.35

V

VCC LOWV COMPARATOR VVCC

LO W V _fall

F alling threshold, disable charge

VVCC

LO W V _rise

R ising threshold, resum e charge

M easure on V C C

SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION) V S LE E P

_F A LL

V S LE E P _H Y S

4

S L E E P falling threshold

V V C C – V S R N to enter S LE E P

40

S L E E P hysteresis S L E E P rising shutdow n deglitch

V C C falling below S R N

S L E E P falling pow erup deglitch

V C C rising above S R N , D elay to exit S LE E P m ode

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100

15 0

mV

500

mV

100

ms

30

ms

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S LU S A 75 – JU L Y 2 0 1 0

ELECTRICAL CHARACTERISTICS (continued) 5.0V ” V V C C ” 2 8 V , –40°C < T J + 125 °C , typical values a re a t T A = 2 5 °C , w ith re sp e ct to G N D (u n le ss o th e rw ise n oted) PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

1.54

1.55

1.5 6

V

BAT LOWV COMPARATOR V LO W V

P re ch a rg e to fast charge transition (LO W V threshold)

V LO W V _H Y S

L O W V hysteresis

M easure on V F B pin

100

mV

L O W V rising deglitch

V F B falling below V LO W V

25

ms

L O W V falling deglitch

V F B rising above V LO W V + V LO W V _H Y S

25

ms

RECHARGE COMPARATOR VRECHG

R echarge threshold (w ith respect to V R E G )

M easure on V F B pin

R echarge rising deglitch

V F B decreasing below V R E C H G

35

50 10

65

mV ms

R echarge falling deglitch

V F B increasing above V R E C H G

10

ms

BAT OVER-VOLTAGE COMPARATOR V O V _R IS E

O ver-voltage rising threshold

A s percentage of V F B

104%

V O V _F A LL

O ver-voltage falling threshold

A s percentage of V F B

102%

INPUT OVER-VOLTAGE COMPARATOR (ACOV) VACOV

A C over-voltage rising threshold on V C C

V A C O V _H Y S

A C over-voltage falling hysteresis

31

32

33

V

1

V

1

ms

A C over-voltage deglitch (both edges)

D elay to changing the S T A T pins

A C over-voltage rising deglitch

D elay to disable charge

1

ms

A C over-voltage falling deglitch

D elay to resum e charge

20

ms

T em perature increasing

145

°C

15

°C

THERMAL SHUTDOWN COMPARATOR TSHUT

T herm al shutdow n rising tem perature

T S H U T _H Y S

T herm al shutdow n hysteresis T herm al shutdow n rising deglitch

T em perature increasing

100

µs

T herm al shutdow n falling deglitch

T em perature decreasing

10

ms

THERMISTOR COMPARATOR V LT F

C old tem perature rising threshold

V LT F _H Y S

R ising hysteresis

V HTF

H ot tem perature rising threshold

V TCO

C ut-off tem perature rising threshold

A s percentage to V V R E F

D eglitch tim e for tem perature out of range d etection

V T S < V LT F , or V T S < V T C O , or V TS < V HTF

D eglitch tim e for tem perature in valid range d etection

72.5%

73.5%

0.2%

0.4%

74.5 % 0.6 %

46.7%

47.5%

48.3 %

44.3%

45%

45.7 %

400

ms

V T S > V LT F – V LT F _H Y S or V T S > V T C O , or V T S > V HTF

20

ms

C urrent rising, in synchronous m ode m easure (V S R P – V S R N )

80

mV

CHARGE OVER-CURRENT COMPARATOR (CYCLE-BY-CYCLE) VOC

C harge over-current rising threshold

CHARGE UNDER-CURRENT COMPARATOR (CYCLE-BY-CYCLE) V IS Y N S E T

C harge under-current falling threshold

S w itch from C C M to D C M , V S R P > 2.2V

1

5

9

mV

BATTERY SHORTED COMPARATOR (BATSHORT) V BATSHT

B A T short falling threshold, forced n on-synchronous m ode

V B A T S H T _H Y S

B A T short rising hysteresis

t B A T S H T _D E G

D eglitch on both edges

V S R P falling

2

V

200

mV

1

µs

1.25

mV

1.25

mV

1

µs

LOW CHARGE CURRENT COMPARATOR V LC

L ow charge current falling threshold

V LC _H Y S

L ow charge current rising hysteresis

t LC _D E G

D eglitch on both edges

M easure V (S R P -S R N )

VREF REGULATOR V V R E F _R E G

V R E F regulator voltage

V V C C > V U V L O , 0 – 35 m A load

I V R E F _LIM

V R E F current lim it

V VREF = 0 V , V VCC > V UVLO

3.267

3.3

3.3 3 3

35

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V mA

5

bq24650 S LU S A 75 – JU LY 2010

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ELECTRICAL CHARACTERISTICS (continued) 5.0V ” V V C C ” 2 8 V , –40°C < T J + 125 °C , typical values a re a t T A = 2 5 °C , w ith re sp e ct to G N D (u n le ss o th e rw ise n oted) PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

6.0

6 .3

UNITS

REGN REGULATOR V R E G N _R E G

R E G N regulator voltage

V V C C > 10 V , M P P S E T > 175 m V

5.7

I R E G N _LIM

R E G N current lim it

V R E G N = 0 V , V V C C > V U V L O , M P P S E T < 75 m V

40

V mA

BATTERY DETECTION tW A K E

W ake tim er

M ax tim e charge is enabled

IW A K E

W ake current

R S E N S E = 10 m ȍ

500

t D IS C H A R G E

D ischarge tim er

M ax tim e discharge current is applied

1

se c

I D IS C H A R G E

D ischarge current

6

mA

I F A U LT

F ault current after a tim eout fault

2

mA

IQ U A L

T erm ination qualification current

2

mA

tQ U A L

T erm ination qualification tim e

50

VW AKE

W ake threshold (w ith respect to V R E G )

V oltage on V F B to detect battery absent during w ake

V D IS C H

D ischarge threshold

V oltage on V F B to detect battery absent during discharge

125

ms 20 0

mA

250

ms

50

mV

1.55

V

PWM HIGH SIDE DRIVER (HIDRV) R D S _H I_O N

H igh side driver (H S D ) turn-on resistance

R D S _H I_O F F

H igh side driver turn-off resistance

V B T S T _R E F R E S H

B o o tstra p refresh com parator threshold V o lta g e

V B T S T – V P H = 5.5 V V B T S T – V P H w hen low side refresh pulse is requested

4.0

3.3

6

ȍ

1

1 .4

ȍ

4.2

V

PWM LOW SIDE DRIVER (LODRV) R D S _LO _O N

L ow side driver (LS D ) turn-on resistance

R D S _LO _O F F

L ow side driver turn-off resistance

4.1

7

ȍ

1

1 .4

ȍ

PWM DRIVERS TIMING D river dead-tim e

D ead tim e w hen sw itching betw een LS D and H S D , N o load at LS D and H S D

P W M ram p height

A s percentage of V C C

30

ns

PWM OSCILLATOR V R A M P _H E IG H T

7%

P W M sw itching frequency

510

600

69 0

kH z

INTERNAL SOFT START (8 steps to regulation current ICHG) S o ft start steps S o ft start step tim e

8

ste p

1.6

ms

1.5

s

CHARGER SECTION POWER-UP SEQUENCING D elay from M P P S E T > 175 m V to charger is allow ed to turn on

C harge-enable delay after pow er-up LOGIC IO PIN CHARACTERISTICS (STAT1, STAT2, TERM_EN) V O U T _LO W

S T A T 1 , S T A T 2 output low saturation voltage

S ink current = 5 m A

0 .5

V

I O U T _H I

L eakage current

V = 32 V

1 .2

µA

V IN _LO W

T E R M _E N input low threshold voltage

0 .4

V

V IN _H I

T E R M _E N input high threshold voltage

I IN _B IA S

T E R M _E N bias current

60

µA

6

1.6 V T E R M _E N = 0.5 V

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S LU S A 75 – JU L Y 2 0 1 0

TYPICAL CHARACTERISTICS V C C = 25V , bq24650 A pplica tio n C ircu it, T A = 2 5°C u n le ss o th e rw ise n o te d

MPPSET 1V/div

VCC 10V/div

LODRV 5V/div VREF 2V/div

PH 20V/div

REGN 5V/div

STAT1 20V/div

IBAT 1A/div

400 ms/div

800 !s/div

Figure 2. Power Up on VCC

Figure 3. Charge Start on MPPSET

MPPSET 1V/div

MPPSET 1V/div

LODRV 5V/div

LODRV 5V/div

PH 20V/div

PH 20V/div

IBAT 1A/div

IBAT 1A/div

10 !s/div

4 ms/div

Figure 4. Charge Soft Start on MPPSET

Figure 5. Charge Stop on MPPSET

HIDRV 20V/div

HIDRV 20V/div

PH 20V/div

PH 20V/div

LODRV 5V/div

LODRV 5V/div

IL 1A/div

IL 1A/div

100 ns/div Figure 6. Switching in Continuous Conduction Mode

200 ns/div

Figure 7. Switching in Discontinuous Conduction Mode

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TYPICAL CHARACTERISTICS (continued) V C C = 2 5 V , b q 2 4 6 5 0 A pplication C ircuit, T A = 25°C u n le ss o th e rw ise n o te d HIDRV 20V/div

HIDRV 20V/div

PH 20V/div

PH 20V/div

LODRV 5V/div

LODRV 5V/div

IL 1A/div

IL 1A/div

400 !s/div

100 ns/div

Figure 8. Switching at 100% Duty Cycle

VIN 5V/div

MPPT Regulation Point

Figure 9. Recharge the BTST-PH Capacitor

VIN 20V/div VBAT 5V/div

PH 20V/div

IBAT 0.5A/div

IL 1A/div

10 ms/div

1 s/div Figure 11. Battery Insertion and Removal

Figure 10. MPPT Regulation During Soft Start

VIN 20V/div

VIN 20V/div

VBAT 5V/div

VBAT 5V/div

PH 20V/div

PH 20V/div

IL 1A/div

IL 1A/div

400 ms/div

10 !s/div

Figure 12. Short Battery Response

8

Figure 13. Charge Reset During Battery Short

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S LU S A 75 – JU L Y 2 0 1 0

TYPICAL CHARACTERISTICS (continued) V C C = 2 5 V , b q 2 4 6 5 0 A pplication C ircuit, T A = 25°C u n le ss o th e rw ise n o te d 100

95

Efficiency - %

ICHG 2A ICHG 1A 90

85

80 0

5

10 VO - Output Voltage - V

15

20

Figure 14. Efficiency vs Output Voltage (VCC = 25V)

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PIN FUNCTIONS PIN NO.

NAME

DESCRIPTION

1

VCC

P

IC p o w e r p o sitive su p ply. P lace a 1-PF ceram ic capacitor from V C C to G N D and place it as clo se as p o ssib le to IC . P la ce a 10-ȍ resistor from in p u t side to V C C pin to filter the noise.

2

MPPSET

I

In p u t vo lta g e se t p o in t. U se a voltage divider from in p u t source to G N D to set voltage on M P P S E T to 1 .2 V . T o d isa b le ch a rg e, pull M P P S E T below 75m V .

3

STAT1

O

O p e n d ra in ch a rg e status output to in d ica te various charger operation. C onnect to the cathode of LE D w ith 1 0 kȍ to th e p u ll-up rail. LO W or LE D lig h t up in d ica te s charge in progress. O th erw ise stays H I or L E D sta ys o ff. W h e n any fault condition occurs, both S T A T 1 and S T A T 2 are H I, or both LE D s are off.

4

TS

I

T em perature q u a lifica tion voltage in p u t. C onnect to a negative tem perature coefficient therm istor. P ro g ra m th e h o t a n d cold tem perature w indow w ith a resistor divider from V R E F to T S to G N D . A 1 0 3 A T -2 th e rm iste r is recom m ended.

5

STAT2

O

O p e n d ra in ch a rg e status output to in d ica te various charger operation. C onnect to the cathode of LE D w ith 1 0 kȍ to th e p u ll-up rail. LO W or LE D lig h t up in d ica te s charge is com plete. O therw ise, sta ys H I or L E D sta ys o ff. W h e n any fault condition occurs, both S T A T 1 and S T A T 2 are H I, or both LE D s are off.

6

VREF

P

3 .3 V reference vo lta g e output. P lace a 1-PF ceram ic capacitor from V R E F to G N D pin close to the IC . T his vo lta g e co u ld b e used for program m ing voltage on T S and the pull-up rail of S T A T 1 and S T A T 2.

7

TERM _EN

I

C harge te rm in a tio n e n able. P ull T E R M _ E N to G N D to disable charge term ination. P ull T E R M _E N to V R E F to a llo w ch a rg e term ination. T E R M _ E N m u st be term inated and cannot be le ft floating.

8

VFB

I

C harge vo lta g e a n a lo g feedback adjustm ent. C onnect the output of a resistor divider pow ered from the b a tte ry te rm in a ls to th is node to adjust the output battery voltage regulation.

9

SRN

I

C harge cu rre n t se n se resistor, negative in p u t. A 0.1-PF ceram ic capacitor is placed from S R N to S R P to p ro vid e d iffe re n tia l-m o de filtering. A n optional 0.1-PF ceram ic capacitor is placed from S R N to G N D for co m m o n -m o d e filte rin g.

10

SRP

P /I

C harge cu rre n t se n se resistor, positive in p u t. A 0.1-PF ceram ic capacitor is placed from S R N to S R P to p ro vid e d iffe re n tia l-m o de filtering. A 0.1-PF ceram ic capacitor is placed from S R P to G N D for co m m o n -m o d e filte rin g.

11

GND

P

P o w e r g ro u n d . G ro u n d connection for high-current pow er converter node. O n P C B la yo u t, con n e ct d ire ctly to so u rce o f low -sid e pow er M O S F E T , to ground connection of in p u t and output capacito rs of the ch a rg e r. O n ly co n n e ct to G N D through the therm al pad underneath the IC .

12

REGN

P

P W M low -side d rive r positive 6V supply output. C onnect a 1-PF ceram ic capacitor from R E G N to G N D , clo se to th e IC . U se to drive lo w -sid e driver and high-side driver bootstrap S chottky diode from R E G N to BTST.

13

LO D R V

O

P W M low -side d rive r output. C onnect to the gate of the lo w -sid e N -channel pow er M O S F E T w ith a sh o rt tra ce .

14

PH

P

S w itch in g n o d e , ch a rg e current output in d u cto r connection. C onnect the 0.1-PF bootstrap capa cito r from P H to B T S T .

15

H ID R V

O

P W M h ig h -sid e d rive r output. C onnect to the gate of the high-side N -channel pow er M O S F E T w ith a sh o rt tra ce .

16

BTST

P

P W M h ig h -sid e d rive r positive supply. C onnect the 0.1-uF bootstrap capacitor from P H to B T S T .

T h e rm a l Pad

10

TYPE

E xp o se d p a d b e n e a th the IC . T h e therm al pad m u st alw ays be soldered to the board and have the via s o n th e th e rm a l p a d p lane star-connecting to G N D and ground plane for high-current pow er con ve rte r. It a lso se rve s a s a th e rm al pad to dissipate heat.

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S LU S A 75 – JU L Y 2 0 1 0

BLOCK DIAGRAM bq24650

VREF VOLTAGE REFERENCE VCC

-

SRN+100 mV

+

SLEEP VREF

3.3V LDO

UVLO

VCC

VCC

-

VUVLO

+

SLEEP

UVLO

VCC

175 mV

+ FBO

MPPSET

1.2 V

COMP ERROR AMPLIFIER

+

-

EAI

2.1 V

CE

+

+

1V

+

VFB

BTST EAO PWM

-

LEVEL SHIFTER

-

BAT_OVP 20uA

SRP

SRP-SRN

+

SYNCH

PH

+ 20X -

V(SRP-SRN) 0.8V

PWM CONTROL LOGIC

+ 5 mV -

+ -

SRN

BTST _+

PH

20 uA

VCC

6V LDO

REFRESH

-

CE

4V

LODRV V(SRP-SRN)

-

200% X IBAT_REG

+

2 mA

CHG_OCP GND

8 mA

FAULT 30 Minute Precharge Timer

CHARGE DISCHARGE

TERM_EN 0.8V

STAT 1

IC Tj

+

145°C

-

TSHUT

CHARGE STAT1

VFB

-

104% X 2.1V

+

BAT_OVP

STATE MACHINE LOGIC

IBAT_ REG

0.8V 10

STAT2 STAT 2

LOWV

1.5V +-

-

LOWV

BATTERY DETECTION LOGIC

DISCHARGE

VREF

+ VCC

+

LTF

ACOV

+

-

TS

+

VFB

REGN

+

FAULT

VFB

HIDRV

-

32V -

SUSPEND

RCHRG

HTF

+

+ -

2.05V +RCHRG V(SRP - SRN) 0.8V 10

+

TERM

TERM

TCO

+ -

TERMINATE CHARGE

Figure 15. Functional Block Diagram

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DETAILED DESCRIPTION

Regulation Voltage VRECH Regulation Current

Precharge Current Regulation Phase

Fastcharge Current Regulation Phase

Fastcharge Voltage Regulation Phase

Termination

Charge Current

Charge Voltage

VLOWV

IPRECH & ITERM

Figure 16. Typical Charging Profile

BATTERY VOLTAGE REGULATION T he bq24650 uses a high accuracy voltage regulator for the charging voltage. T he charge vo lta g e is program m ed via a resistor divider from the battery to ground, w ith the m idpoint tied to the V F B pin. T he vo lta g e at the V F B pin is regulated to 2.1V , giving the follow ing equation for the regulation voltage: ! R2 " VBAT = 2.1 V # $1+ & R1 %' (1) w here R 2 is connected from V F B to the battery and R 1 is connected from V F B to G N D . Li-Ion, LiF eP O 4, and sealed lead acid are w idely used battery chem istries. M ost com m ercial Li-ion cells ca n now be charged to 4.2V /cell. A LiF eP O 4 battery allow s a m uch higher charge and discharge rate, but the energy density is low er. T he typical cell voltage is 3.6V . T he charge profile of both Li-Ion and LiF eP O 4 is preconditioning, constant current, and constant voltage. F or m axim um cycle life, the end-of-charge vo lta g e threshold could be low ered to 4.1V /cell. A lthough it's energy density is m uch low er than Li-based chem istry, lead acid is still popular due to its lo w m anufacturing cost and high discharge rates. T he typical voltage lim it is from 2.3V to 2.45V . A fter the battery has been fully charged, a float charge is required to com pensate for the self-discharge. T he float charge lim it is 100m V -200m V below the constant voltage lim it.

INPUT VOLTAGE REGULATION A solar panel has a unique point on the V -I or V -P curve, called the M axim um P ow er P oint (M P P ), at w h ich the entire photovoltaic (P V ) system operates w ith m axim um efficiency and produces its m axim um output pow er. T he constant voltage algorithm is the sim plest M axim um P ow er P oint T racking (M P P T ) m ethod. T he bq24650 autom atically red uces charge current so the m axim um pow er point is m aintained for m axim um efficiency.

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If the solar panel or other input source cannot provide the total pow er of the system and bq24650 ch a rg e r, the input voltage drops. O nce the voltage sensed on the M P P S E T pin drops below 1.2V , the charger m aintains the input voltage by reducing the charge current. If the M P P S E T pin voltage is forced below 1.2V , the bq24650 sta ys in the input voltage regulation loop w hile the output current is zero. T he S T A T 1 pin is LO W and S T A T 2 pin is H IG H . T he voltage at the M P P S E T pin is regulated to 1.2V , giving E quation 2 for the regulation voltage: ! R3 " VMPPSET = 1.2 V # $1+ % & R4 '

(2)

T he M P P S E T pin is also used as charge enable control. If the voltage on M P P S E T is pulled dow n below 75m V , charge is disabled. C harge resum es if the voltage on M P P S E T goes back above 175m V .

BATTERY CURRENT REGULATION B attery current is sensed by resistor R S R connected betw een S R P and S R N . T he full-scale differential vo lta g e betw een S R P and S R N is fixed at 40m V . T hus, for a 20-m ȍ sense resistor, the charging current is 2A . F or charging current, refer to E quation 3: 40 mV ICHARGE = RSR (3)

BATTERY PRECHARGE O n pow er-up, if the battery voltage is below the V LO W V threshold, the bq24650 applies the precharge cu rre n t to the battery. T his feature is intended to revive deeply discharged cells. If the V LO W V threshold is not reached w ith in 30 m inutes of initiating precharge, the charger turns off and a F A U LT is indicated on the status pins. T he precharge current is determ ined as 1/10 of the fast charge current according to the follow ing equation: 4 mV IPRECHARGE = RSR

(4)

CHARGE TERMINATION AND RECHARGE T he bq24650 m onitors the charging current during the voltage regulation phase. T erm ination is detected w h ile the voltage on the V F B pin is higher than the V R E C H threshold and the charge current is less than the I T E R M threshold (1/10 of fast charge current), as calculated in E quation 5: 4 mV ITERM = RSR (5) A • • •

new charge cycle is initiated w hen one of the follow ing conditions occurs: T he battery voltage falls below the recharge threshold A pow er-on-reset (P O R ) event occurs M P P S E T falls below 75m V to reset charge enable

T he T E R M _E N pin m ay be taken LO W to disable term ination. If T E R M _E N is pulled above 1.6V , the bq24650 allow s term ination.

POWER UP T he bq24650 uses a S LE E P com parator to determ ine the source of pow er on the V C C pin, since V C C ca n be supplied either from a battery or an adapter. If the V C C voltage is greater than the S R N voltage, and all other conditions are m et for charging, the bq24650 then attem pts to charge a battery (see the Enabling and Disabling Charging section). If S R N voltage is greater than V C C , indicating that a battery is the pow er so u rce , the bq24650 enters low quiescent current (< 15µA ) S LE E P m ode to m inim ize current drain from the battery. If V C C is below the U V LO threshold, the device is disabled, and V R E F LD O turns off.

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ENABLE AND DISABLE CHARGING T he follow ing conditions have to be valid before charging is enabled: • C harge is allow ed (M P P S E T > 175m V ) • D evice is not in U nder-V oltage-Lock-O ut (U V LO ) m ode and V C C is above the V C C LO W V threshold • D evice is not in S LE E P m ode (i.e. V C C > S R N ) • V C C voltage is low er than A C over-voltage threshold (V C C < V A C O V ) • 30m s delay is com plete after initial pow er-up • R E G N LD O and V R E F LD O voltages are at correct levels • T herm al S hut (T S H U T ) is not valid • T S fault is not detected O ne of the follow ing conditions stops on-going charging: • C harge is disabled (M P P S E T < 75m V ) • A dapter is rem oved, causing the device to enter V C C LO W V or S LE E P m ode • A dapter voltage is less than 100m V above battery • A dapter is over voltage • R E G N or V R E F LD O voltage is not valid • T S H U T IC tem perature threshold is reached • T S voltage goes out of range indicating the battery tem perature is too hot or too cold

AUTOMATIC INTERNAL SOFT-START CHARGER CURRENT T he charger autom atically soft-starts the charger regulation current every tim e the charger goes into fast-charge to ensure there is no overshoot or stress on the output capacitors or the pow er converter. T he soft-start co n sists of stepping-up the charge regulation current into 8 evenly divided steps up to the program m ed charge cu rre n t. E ach step lasts approxim ately 1.6m s, for a typical rise tim e of 13m s. N o external com ponents are needed for this function.

CONVERTER OPERATION T he synchronous buck P W M converter uses a fixed frequency voltage m ode w ith feed-forw ard control sch e m e . A type III com pensation netw ork allow s using ce ram ic capacitors at the output of the converter. T he com p e n sa tio n input stage is connected internally betw een the feedback output (F B O ) and the error am plifier input (E A I). T he feedback com pensation stage is connected betw een the error am plifier input (E A I) and error am plifier output (E A O ). T he LC output filter m ust be selected to give a resonant frequency of 12 kH z – 17 kH z for the bq24650, w here resonant frequency, f o , is given by: 1 fo = 2! L o Co (6) A n internal saw -tooth ram p is com pared to the internal E A O error control signal to vary the duty-cycle of the converter. T he ra m p height is 7% of the inpu t adapter voltage m aking it alw ays directly proportional to the in p u t adapter voltage. T his cancels out any loop gain variation due to a change in input voltage and sim plifies the lo o p com pensation. T he ram p is offset by 300m V in order to allow zero percent duty-cycle w hen the E A O sig n a l is below the ram p. T he E A O signal is also allow ed to exceed the saw -tooth ram p signal in order to get a 100% duty-cycle P W M request. Internal gate drive logic allow s achieving 99.98% duty-cycle w hile ensuring the N -channel upper device alw ays has enough voltage to stay fully on. If the B T S T pin to P H pin voltage falls below 4.2V for m ore than 3 cycles, then the high-side n-channel pow er M O S F E T is turned off and the lo w -sid e n-channel pow er M O S F E T is turned on to pull the P H node dow n and recharge the B T S T capacitor. T hen the high-side driver returns to 100% duty-cycle operation until the (B T S T -P H ) voltage is detected to fall lo w again due to leakage current discharging the B T S T capacitor below 4.2 V , and the reset pulse is reissued. T he fixed frequency oscillator keeps tight con trol of the sw itching frequency under all conditions of inpu t vo lta g e , battery voltage, charge current, and tem perature, sim plifying output filter design and keeping it out of the audible noise region.

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SYNCHRONOUS AND NON-SYNCHRONOUS OPERATION T he charger operates in synchronous m ode w hen the S R P -S R N voltage is above 5m V (0.5-A inductor cu rre n t for a 10-m ȍ sense resistor). D uring synchro nous m ode, the internal gate drive logic ensures there is break-before-m ake com plim entary sw itching to prevent shoot-through currents. D uring the 30ns dead tim e w h e re both F E T s are off, the body-diode of the low -side pow er M O S F E T conducts the inductor current. H a vin g the low -side F E T turn on keeps pow er dissipation low , and allow s safe charging at high currents. D u rin g synchronous m ode the inductor current is alw ays flow ing and the converter operates in continuous co n d u ctio n m ode (C C M ), creating a fixed tw o-pole system . T he charger operates in non-synchronous m ode w hen the S R P -S R N voltage is below 5m V (0.5-A in d u cto r current for a 10-m ȍ sense resistor). In addition, the charger is forced into non-synchronous m ode w hen battery voltage is low er than 2V or w hen the average S R P -S R N voltage is low er than 1.25m V . D uring non-synchronous operation, the body-diode of the low -side M O S F E T can conduct the positive in d u cto r current after the low -side n-channel pow er M O S F E T turns off. W hen the load current decreases and the in d u cto r current drops to zero, the body diode is naturally turned off and the inductor current becom es discontinuous. T his m ode is called D iscontinuous C onduction M ode (D C M ). D uring D C M , the low -side n-channel pow er M O S F E T turns on w hen the bootstrap capacitor voltage drops below 4.2V , then the low -side pow er M O S F E T turns off and stays off until the beginning of the next cycle, w here the high-side pow er M O S F E T is turned on again. T he low -side M O S F E T on tim e is required to ensure the bootstrap capacitor is alw ays recharged and able to ke e p the high-side pow er M O S F E T on during the next cycle. T his is im portant for battery chargers, w here unlike regular dc-dc converters, there is a battery load that m aintains a voltage and can both source and sink cu rre n t. T he low -side pulse pulls the P H node (connection betw een high and low -side M O S F E T s) dow n, allow ing the bootstrap capacitor to recharge up to the R E G N LD O value. A fter the refresh pulse, the low -side M O S F E T is kept off to prevent negative inductor current from occurring. A t very low currents during non-synchronous operation, there m ay be a sm all am ount of negative in d u cto r current during the recharge pulse. T he charge should be low enough to be absorbed by the input cap a cita n ce . W henever the converter goes into zero percent duty-cycle, the high-side M O S F E T does not turn on, and the low -side M O S F E T does not turn on (except for recharge pulse) either, and there is alm ost no discharge from the battery. D uring D C M m ode the loop response autom atically changes and has a single pole system at w hich the pole is proportional to the load current, because the converter does not sink current, and only the load provides a current sink. T his m eans at very low currents the loop response is slow er, as there is less sinking cu rre n t available to discharge the output voltage.

CYCLE-BY-CYCLE CHARGE UNDER CURRENT In the bq24650, if the S R P -S R N voltage decreases below 5m V , the low side F E T is turned off for the rem ainder of the sw itching cycle to prevent negative indu ctor current. D uring D C M , the low -side F E T only turns on w h e n the bootstrap capacitor voltage drops below 4.2V to provide refresh charge for the bootstrap capacito r. T his is im portant to prevent negative inductor current from causing a boost effect in w hich the input voltage incre a se s as pow er is transferred from the battery to the input capacitors and lead to an over-voltage stress on the V C C node and potentially cause dam age to the system .

INPUT OVER-VOLTAGE PROTECTION (ACOV) A C O V provides protection to prevent system dam age due to high input voltage. O nce the adapter vo lta g e rea ches the A C O V threshold, charge is disabled.

INPUT UNDER-VOLTAGE LOCK OUT (UVLO) T he system m ust have a m inim um V C C voltage to allow proper operation. T his V C C voltage could co m e from either input adapter or battery, since a cond uction path exists from the battery to V C C through the high-side N M O S body diode. W hen V C C is below the U V LO threshold, all circuits on the IC , including V R E F LD O , are disabled.

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BATTERY OVER-VOLTAGE PROTECTION T he converter does not allow the high-side F E T to turn on until the B A T voltage goes below 102% of the reg ulation voltage. T his allow s one-cycle response to an over-voltage condition – such as occurs w hen the lo a d is rem oved or the battery is disconnected. A current sink from S R P to G N D is on to discharge the store d energy on the output capacitors.

CYCLE-BY-CYCLE CHARGE OVER-CURRENT PROTECTION T he charger has a secondary cycle-to-cycle over-current protection. It m onitors the charge current and prevents the current from exceeding 200% of the program m ed charge current. T he high-side gate drive turns off w h e n over-current is detected and autom atically resum es w hen the current falls below the over-current threshold.

THERMAL SHUTDOWN PROTECTION T he Q F N package has low therm al im pedance, w hich provides good therm al conduction from the silico n to the am bient, to keep junction tem peratures low . A s an added level of protection, the charger converter turns off and self-protects w henever the junction tem perature exceeds the T S H U T threshold of 145°C . T he charger sta ys off until the junction tem perature falls below 130°C .

TEMPERATURE QUALIFICATION T he controller continuously m onitors battery tem perature by m easuring the voltage betw een the T S pin and G N D . A negative tem perature coefficient therm istor (N T C ) and an external voltage divider typically develop this voltage. T he controller com pares this voltage against its internal thresholds to determ ine if charging is allow ed. T o initiate a charge cycle, the battery tem perature m ust be w ithin the V LT F to V H T F thresholds. If battery tem perature is outside of this range, the con troller suspends charge and w aits until the battery tem perature is w ithin the V L T F to V H T F range. D uring the charge cycle the battery tem perature m ust be w ithin the V LT F to V T C O thresholds. If battery tem perature is outside of this range, the controller suspends charge and w aits until the battery tem perature is w ithin the V LT F to V H T F range. T he controller suspends charge by turning off the P W M charge F E T s. F ig ure 17 sum m arizes the operation. VREF

VREF

CHARGE SUSPENDED

CHARGE SUSPENDED VLTF VLTFH

VLTF VLTFH

TEMPERATURE RANGE TO INITIATE CHARGE

TEMPERATURE RANGE DURING A CHARGE CYCLE

VHTF VTCO

CHARGE SUSPENDED

CHARGE SUSPENDED GND

GND

Figure 17. TS Pin, Thermistor Sense Thresholds A ssum ing a 103A T N T C therm istor on the battery pack as show n in F igure 1, the values of R T 1 and R T 2 ca n be determ ined by using E quation 7 and E quation 8: ! 1 1 " VVREF # RTHCOLD # RTHHOT # % $ & ' VLTF VTCO ( RT2 = !V " !V " RTHHOT # % VREF $ 1& $ RTHCOLD # % VREF $ 1& ' VLTF ( ' VTCO ( (7)

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VVREF !1 VLTF RT1 = 1 1 + RT2 RTHCO LD

(8)

VREF

RT1

bq24650 TS

RTH 103AT

RT2

Figure 18. TS Resistor Network

CHARGE ENABLE M P P S E T is used to disable or enable the ch arge process. A voltage above 175m V on this pin enables ch a rg e , provided all other conditions for charge are m et (see the Enabling and Disabling Charge section). A vo lta g e below 75m V on this pin also resets all tim ers and fault conditions.

INDUCTOR, CAPACITOR, AND SENSE RESISTOR SELECTION GUIDELINES T he bq24650 provides internal loop com pensation. W ith this schem e, the best stability occurs w he n the LC resonant frequency, f o , is approxim ately 12kH z – 17kH z for the bq24650. T able 1 provides a sum m ary of typical LC com ponents for various charge currents. Table 1. Typical Inductor, Capacitor, and Sense Resistor Values as a Function of Charge Current CHARGE CURRENT

0.5A

1A

2A

4A

8A

10A

O u tp u t inductor low

22 µH

15 µH

10 µH

6.8 µH

3.3 µH

3.3 µH

O u tp u t ca p a cito r C O

7 µF

10 µF

15 µF

20 µF

40 µF

40 µF

S e n se resistor

80 m ȍ

40 m ȍ

20 m ȍ

10 m ȍ

5 mȍ

4 mȍ

CHARGE STATUS OUTPUTS T he open-drain S T A T 1 and S T A T 2 outputs in dicate various charger operations as listed in T able 2. T hese sta tu s pins can be used to drive LE D s or com m unicate w ith the host processor. N ote that O F F indicates that the open-drain transistor is turned off. Table 2. STAT Pin Definition for bq24650 CHARGE STATE

STAT1

STAT2

C h a rg e in p rog ress

ON

OFF

C h a rg e com plete

OFF

ON

C h a rg e suspend, o ve r-vo lta g e , sle e p m o d e , b a tte ry a b sent

OFF

OFF

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BATTERY DETECTION F or applications w ith rem ovable battery packs, the bq24650 provides a battery absent detection sch e m e to reliably detect insertion or rem oval of battery packs. POR or RECHARGE

The battery detection routine runs on power up, or if VFB falls below VRECH due to removing a battery or discharging a battery

Apply 8mA discharge current, start 1s timer

VFB < VLOWV

No

Yes

1s timer expired

No

Yes

Battery Present, Begin Charge

Disable 6mA discharge current

Enable 125mA Charge, Start 0.5s timer

VFB > VRECH

Yes

Disable 125mA Charge

No

0.5s timer expired

No

Yes

Battery Present, Begin Charge

Battery Absent

Figure 19. Battery Detection Flowchart O nce the device has pow ered up, a 6-m A discharge current is applied to the S R N term inal. If the battery vo lta g e falls below the LO W V threshold w ithin 1 seco nd, the discharge source is turned off, and the charger is turned on at low charge current (125m A ). If the battery voltage gets up above the recharge threshold w ithin 500m s, there is no battery present and the cycle restarts. If either the 500m s or 1 second tim er tim e out before the respective thresholds are hit, a battery is detected and a charge cycle is initiated.

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Battery not detected VREG VRECH (VWAKE)

Battery inserted

VLOWV (VDISCH)

Battery detected

tLOWV_DEG

tWAKE

tRECH_DEG

Figure 20. Battery Detect Timing Diagram C are m ust be taken that the total output capacitance at the battery node is not so large that the discharge cu rre n t source cannot pull the V F B voltage below the LO W V threshold during the 1 second discharge tim e. T he m axim um output capacitance can be calculated according to E quation 9: ! tDISCH I CMAX = DISCH " R # 0.5 ! $1+ 2 % & R1 ' (9) W here C M A X is the m axim um output capacitance, I D IS C H is the discharge current, t D IS C H is the discharge tim e, and R 2 and R 1 are the voltage feedback resistors from the battery to the V F B pin. T he 0.5 factor is the difference betw een the R E C H A R G E and the LO W V thresholds at the V F B pin. Example F or a 3-cell Li+ charger, w ith R 2 = 500kȍ, R 1 = 100kȍ (giving 12.6V for voltage regulation), I D IS C H = 6m A , t D IS C H = 1 second. 6 mA ! 1 sec CMAX = = 2000 μF # 500 k" $ 0.5 ! %1+ & ' 100 k" ( (10) B ased on these calculations, no m ore than 2000 µF should be allow ed on the battery node for proper operation of the battery detection circuit.

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Component List for the Typical System Circuit in Figure 1 PART DESIGNATOR

QTY

DESCRIPTION

Q 1, Q 2

2

N -channel M O S F E T , 40 V , 10 A , P ow erP A K S O -8, V ishay-S iliconix, S i7288

D2

1

D iode, D ual S ch o ttky, 30 V , 200 m A , S O T 23, F a irch ild , B A T 54C

D3, D4

2

L E D D iode, G re e n , 2.1V , 20m A , LT S T -C 190G K T

RSR

1

S e n se R esistor, 2 0 m ȍ, V ishay-D ale, W S L1206R 0200D E A

L1

1

In d u cto r, 1 0 µH , 7 A , V ishay-D ale IH LP -2525C Z

C6, C8

2

C apacitor, C eram ic, 10 PF , 35 V , 20% , X 7R , 1210, P anasonic

C9

1

C apacitor, C eram ic, 4.7 PF , 35 V , 20% , X 7R , 1210, P anasonic

C2, C3, C4

3

C apacitor, C eram ic, 1 PF , 35 V , 10% , X 7R , 0805, K em et

C5, C7

2

C apacitor, C eram ic, 0.1 PF , 35 V , 10% , X 7R , 0805, K em et

C1

1

C apacitor, C eram ic, 2.2 PF , 35V , 10% , X 7R , 1210, K em et

C10

1

C apacitor, C eram ic, 22 pF , 35V , 10% , X 7R , 0603 K em et

R1

1

R esistor, C hip, 1 0 0 kȍ, 1/16W , 0.5% , 0402

R2, R3

2

R esistor, C hip, 4 9 9 kȍ, 1/16W , 0.5% , 0402

R4

1

R esistor, C hip, 3 6 kȍ, 1/16W , 0.5% , 0402

R9

1

R esistor, C hip, 5 .2 3 kȍ, 1/16W , 1% , 0402

R10

1

R esistor, C hip, 3 0 .1 kȍ, 1/16W , 1% , 0402

R7, R8

2

R esistor, C hip, 1 0 kȍ, 1/16W , 5% , 0402

R6

1

R esistor, C hip, 1 0 ȍ, 1/4W , 5% , 1206

R5

1

R esistor, C hip, 2 ȍ, 1W , 5% , 2012

D1

1

D iode, S ch o ttky R e ctifier, 40V , 10A , P D S 1040

Q3

1

N -C hannel M O S F E T , 60V , 115m A , S O T -23, 2N 7002D IC T

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APPLICATION INFORMATION INDUCTOR SELECTION T he bq24650 has a 600-kH z sw itching frequency to allow the use of sm all inductor and capacito r va lu e s. Inductor saturation current should be higher than the charging current (I C H G ) plus half the ripple current (I R IP P LE ): ISAT ! ICHG +(1/2)IRIPPLE (11) Inductor ripple current depends on input voltage (V IN ), duty cycle (D = V O U T /V IN ), sw itching frequency (fs), and inductance (L): V ! D ! (1 " D) IRIPPLE = IN fs × L (12) T he m axim um inductor ripple current happens w ith D = 0.5 or close to 0.5. U sually inductor ripple is designed in the range of 20% to 40% of the m axim um cha rging current as a trade-off betw een inductor size and efficiency for a practical design.

INPUT CAPACITOR T he input capacitor should have enough ripple current rating to absorb input sw itching ripple current. T he w o rst case R M S ripple current is half of the chargin g current w hen duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then the w orst case capacitor R M S current I C IN occurs w here the duty cycle is closest to 50% and can be estim ated by the follow ing equation: ICIN ! ICHG " D " (1 # D)

(13)

A low E S R ceram ic capacitor such as X 7R or X 5R is preferred for the input decoupling capacitor and sh o u ld be placed as close as possible to the drain of the high-side M O S F E T and source of the low -side M O S F E T . T he voltage rating of the capacitor m ust be higher than the norm al input voltage level. A 25V rating or higher capacitor is preferred for a 20V input voltage . A 20PF capacitance is suggested for a typical 3A to 4A ch a rg in g current.

OUTPUT CAPACITOR T he output capacitor also should have enough ripple current rating to absorb output sw itching ripple curre n t. T he output capacitor R M S current I C O U T is given as: I ICOUT ! RIPPLE " 0.29 # IRIPPLE 2 # 3 (14) T he output capacitor voltage ripple can be calculated as follow s: #VO $

VOUT ! V & 1 % OUT 2 & VIN 8LCfs (

" ' ' )

(15)

A t certain input/output voltages and sw itching frequencies, the voltage ripple can be reduced by incre a sin g the output filter inductor and capacitor values. T he bq24650 has an internal loop com pensator. T o achieve good loop stability, the resonant frequency of the output inductor and output capacitor should be designed betw een 12 kH z and 17 kH z. T he preferred ce ra m ic capacitor has a 35V or higher rating, X 7R or X 5R . C eram ic capacitors show a de-bias effect. T his effect reduces the effective capacitance w hen a dc-bias vo lta g e is applied across a ceram ic capacitor, as on the output capacitor of a charger. T he effect m ay le a d to a significant capacitance drop, especially for high voltages and sm all capacitor packages. S ee the m anufacturer’s datasheet about perform ance w ith a dc bias voltage applied. It m ay be necessary to choose a higher vo lta g e rating or nom inal capacitance value in order to achieve the required value at the operating point.

POWER MOSFETS SELECTION T w o external N -channel M O S F E T s are used for a synchronous sw itching battery charger. T he gate drivers are internally integrated into the IC w ith 6V of gate drive voltage. 30V or higher voltage rating M O S F E T s are preferred for 20V input voltage, and 40V or higher rating M O S F E T s are preferred for 20V to 28V input vo lta g e . Submit Documentation Feedback

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F igure-of-m erit (F O M ) is usually used for selecting a proper M O S F E T based on a tradeoff betw een co n d u ctio n loss and sw itching loss. F or a top-side M O S F E T , F O M is defined as the product of the M O S F E T 's on-resistance, R D S (o n ) , and the gate-to-drain charge, Q G D . F or a bottom -side M O S F E T , F O M is defined as the product of the M O S F E T 's on-resistance, R D S (on) , and the total gate charge, Q G . FOMtop ! RDS(on) " QGD ; FOMbottom ! RDS(ON) " QG

(16)

T he low er the F O M value, the low er the total pow er loss. U sually a low er R D S (on) has a higher cost w ith the sa m e package size. T op-side M O S F E T loss includes conduction loss and sw itching loss. It is a function of duty cycle (D = V O U T /V IN ), charging current (I C H G ), the M O S F E T 's on-resistance R D S (on) , input voltage (V IN ), sw itching frequency (F ), turn-on tim e (t on ) and turn-off tim e (t off ): 1 Ptop ! D " ICHG2 " RDS(ON) # " VIN " ICHG " (t on # t off ) " F 2 (17) T he first item rep resents the conduction loss. U sually M O S F E T R D S (O N ) increases by 50% w ith 100°C ju n ctio n tem perature rise. T he second term represents sw itching loss. T he M O S F E T turn-on and turn-off tim es are given by: Q Q t on ! SW ; t off ! SW Ion Ioff (18) w here Q S W is the sw itching charge, I on is the turn-on gate driving current, and I off is the turn-off gate driving current. If the sw itching charge is not given in the M O S F E T datasheet, it can be estim ated by gate-to-drain charge (Q G D ) and gate-to-source charge (Q G S ): 1 QSW ! QGD " # QGS 2 (19) T he gate driving current total can be estim ated by the R E G N voltage (V R E G N ), M O S F E T plateau volta g e (V P L T ), total turn-on gate resistance (R on ), and turn-off gate resistance (R off ) of the gate driver: VREGN ! Vplt Vplt Ion " ; Ioff " Ron Roff (20) T he conduction loss of the bottom -side M O S F E T is calculated w ith the follow ing equation w hen it operates in synchronous continuous conduction m ode: Pbottom ! (1 " D) # ICHG2 # RDS(ON)

(21)

If the S R P -S R N voltage decreases below 5m V (the charger is also forced into non-synchronous m ode w h e n the average S R P -S R N voltage is low er than 1.25m V ), the low -side F E T is turned off for the rem ainder of the sw itching cycle to prevent negative inductor cu rrent. A s a result, all of the freew heeling current goes through the body diode of the bottom -side M O S F E T . T he m axim um charging current in non-synchronous m ode can be up to 0.9A (0.5A typ) for a 10-m ȍ chargin g cu rre n t sensing resistor, considering the IC tolerance. C hoose a bottom -side M O S F E T w ith either an internal S chottky or body diode capable of carrying the m axim um non-synchronous m ode charging current. M O S F E T gate driver pow er loss contributes to dom inant losses on the controller IC , w hen the buck co n ve rte r is sw itching. C hoosing a M O S F E T w ith a sm all Q g_total reduces pow er loss to avoid therm al shutdow n. PICLOSS_Driver ! VIN " Qg_total " fs

(22)

W here Q g _ tota l is the total gate charge for both the upper and low er M O S F E T s at 6V V R E G N .

INPUT FILTER DESIGN D uring adapter hot plug-in, the parasitic inductance and the input capacitor from the adapter cable form a se co n d order system . T he voltage spike at the V C C pin m ay be beyond the IC m axim um voltage rating and dam age the IC . T he input filter m ust be carefully designed and tested to prevent an over-voltage event on the V C C pin.

22

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T here are several m ethods to dam ping or lim iting the over-voltage spike during adapter hot plug-in. A n electrolytic capacitor w ith high E S R as an input capacitor can dam p the over-voltage spike w ell below the IC m axim um pin voltage rating. A high current ca pability T V S Z ener diode can also lim it the over-voltage le ve l to an IC safe level. H ow ever, these tw o solutions m ay not be low est cost or sm allest size. A cost effective and sm all size solution is show n in F igure 21. R 1 and C 1 are com posed of a dam ping R C netw ork to dam p the hot plug-in oscillation. A s a result, the over-voltage spike is lim ited to a safe le ve l. D 1 is used for reverse voltage protection for the V C C pin. C 2 is the V C C pin decoupling capacitor and it sh o u ld be placed as close as possible to the V C C pin. R 2 and C 2 form a dam ping R C netw ork to further protect the IC from high dv/dt and high voltage spike. T he C 2 value should be less than the C 1 value so R 1 can dom inant the equivalent E S R value to get enough dam ping effect for hot plug-in. R 1 and R 2 m ust be sized enough to handle in-rush current pow er loss according to the resistor m anufacturer’s datasheet. T he filter com pone n t va lu e s alw ays need to be verified w ith a real application. D1

Adapter Connector

R2(1206) 4.7 - 30 !

R1(2010) 2!

VCC pin

C1 2.2 "F

C2 0.1 - 1 "F

Figure 21. Input Filter

MPPT TEMPERATURE COMPENSATION A typical solar panel com prises of alot of cells in a series connection, and each cell is a forw ard-biased p-n junction. S o, the open-circuit voltage (V O C ) of a solar cell has a tem perature coefficient that is sim ila r to a com m on p-n diode, or about – 2m V /°C . A crystalline solar panel specification alw ays provides both open-circuit voltage V O C and peak pow er point voltage V M P . T he difference betw een V O C and V M P can be approxim ated as fixed and tem perature-independent, so the tem perature coefficient for the peak pow er point is sim ilar to that of V O C . N orm ally, panel m anufacturers specify the 25°C values for V O C and V M P , and the tem perature coe fficie n t for V O C , as show n in the follow ing figure.

Panel Voltage - V

VOC

VMP

5

15

25

35

45

55

TA - Free-Air Temperature - °C

Figure 22. Solar Panel Output Voltage Temperature Characteristics T he bq24650 em ploys a feedback netw ork to the M P P S E T pin to program the input regulation voltage. B ecause the tem perature characteristic for a typical so lar panel V M P voltage is alm ost linear, a sim ple solution for tracking this characteristic can be im plem ented by using an LM 234 3-term inal current source, w hich can create an easily program m able, linear tem perature dependent current to com pensate the negative tem perature coefficie n t of the solar panel output voltage.

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R21: 20Ω

VIN

Solar Panel

R20 2Ω C21 2.2!F

C21 0.47!F

LM234

VCC R3

I1 RSET

ISET

VREG R4

I2

MPPSET

bq24650

Figure 23. Feedback Network In the circuit show n in F igure 23, for the LM 234 tem perature sensor, 227 μV/ !K ISET = " Temp RSET

(23)

T hus, 0.0677V RSET

(24)

T he current node equation is, V V - VREG I2 = REG = I1 + ISET = IN + ISET R4 R3

(25)

T o have a zero tem perature coefficient on V R E G , d(VIN - VREG ) dI dI2 1 = × + SET = 0 dT dT R3 dT

(26)

ISET (25!C) =

! -dVIN /dT " 2mV × number of solar cells in series R3 = # $ = RSET × dI /dT 227μV % SET & VREG × R3 VMPPSET × R3 R4 = = # !VIN + R3 × ISET " - VREG 0.0677V $ % VMP (25°C) + R3 × & - VMPPSET RSET ( '

(27)

(28)

F or exam ple, given a com m on 18-cell solar panel that has the follow ing specified characteristics: O pen circuit voltage (V O C ) = 10.3V M axim um pow er voltage (V M P ) = 9V O pen-circuit voltage tem perature coefficient (V O C ) = – 38m V /°C A ppling the follow ing param eters into the equations of R 3 and R 4 : 1. T em perature coefficient for V M P (sam e as that of V O C ) of – 38m V /°C 2. P eak pow er voltage of 9V 3. M P P S E T reg ulation voltage of 1.2V A nd choosing R S E T = 1000ȍ. T he resistor values are R S E T = 1kȍ, R 3 = 167.4kȍ, and R 4 = 10.6kȍ. S electing standard 1% accuracy resistors and R S E T = 1kȍ, R 3 = 169kȍ, and R 4 = 10.7kȍ.

24

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PCB LAYOUT T he sw itching node rise and fall tim es should be m inim ized for m inim um sw itching loss. P roper layo u t of the com ponents to m inim ize the high frequency current path loop (see F igure 24) is im portant to prevent electrical and m agnetic field radiation and high frequency resonant problem s. T he follow ing is a P C B layout priority list for proper layout. Layout of the P C B according to this specific order is essential. 1. P lace input capacitor as close as possible to the sw itching M O S F E T supply and ground connections and use the shortest copper trace connection. T hese parts should be placed on the sam e layer of the P C B in ste a d of on different layers and using vias to m ake this connection. 2. T he IC should be placed close to the sw itching M O S F E T gate term inals, and the gate drive sign a l traces kept short for a clean M O S F E T drive. T he IC can be placed on the other side of the P C B of the sw itch in g M O S F E T s. 3. P lace the inductor input term inal as close as possible to the sw itching M O S F E T output term inal. M inim ize the copper area of this trace to low er electrical and m agnetic field radiation but m ake the trace w ide enough to carry the charging current. D o not use m ultiple layers in parallel for this connection. M inim ize parasitic capacitance from this area to any other trace or plane. 4. T he charging current sensing resistor sh ould be placed right next to the inductor output. R oute the se n se leads connected across the sensing resistor back to the IC in the sam e layer, close to each other (m inim ize loop area) and do not route the sense leads through a high-current path (see F igure 25 for K elvin co n n e ctio n for best current accuracy). P lace decoupling capacitor on these traces next to the IC . 5. P lace output capacitor next to the sensing resistor output and ground. 6. O utput capacitor ground connections need to be tied to the sam e copper that connects to the input ca p a cito r ground before connecting to system ground. 7. R oute analog ground separately from pow er ground and use a single ground connection to tie charg e r pow er ground to charger analog ground. Just beneath the IC use analog ground copper pour but avoid pow er pins to reduce inductive and capacitive noise coupling. C onnect analog ground to the G N D pin. U se the therm al pad as a single ground connection point to connect analog ground and pow er ground together, or use a 0-ȍ resistor to tie analog ground to pow er ground (therm al pad should tie to analog ground in this ca se ). A star-connection under the therm al pad is highly recom m ended. 8. It is critical that the exposed therm al pad on the backside of the IC package be soldered to the P C B ground. E nsure that there are sufficient therm al vias directly under the IC , connecting to the ground plane on the other layers. 9. D ecoupling capacitors should be placed next to the IC pins and m ake trace connection as short as possible. 10. T he num ber and physical size of the vias should be enough for a given current path. SW

L1

R1

High Frequency

VIN C1

Current Path

VBAT

BAT PGND

C2

C3

Figure 24. High Frequency Current Path

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Charge Current Direction R SNS To Inductor

To Battery

Current Sensing Direction To SRP and SRN pin Figure 25. Sensing Resistor PCB Layout

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PACKAGING INFORMATION Orderable Device

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(1)

Package Type Package Drawing

Pins

Package Qty

Eco Plan

(2)

Lead/ Ball Finish

MSL Peak Temp

(3)

Samples (Requires Login)

BQ 24650RVAR

A C T IV E

VQFN

RVA

16

3 000

G re en (R oH S & no S b/B r)

C U N IP D A U Leve l-2-2 60C -1 Y E A R

P urchase S am ples

B Q 24 65 0R V A T

A C T IV E

VQFN

RVA

16

2 50

G re en (R oH S & no S b/B r)

C U N IP D A U Leve l-2-2 60C -1 Y E A R

R eque st F re e S a m ple s

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T h e m a rketin g sta tu s valu e s a re de fin ed as fo llow s: ACTIVE: P ro d u ct d evice re co m m e n d ed for ne w d esign s. LIFEBUY: T I h as a n n o u n ce d th a t th e d evice w ill be disco ntin ue d, a nd a lifetim e-buy period is in effect. NRND: N ot reco m m e n d e d fo r n e w de sig ns. D evice is in prod uction to support existing custom ers, but T I does not recom m end using this part in a new design. PREVIEW: D e vice h as b e e n an no un ced bu t is n ot in p ro du ctio n. S a m p les m ay or m ay not be available. OBSOLETE: T I ha s disco n tin u e d th e p ro du ctio n o f the de vice . (2)

E co P la n - T h e p la n n e d e co -frie n d ly cla ssifica tio n : P b -F re e (R o H S ), P b -F re e (R o H S E xe m p t), o r G re e n (R o H S & n o S b /B r) - p le a se ch e ck http://w w w .ti.com /productcontent fo r th e la te st a va ila b ility in fo rm ation a nd a dd itio n a l p rod uct content details. TBD: T he P b -F re e/G re e n con versio n p la n h as n ot b ee n d efine d. Pb-Free (RoHS): T I's term s "Lead-F ree" or "P b-F ree" m ean sem iconductor products that are com patible w ith the current R oH S requirem ents for all 6 substances, including the requirem ent that le ad not exce ed 0 .1 % b y w eig h t in hom ogeneous m aterials. W here desig n e d to b e so ld e re d a t h ig h te m p e ra tu re s, T I P b -F ree p ro du cts are suita ble for use in specified lead-free processes. Pb-Free (RoHS Exempt): T his com ponent has a R oH S exem ption for either 1) lead-based flip-chip solder bum ps used betw een the die and package, or 2) lead-based die adhesive used betw een the die an d le ad fra m e. T h e co m p on en t is o the rw ise con sid ered P b-F re e (R oH S com patible) as defined above. Green (RoHS & no Sb/Br): T I defines "G reen" to m ean P b-F ree (R oH S com patible), and free of B rom ine (B r) and A ntim ony (S b) based flam e retardants (B r or S b do not exceed 0.1% by w eight in h o m o gen eo us m a teria l) (3)

M S L , P e a k T e m p . -- T h e M oistu re S e nsitivity Le vel ra tin g a ccording to the JE D E C industry standard classifications, and peak solder tem perature.

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Device

Package Package Pins Type Drawing

SPQ

Reel Reel A0 Diameter Width (mm) (mm) W1 (mm)

B0 (mm)

K0 (mm)

P1 (mm)

W Pin1 (mm) Quadrant

BQ 24650RVAR

VQFN

RVA

16

3000

330.0

12.4

3.75

3.75

1.15

8.0

12.0

Q1

BQ 24650RVAT

VQFN

RVA

16

250

180.0

12.4

3.75

3.75

1.15

8.0

12.0

Q1

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Package Drawing

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SPQ

Length (mm)

Width (mm)

Height (mm)

BQ 24650RVAR

VQFN

RVA

16

3000

367.0

367.0

3 5.0

BQ 24650RVAT

VQFN

RVA

16

250

210.0

185.0

3 5.0

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