Your Hot Ideas … Our Cool Solutions! IUT GEII May 31 2007 Patrizio Piasentin – Actel France Country Manager Cyril Carsalade - FAE
Actel Company Overview Established FPGA Supplier First product shipped - 1988 $191M in sales in 2006 63 consecutive quarters of Pro Forma profitability Strong balance sheet >$170 M cash, no debt More than 550 employees Fabless company #1 non volatile FPGA supplier 100% green and RoHS compliant
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The Challenges Facing Today’s System Designer Time to market and design costs driving Programmable System Chip (PSC) market cin >>X >>Y; for (;;) {cout X>>Y; }
MCU Suppliers
Analog Suppliers
LUT
Malleable (HW & SW) Mixed Signal PSC
FPGA Suppliers
ASIC Suppliers Your Hot Ideas … Our Cool Devices
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Fusion PCS with ARM7 Changes the competitive landscape Integrates analog, Flash, SRAM and FPGA with soft ARM7 IP core in a single chip Fusion and ARM7 unlock possibilities by increasing design flexibility and configurability while reduced power, footprint, board complexity and risk
Fusion ARM7 System Off-chip Memory SRAM or Flash
Cache Memory SRAM
NV Storage FLASH
CoreMP7 FPGA MPUOptimized / MCU
Flash FPGA
ARM7
Analog Interface
Power Mgmt
Clock Mgmt
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Discrete Analog
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Actel’s Key Market Segments Value-based FPGA Sub-$10 market System Cost effective
Programmable System Chip System developers need integrated functionality on a single chip Analog / Processing / User Flash
System Critical Where failure and tampering are not options SEU immune technologies
Nonvolatile technologies applied to three target market segments Your Hot Ideas … Our Cool Devices
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Actel Solutions Includes Enablers Software & Hardware Tools •Libero Integrated Design Environment •EDA Partners •Programming Solutions •Verification and Debug Solutions •Evaluation Boards
Intellectual Property •DirectCores •CompanionCores •Solution Partners •Free Evaluations
Support •Technical Support •Technical Training •Customer Portal •Knowledge Base
Services •Design Services •DO 254 Services •Prototyping Services •Programming Services
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Award Winning Products
2007 EE Times ACE Awards Finalist 2006 EDN “Hot 100 Products of Year” 2006 EE Times “Ultimate Products – Q3 2006” 2007 EE Times China ACE Awards Finalist 2006 ECN Technology Awards 2006 EE Times ACE Awards Finalist–Design Team 2006 Electronics Weekly Elektra Awards Finalist 2006 EDN China Leading Product Award 2006 EEPW Editor’s Choice Award “Best Embedded System Product” (China)
2006 Electron d’Or Award (France) 2006 IEC DesignVision Award 2005 EDN “Innovation of the Year” Award 2005 EDN “Hot 100 Products of Year”
2005 EDN “Hot 100 Products of Year” 2005 Electronic Products “Product of the Year”
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Actel Differentiators
FPGA Technologies Compared
Actel SRAM
Flash
Antifuse
1T 6T
Reprogrammable
Best of Both Worlds Reprogrammable & Nonvolatile
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2007 Roadshow
Nonvolatile
9
Actel Technology Advantages Single-chip offerings provide total cost advantage over competition
Inherently more secure than any other solution
All Actel devices function as soon as power is applied to the board
Power advantages over competition
Actel delivers a significant reliability advantage over SRAM-based devices Your Hot Ideas … Our Cool Devices
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Typical System Board Before Fusion Clock Clockchip chiprequire require because becauseFPGA FPGAhas has no nosource source
OSC. Clock Chip
RTC RTCto totrack trackreal real time timeand andtime timestamp stamp events events RTC Digital FPGA
Processor
PWM
EE22PROM PROM for fordata data logging logging
External Externalflash flash for forcode code
EEPROM
NV Storage
Memory
Memory
For Formotor motor control control ADC
Temp Monitor and Fan Cntrl
ADC ADCto tointerface interfaceto to “real “realworld” world” Your Hot Ideas … Our Cool Devices
CPLD
Power Seq. Current Monitor and Brown-out detect
Sequences Sequences and andmonitors monitors multiple multiplepower power supplies supplies CPLD CPLDfor for SRAM SRAM configuration configuration /supervisory /supervisory
Thermal Thermalmgt mgtIC IC for forfan fancontrol control 2007 Roadshow
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Typical System Board After Fusion
Processor FUS1ON PSC
Memory
Memory
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Total System Cost ProASIC3 Leadership SP3 & CYC 2
ProASIC3
Comparable
Comparable
Always
Not required
Clock Management
Often
Not required
Live at Power-Up CPLD
Often
Not required
Reset Controller
Sometimes
Not required
Configuration LDO
Very Often
Not required
Brownout detector
Very Often
Not required
Heat Sink / Cooling
Sometimes
Not required
FPGA Core LDO adder
Always
Not required
PCB AREA Penalty
Always
Not required
FPGA Unit Cost Configuration Memory Class 2 LAPU Penalty
Volatile SRAM Penalty
Total Bill of Materials Adder Up to 100% adder
No adder
There is also a support cost overhead Development and debug time Your Hot Ideas … Our Cool Devices
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Actel IGLOO Low Power Leadership Actel IGLOO is the lowest power solution
Low Power Mode 60KSG (nW/uLE) 500
CPLDs short of logic and features for same power budget
400 300
IGLOO wins on power AND features
200 100 0 Series2
XC2C512
LCMXO640C
QL1P100
AGL060
451
77
47
15
Other FPGAs not competitive
Device
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Temperature Effect MUST Consider Temperature effects when choosing your target FPGA Static Power at Temp (25C vs 85C) 1000 900
Spartan3 - 85C
800
Static Power (mW)
700 600 500 400 300
PA3/E - 85C
Spartan3 - 25C
200 100
PA3/E - 25C
0 0
5000
10000
15000
20000
25000
30000
35000
40000
45000
50000
LE (equiv.) Your Hot Ideas … Our Cool Devices
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Programmable Logic Technologies SRAM
SRAM
SRAM FPGA with boot (PROM or MCU)
Hybrid FPGAs/CPLDs – SRAM fabric loaded from NVM on chip PROM
SRAM FPGA
or MCU
NVM Hybrid FPGA/CPLD
NVM
EEPROM
Flash/Antifuse
SPLD/CPLDs – EEPROM
NVM FPGAs
EEPROM SPLD/CPLD
NVM FPGA
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Live at Power Up SRAM FPGA Example System using SRAM FPGA loaded from external Flash Power Up Sequence
Time
1.
Power On (applied)
0 ns
2.
Regulate power, clock
3.
Apply Reset and provide clocks to devices
4.
SPLD Address Memory for MCU
5.
Power Up (stable)
6.
Components initialized
7.
MCU wakes up and starts initializing
Reset Controller (CPLD)
ASSP
Clock Generation PLL/Dividers
MCU
100 µs
Config.
MCU operational
9.
FPGA configuration loaded from MCU
10.
FPGA operational
SRAM FPGA
Address/Data
Address/data Decode SPLD
Address/Data
Address/Data
8.
Xtal Osc.
Flash Memory >200 ms Your Hot Ideas … Our Cool Devices
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Live At power up (Level 0) Live After power up (Level 1) Live After system initialized (Level 2) 17
Live at Power Up Actel NVM FPGA Case Circuit showing design implementation using Actel Flash FPGA Clock Reset
Power Up Sequence
Time
1.
Power On (applied)
0 ns
2.
Regulate power, clock
3.
Actel FPGA is Live, I/Os active FPGA applies Reset and provides Clocks to devices
4.
FPGA initializes memory
5.
Power Up (stable)
6.
Components initialized
7.
MCU wakes up and starts initializing
Live After power up (Level 1)
8.
MCU is operational
Live After system initialized (Level 2)
50 µs
MCU
ASSP
Actel FPGA
Clock Source
Memory 100 µs
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Live At power up (Level 0)
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PLD Live At Power Up timing Family
Power-Up Time
LAPU
(est./test)
Classification
SPLD (EEPROM)
22V10
100us
0
CPLD (EEPROM)
MAX7000
100us
0
Hybrid CPLD
MAX II1
>2ms
1
>2ms
1
CoolRunner II Lattice FPGA
ispXPGA2
Xilinx FPGA
Spartan31 XC3S200
>200ms
2
Altera FPGA
Cyclone1
>200ms
2
Actel FPGA
ProASICPLUS
100us
0
Actel FPGA
ProASIC3
100us
0
Actel FPGA
Ax, Sx, Sx-A, Mx, eX
100us
0
Notes 1. Best Case conditions taken from datasheet 2. Based on the company statement on web site 3. Ramp up 1ms
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What is Over Building, Cloning and Reverse Engineering
Over Building Unscrupulous manufacturer buys standard parts (FPGAs) on the open market and over builds. Selling the extra inventory for profit with non of the support and design overhead.
Cloning A competitor makes a copy of the boot prom or intercepts the bit stream from the on-board processor and copies the code. If you have a bit stream in your design, your IP is very vulnerable to cloning.
Reverse Engineering A competitor copies a design by reconstructing a “schematic” or netlist level representation in the process, he understands how the design works and to improve it. Your Hot Ideas … Our Cool Devices
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ProASIC3/E Security Features Device Security Layers
Muti-layered approach to Security
Physical
Physical Flash under 7 Metal Layers. Virtually impossible to detect charge on Floating Gates There is NO readback mechanism on PA3 devices
Security Header
Password
Password FlashLock – 128 bit FlashLock password. Correct password is needed to modify security settings
Decryption
Decryption Bitstream can be encrypted in Libero and then decrypted using a built-in AES decryption core
Application
Application IP cores that provide AES or DES encryption or decryption of data can be programmed into the FPGA fabric. The on-chip FROM is very useful (and secure) to store keys for these user applications
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ProASIC3 Secure ISP Leadership Several security options exist
Libero Plain Text
AES Encryption
Option 1: FlashLock Security in effect Device programmed with plain text
(bypass) Source Cipher Text
Opt. 3
Opt. 2
Opt. 1
TCP/IP Internet
AES Decrypt
FROM
Option 2: Overbuilding Protection Device programmed in-house with an
AES key only, then shipped to a 3rd party manufacturer Final programming at untrusted site (contract manufacturer) using AESencrypted bit-stream
Option 3: Secure ISP Device can be reprogrammed remotely
using AES encrypted programming file for easy and secure field upgrades
Secure FROM programming FPGA Core
Same options as above Can be updated independently Your Hot Ideas … Our Cool Devices
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ASIC Alternatives Reliability & Liability FPGA users want ASIC reliability and not product liability
Oxide Insulation
Gate
Drain
SRAM FPGAs are unreliable?
Source
N+
N+
- - + -+ + - - + + -+ +
P Substrate Depletion Region
Dominant failure mechanism for SRAM FPGAs is Firm Errors at ALL altitudes
SRAM FPGAs Incoming neutron causes firm error in routing
SRAM FPGA FIT (Failure in Time) rate is 2 orders of magnitude higher than Industry norms ProASIC3 Flash FPGAs are Firm Error immune
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High Energy Neutron
Firm error leads to . . .
misrouted signal
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or missing signal
23
Neutron Effects on FPGA Configuration SRAM FPGAs are vulnerable to neutron upsets SRAM
Flash
Antifuse
1 1 0 1 1 0 0 1
A B
10
10
10
1 0
10
1 0
C
A B C
Q
A B C
Q
1 0
Q SRAM cells control function of logic cell. SRAM cells are active devices with low capacitance and are vulnerable to neutron upset
Flash cells connect to tieoffs and signal tracks. Flash cells store charge on a thin floating gate and are immune to neutron upset Your Hot Ideas … Our Cool Devices
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Antifuses control connections to tie-offs and signal tracks. Antifuses are passive devices and are immune to neutron upset 24
Firm Errors Have Serious Impact on SRAM FPGA Logic SRAM Look-Up Table configures logic cell to implement OR-3 logic 1 1 1 1 1 1 1
A B
10
10
10
1 0
Single bit error causes complete PERMANENT change in function
SRAM Look-Up Table configures logic cell to implement constant logic 1
0
1 1 1 1 1 1 1
A B
10
1 0
Neutron
C
10
10
1 0
10
1 0
C
1 0
1 0
Configuration SRAM
Q A B C
10
1
Q
1111111
A B C
Q
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2007 Roadshow
x x x
Vdd
Q
25
Automotive Examples Scenario An occupant sensing airbag system uses one FPGA One million systems are in service The table indicates system FIT rates and MTBF using a variety of FPGAs FPGA Logic Error Failure Rates in Autom otive System Xilinx Rosetta Xilinx XC2V6000 Xilinx XC2V3000 Xilinx XC2V1000
Sea Level 416,666,667 FITs MTBF (Hours) 2.40 200,236,672 FITs MTBF (Hours) 4.99 77,852,516 FITs MTBF (Hours) 12.84
5,000 Ft 2,281,746,032 MTBF (Hours) 1,096,534,154 MTBF (Hours) 426,335,208 MTBF (Hours)
iRoC Phase 2 FITs 0.44 FITs 0.91 FITs 2.35
Xilinx XC3S1000 Altera EP1C20 Actel APA1000 Actel AX1000
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Sea Level 2,393,001,555 FITs MTBF (Hours) 0.42 1,150,000,000 FITs MTBF (Hours) 0.87 447,122,862 FITs MTBF (Hours) 2.24 320,000,000 FITs MTBF (Hours) 3.13 460,000,000 FITs MTBF (Hours) 2.17 0 FITs MTBF (Hours) 0 FITs MTBF (Hours) -
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5,000 Ft 8,115,396,579 MTBF (Hours) 3,900,000,000 MTBF (Hours) 1,516,329,705 MTBF (Hours) 1,100,000,000 MTBF (Hours) 1,600,000,000 MTBF (Hours) 0 MTBF (Hours) 0 MTBF (Hours)
FITs 0.12 FITs 0.26 FITs 0.66 FITs 0.91 FITs 0.63 FITs FITs -
26
Neutron Test Results Summary – Configuration Failures Equivalent Functional Failure FIT Rates per Device FPGA
Technology
Ground-Level Applications
Commercial Aviation
Military Aviation
Sea Level
5,000 Ft
30,000 Ft
60,000 Ft
Actel AX1000 1M-Gate
0.15µm Antifuse
No Failures Detected
No Failures Detected
No Failures Detected
No Failures Detected
Actel APA1000 1M-Gate
0.22µm Flash
No Failures Detected
No Failures Detected
No Failures Detected
No Failures Detected
Actel A3P1000 1M-Gate
0.13µm Flash
No Failures Detected
No Failures Detected
No Failures Detected
No Failures Detected
Xilinx XC2V3000 3M-Gate
0.15µm SRAM
1,150 FITs
3,900 FITs
170,000 FITs
540,000 FITs
Xilinx XC3S1000 1M-Gate
90nm SRAM
320 FITs
1,100 FITs
47,000 FITs
150,000 FITs
Altera EP1C20 1M-Gate
0.13µm SRAM
460 FITs
1,600 FITs
67,000 FITs
220,000 FITs
Altera EP2C20 1M-Gate
90nm SRAM
700 FITs
2,400 FITs
103,000 FITs
330,000 FITs
Altera EP2S30 2M-Gate
90nm SRAM
1,500 FITs
5,200 FITs
225,000 FITs
710,000 FITs
FITs = number of errors in 109 hours
Acceptable FIT rates for commercial applications are < 100 Acceptable FIT rates for high-reliability applications are < 20 Your Hot Ideas … Our Cool Devices
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Motor control challenge Time to Market and Cost Regulation pressure (pollution) Customer pressure (oil consumption )
Sensors & Actuators Algorithm complexity # of process
uController performance required uController cost Time to design software
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Sensor N
$ uController
Actuator 1 Actuator 2
Parallel
Sensor 1 Sensor 2
Parallel
uController Real Time Issues
Sequential
Actuator M
Memory
Process 1 Process 2 Process P
Real Time issue Your Hot Ideas … Our Cool Devices
2007 Roadshow
Time
29
Vision: FPGA is uC companionchip Sensor 1 Sensor 2 Sensor N
uC
$
Actuator 1 Actuator 2 Actuator M
FPGA FPGA
$
Process 1 Process 2 Process P
NO Real Time issue Your Hot Ideas … Our Cool Devices
2007 Roadshow
Time
30
Reliable and low cost
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ProASIC3 The Production FPGA Technology Changes Flash Advantages
ProASIC3/E Typical Floorplan RAM/FIFO
PLL/CCC
VersaNets
VersaTile
Pro I/O
Charge Pumps FROM ISP AES NVM Decryption Your Hot Ideas … Our Cool Devices
2007 Roadshow
JTAG ISP 33
ProASIC3/E Key Features Industry’s Lowest Cost FPGA solution 130nm 7LM Flash-Based CMOS FPGA
Only FPGA with on-chip user Non-Volatile Flash Memory 1024 bits (128 x 8 pages) of On-Chip user NVM Flash
Only FPGA supporting ARM7 soft core with CoreMP7 Industry’s best FPGA ISP solution Fast single voltage - Flash ISP Secure FlashLock enabled read-back protection AES based secure In System Programming
Only FPGA with ASIC like features Fast, Single Chip, Live at Power Up, Firm Error Immune
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ProASIC3 Fine Grained Architecture Up to 75,264 tiles any of which can be any 3 input combinatorial gate, a latch or a D-FF with Enable
a
Data X3 pin 4
Clk X2 pin 3
All input signals can be inverted Easier technology mapping and netlist optimizations
Clr XC pin 5
a
a a a a
0 1
0 1 a
Y pin 1 F2 YL
0 1 a a
a
a a
a
Set/Reset/Enable X1 pin 2
Register intensive applications are handled easily
a
a 0 1 a a a a a a a a
a
a
a a
Your Hot Ideas … Our Cool Devices
a
a
Combinatorial : Any function of 3 inputs. 3 LUT equivalent A B C
a
Q
a
a
Sequential: D FLIP-FLOP With Enable and Set or Reset D Enable CLK Set or Reset
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Q
35
Clock Conditioning Circuitry
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ProASIC3/E PLL Specifications Each CCC contains a PLL PLL Specification • Input Frequency Range (fIN) = 1.5 to 350 MHz • Feedback Frequency Range (fVCO) = 1.5 to 350 MHz • Output Frequency Range (fOUT) = 24 to 350 MHz • Output Phase Shift = 0 °, 90 °, 180 °, and 270 ° • Output Duty Cycle = 50% ±2% or better • Low Output Jitter (max at 25° C) >Y; for (;;) {cout X>>Y; }
MCU Suppliers
Analog Suppliers
LUT
Programmable System Chip
FPGA Suppliers
ASIC Suppliers Your Hot Ideas … Our Cool Devices
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Fusion starts with ProASIC3… SRAM / FIFO FPGA Core
PA3
Digital I/O
PLL/CCC User FROM
Security
Charge Pumps
Clocking RTC, Xtal Osc.
Analog – to – Digital Converter Analog I/O
Embedded Flash Your Hot Ideas … Our Cool Devices
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Fusion – Programmable System Chip Changes the competitive landscape The world’s first mixed-signal FPGA Fusion unlocks creativity: New architecture provides configurability and new tools provide simplified design flow
Embedded Flash Memory
LUT Flash FPGA Fabric
Configurable Analog
Programmable System Chip Your Hot Ideas … Our Cool Devices
Integrated clock resources 2007 Roadshow
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Fusion – Unprecedented Integration Integrates across functional boundaries Based on ProASIC 3 130nm FPGA Same Security features as ProASIC 3 Typical System System Memory DRAM
Cache Memory SRAM
MPU / MCU
Analog Interface
Power Mgmt
NV Storage FLASH
FPGA / ASIC
Thermal Mgmt
Clock Mgmt
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Discrete Analog
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Embedded-flash Process Supports Integration Actel is in a unique position to integrate Analog, Flash, FPGA, Logic, SRAM and Soft MCU For analog integration High-voltage transistors Triple-well process
For nonvolatile storage integration Embedded flash memory
For SRAM integration High-performance CMOS
For programmable logic integration Flash-based FPGA fabric
For soft MCU integration AES-based security
Embedded flash process is the best technology for realworld programmable system-chip applications Your Hot Ideas … Our Cool Devices
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Fusion: Only FPGA with Analog! Successive Approximation Register (SAR) ADC Up to 12 bit or 600 Ksps ±6 Total Unadjusted Error (TUE) Internal reference
GPIO
Built in sample and hold
Analog Inputs
Ana Mux
MOSFET Outputs A/D
FLASH Memory
A3P FPGA Fabric (incl. SRAM, CCC/PLL, IO)
Increases accuracy of dynamic signals
Analog I/O
Xtal OSC, RC OSC, RTC, Vreg
± 12 V Tolerant Up to 30 channels input Current monitor block 2 mV resolution
Temperature monitor block 2 C calibrated 5 C w/o calibration
MOSFET Gate driver output JTAG Port
Programmable drive strength P and N channel devices
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Elements of Analog Block Analog Quad
Vcc (1.5V)
5 to 10 Quads/Device Voltage monitor block Current Monitor block Temperature monitor block Gate control/driver block
ADC
Pads AV0 AC0 AG0 AT0
Analog Quad0
ATRTN0 AV1 AC1 AG1 AT1 AV2 AC2 AG2 AT2
Analog Quad1 Analog Quad2
ATRTN1 AV3 AC3 AG3 AT3 AV4 AC4 AG4 AT4
Analog Quad3 Analog Quad4
16 Analog Mux (32 to 1)
ATRTN2
Selectable 8/10/12 bits Up to 32 input channels Up to 600K samples/sec Selectable reference voltage
AV5 AC5 AG5 AT5 AV6 AC6 AG6 AT6
Analog Quad5
ADC Digital out to FPGA
Analog Quad6
ATRTN4 AV7 AC7 AG7 AT7 AV8 AC8 AG8 AT8
Analog Quad7 Analog Quad8
ATRTN5 AV9 AC9 AG9 AT9
Analog Quad9 Temperature Monitor Internal Diode
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Fusion: Analog Quad – I/O Structure
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Fusion: Flash Features Flash array 2 Mbit (1 – 4 /device) Each 2 Mbit Array operates independently (controller) Independent JTAG access
GPIO
Very Flexible operation Analog Inputs
Ana Mux
MOSFET Outputs A/D
FLASH Memory
JTAG Port
x8, x16, and/or x32 FPGA interface Each supports multiple partitions Small page size Can be accessed by either on-chip or off chip resources
A3P FPGA Fabric (incl. SRAM, CCC/PLL, IO)
Xtal OSC, RC OSC, RTC, Vreg
Supports High performance 60 ns random access Pipelined 10 ns access of sequential memory addresses
Uses: EEPROM emulation, state saving, boot code, data storage
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Applications for flash Embedded Processor Code Storage 2 Mbit to 8 Mbit arranged in 1 to 4 independent blocks Suitable for embedded processor cores (i.e. Core8051)
ADC Calibration/Error Correction Characterize your analog datapath, compute correction factors, and store them in flash as a look-up table Provide several look-up tables for various temperature ranges
System Initialization Initialize ADC configuration, internal memory contents, and machine states at power-up
Data/Event Logging (Black Box) and State Saving Store system parameters for later analysis Save internal logic states before entering deep sleep mode Restore logic states during the wake-up process Record events and alarms Your Hot Ideas … Our Cool Devices
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Fusion: Comprehensive Clocking resources Fusion builds up clocking resources: On chip clock sources:
GPIO
Analog Inputs
Ana Mux
MOSFET Outputs A/D
A3P FPGA Fabric (incl. SRAM, CCC/PLL, IO)
CCCs (6) / PLLs (1 or 2) RC oscillator Crystal Oscillator
Real Time Counter (RTC)
Use Models Internal 100MHz RC oscillator ±1% over I-temp range
Crystal OSC circuit FLASH Memory
Xtal OSC, RC OSC, RTC, Vreg
32 KHz – 20 MHz
CCC/PLLs can multiply, divide, and phase shifts clock signals for user applications Sources include: crystal Osc,
JTAG Port
RC Osc, or external clock
RTC enables low power standby mode
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RC & Crystal OSC System Block Diagram
GND_OSC
100 MHz RC clock generator
VCC_OSC
Clock out to FPGA core
C
GLINT
R C
Crystal Oscillator
C External Or External Crystal RC
Xtal Clock Clock IOs
PLL/ CCC
GLA GLC
NoGlitch Mux
To core CLKOUT
From FPGA Core
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Voltage Regular (V-Reg) Runs from a single 3.3V supply Generates 1.5 V supply up to 500 mA
External pin on Fusion package
VDD33 VDD33
Uses external pass transistor
1.5V supply is external to the device and can be routed to Power FPGA Embedded Flash
PTBASE
1.5V Regulator
PTEM 1.5V out
PDVR
Single supply for both core and Embedded Flash Cannot be powered down independently
VDD33 1uA PUB
Power Up to 1
Configurable control includes: FPGA power down signal External wake up signal – push button, wake up signal… Internal wake up – RTC Your Hot Ideas … Our Cool Devices
Power Up/Down Toggle Control Switch
Low Power Triple Inverter
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RTC + Voltage Regul. => Low Power Voltage Regulator can be used to control 1.5V system power Sleep mode = RTC on with 1.5 V (FPGA off) Device will draw ~ 200 µA (OSC) Can wake with either internal signal (RTC) or external signal
Standby mode = RTC off + with 1.5 V (FPGA off) Device will draw ~10µA Needs external signal to wake up
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RTC + V-Reg = Low Power 40-bit Real-Time Counter and Match register Use for sleep/wake interval timer Use for real-time, watch-dog, service hours timer
V-Reg provides 1.5V power from 3.3V supply for FPGA and Flash blocks Standby mode = 3.3V on + RTC on + V-Reg (1.5 V for FPGA off)
Device will draw ~ 200 µA (OSC) Can wake with either internal signal (RTC) or external signal
Sleep mode = 3.3V on + RTC off + V-Reg (1.5 V for FPGA off)
JTAG TAP
Device will draw ~10µA Needs external signal to wake up
JTAG B.S.
Control/Status Reg
Match Reg
Start Up Voltage Regulator
Counter
Crystal Clock
Prescaler
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AFS I/Os Similar to A3P Bank selectable 3 Registers per I/O (Input, Output, and Enable) Multiple I/O Standard Support Bank 6
High-Speed 700Mb/s LVDS with External
Bank 1
Resistors LVPECL
Bank 2
HSTL1, SSTL2/3, GTL+, LVTTL, LVCMOS
Bank 0
Bank 3
Hot Swappable 1.5v - 3.3v Configurable DDR Send/Receive Mode
Bank 4
AFS
Analog IOs
Analog IOs Analog Slow Digital IOs
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Fusion Family
I/O: Single ended / Double ended (analog)
I/O
Analog
Memory
General
Part #
AFS090
90K System Gates 2,304 Tiles (D-FF) Yes Secure (AES) ISP 1 PLLs Globals 18 6 RAM blocks (512x9) 27 Kbits Total RAM 1Kbits FlashROM bits 1 Flash Memory Blocks Total Flash Memory 2 Mbits 5 Analog Quads 15 Analog Inputs 5 Output Gate Drivers I/O Types Analog / LVDS / Std+ 4 I/O Banks (+ JTAG) 75 Max Digital I/O Analog I/O 20 37/9 (16) QN108 60/16 (20) QN180 PQ208 75/22 (20) FG256 FG484 FG676
AFS250
AFS600
AFS1500
250K 6,144 Yes 1 18 8 36 Kbits 1Kbits 1 2 Mbits 6 18 6
600K 13,824 Yes 2 18 24 108 Kbits 1Kbits 2 4 Mbits 10 30 10
1,500K 38,400 Yes 2 18 60 270 Kbits 1Kbits 4 8 Mbits 10 30 10
Analog / LVDS / Std+
Analog / LVDS / Pro
Analog / LVDS / Pro
4 114 24
5 172 40
5 278 40
65/15 (24) 93/26 (24) 114/37 (24)
Your Hot Ideas … Our Cool Devices
2007 Roadshow
95/46 (40) 119/58 (40) 172/86 (40)
119/58 (40) 228/86 (40) 278/139 (40)
66
The Fusion Tools Vision Design Creation (HDL or C++) Import / Export applets (2006)
Synthesis / Compile
Instantiation & Interconnect
System Creation & Management
(SmartGen, Launch)
(SmartConnect 2006)
HW/SW Simulation
Models for All Chip Resources (Launch)
Silicon Debug Platform
HW/SW Debug in Silicon (Launch)
Your Hot Ideas … Our Cool Devices
2007 Roadshow
67
Fusion Starter Kit – Current View
Your Hot Ideas … Our Cool Devices
2007 Roadshow
68
Fusion PSC: Target Applications Power and temperature management Power sequencing with tracking control Smart battery charging Voltage, current, temperature monitors and alarms Fan and heat-element control and monitoring Intelligent Platform Management Interface (IPMI)
Motor and motion control Motor control – stepper, 3-phase and solenoid control Anti-lock brakes
System initialization and configuration Context save and restore Context switching System boot codes
Storage Program code storage EEPROM emulation Data acquisition and logging
Low power and clocking Control for sleep mode and wake-up Live at power-up clock generation, conditioning, and distribution Your Hot Ideas … Our Cool Devices
2007 Roadshow
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Fusion Flexibility: Power Management Applet Everything today’s system sequencers can do plus… FPGA gates – your design here… Event and alarm logging using on-chip flash for remote diagnostics Sequence system along with power management activities Enable devices, system buses, interfaces, memories etc. during power-up/down
Additional system management activities: Thermal monitoring and fan control Easy field changes of sequences or alarm levels use Fusion flash Upgradeable using spare I/Os and gates Support for ANY voltage from ±12V High precision through infinite supply ramp control No compromises
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2007 Roadshow
70
Fusion Stack: Simplifies Design Level 0 - Fusion smart peripherals FPGA Fabric
Peripherals are treated equally, whether hard-wired or soft IP
User Application
Level 1 - Fusion Smart Backbone Built-in control (soft IP) configures peripherals from flash memory Backbone is scalable to any number of peripherals or applets
Optional MCU (ARM or 8051) Fusion Applet 1
Fusion Applet 2
(i.e. power sequence)
(i.e. Thermal Mgmt)
Level 2 - Fusion applets
Fusion Applet 3
Control Fusion Smart Backbone
OSCs, RTC Flash Memory
ADC Analog I/O
Flash Memory
Application building blocks implementing specific functions Rapid deployment Applets can be rapidly combined to create large applications
Level 3 - User application Optional ARM7 or 8051 Verified and integrated (CoreConsole) Well-defined interface for external IP and tool integration
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2007 Roadshow
71
New Tools: SmartGen Peripheral Configurator New graphical productivity tools ADC sampling Digital low-pass filtering Threshold comparisons State filtering Analog input High current output Flash memory access (FlashPoint™)
Automatically connects FPGA, flash and analog to Smart Backbone
Your Hot Ideas … Our Cool Devices
2007 Roadshow
72
Actel Fusion is… The World’s First Mixed Signal FPGA The ultimate Programmable System Chip Introduces analog and flash to programmable logic
An excellent soft MCU platform The only single chip programmable soft 8051/ARM platform
An excellent alternative to mixed-signal ASIC Time to market, risk reduction, no NRE
Your Hot Ideas … Our Cool Devices
2007 Roadshow
73
Fusion PSC: Changing the Competitive Landscape
ASSP or Mixed-Signal ASIC
FPGA
Highly Integrated Application Optimized Secure Low Power Live at Power-up On-chip Flash Low Unit Cost Monolithic Nonvolatile Analog No NRE Configurable Rapid Prototyping Short Lead-time ISP Extendable/Flexible Your Hot Ideas … Our Cool Devices
2007 Roadshow
74
Actel IGLOO Low Power Flash FPGAs
Expectations and Reality Collide in the Portable Market -Apple: “… up to 20 hours of battery life - five more than before…” -Motorola: “…for most consumers, form factor is the crucial hook…” -Fuji: “…quick response times … 1.4 second startup…”
Your Hot Ideas … Our Cool Devices
-Xilinx: “…the industry has crossed a critical inflection point at 90nm, where performance competes with power and thermal budgets…” -Philips: “…ultra-thin leadless package allows designers flexibility to add more functionality into smaller spaces…”
2007 Roadshow
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Actel IGLOO Low Power Flash Family The low-power, high-density, reprogrammable ASIC alternative for portable apps Devices from 30K to 3 million system gates Lowest power 4x lower static power (5µW) than nearest competitor (19.8µW) More than 5x longer battery life in portable applications compared to leading devices Flexible low-power implementation options
The only low-power FPGA solution to support 1.2V Features meet application requirements Single chip Lowest total system cost Small footprint packages Your Hot Ideas … Our Cool Devices
2007 Roadshow
77
Portable Friendly Actel IGLOO FPGAs True Single Chip Single voltage Elimination of additional components and reduced board size
Small footprint packages CS196 8x8mm, 133 I/O, 0.5mm ball pitch array
QFN 132 8x8mm, 87 I/O, Three 0.5mm pad array
Reprogrammable – easy prototyping and updates no socket required
Your Hot Ideas … Our Cool Devices
2007 Roadshow
78
Igloo FPGAs Flexible System Implementation Flash*Freeze mode Power consumption as low as 5µW Enter/exit within 1µs via
Flash*Freeze pin
During Flash*Freeze No need to power off voltage Freezes incoming clocks and inputs Core registers and SRAM maintain
state ‘No’ power consumed by I/Os, JTAG pins, PLL
Low-power active mode Allows IGLOO to directly control system power Power consumption as low as 25µW (Static) Slow (e.g. 32KHz) or stop the clocks Part remains active in system
Sleep mode Your Hot Ideas … Our Cool Devices
2007 Roadshow
79
Actel’s IGLOO Power Modes Overview Mode
Vcci
Vcc Core Clocks To resume operation
Trigger
Active
On
On
On
On
None
-
Static Flash* Freeze Idle
On
On
On
On
External
On
On
On
Off
Deassert Flash*Freeze pin Initiate clock
Sleep
On
Off
Off
Off
Vcc Supply
External
Shutdown
Off
Off
Off
Off
Vcc and Vcci supplies
External
External
ULSICC macro can be used to reduce static/active power
Your Hot Ideas … Our Cool Devices
2007 Roadshow
80
Battery Life Experiment
IGLOO best in all power categories Sleep (low power) mode, static, dynamic
Your Hot Ideas … Our Cool Devices
2007 Roadshow
81
Cooling Considerations
Volatile SRAM Penalty
SRAM FPGA
IGLOO
Configuration LDO
Very Often
Not required
Brownout detector
Very Often
Not required
Heat Sink / Cooling
Sometimes
Not required
Always
Not required
Significant
No adder
FPGA Core LDO adder Total Power Adder
More support devices, more total power Heat dissipation Dynamic power savings, 1.2V for IGLOO Added Cost $1 per Watt of additional system cost (estimates)
Your Hot Ideas … Our Cool Devices
2007 Roadshow
82
Actel Libero IDE SmartPower
Advanced Power Analysis Analyze Block Power by Type, Instance or by Rail
Benefits Design-level power summary View detailed hierarchical reports of dynamic power consumption Average switching activity Ambient and junction temperature readings
I/O Enable Rate Estimation Models Percent of time-enabled outputs actively drive loads
Provides better power estimation
Your Hot Ideas … Our Cool Devices
2007 Roadshow
83
Reference Design - Low-power Storage Solution Functionality Bridge from processor bus to various storage interface Include WinCE device drivers
Processor Support ARM-based solutions
Storage Standards ATA6 and CE-ATA HDD Secure Digital SD 1.1/2.0 and MMC CompactFlash 3.0 CardBus 2.1/PCMCIA
Target Application Smart Phone, GPS and PDA Handheld & mobile storage
Software drivers, schematics, BOM and HDL code provided Turnkey important
Your Hot Ideas … Our Cool Devices
2007 Roadshow
84
Actel IGLOO Family Based on Actel’s 3rd generation Flash technology Support 1.2V to 1.5V (nominal) core operation
AGL030
Actel Igloo
AGL060
AGL125
AGL250
AGL600
AGL1000
AGLE600
AGLE3000
M7AGL250 *
M7AGL600 *
M7AGL1000 *
M7AGLE600 *
M7AGLE3000 *
Family Members
Tiles (D-FF)
768
1536
3072
6144
13824
24576
13824
75264
Ram K Bits
-
18
36
36
108
144
108
504
4608 bit blocks
-
4
8
8
24
32
24
112
PLLs
-
1
1
1
1
1
6
6
I/O
Std,HS
Std+
Std+
Std+/LVDS
Std+/LVDS
Std+/LVDS
Pro
Pro
I/O Banks (+ JTAG)
2
2
2
4
4
4
8
8
1.2V Typ. FlashFreeze (uW)
5
9
17
33
72
122
72
294
Static (uW)
25
30
38
60
99
149
111
333
Typ. Sleep (uW), Vcci=1.5V
7.5
7.5
7.5
13.5
13.5
13.5
27
27
QN132
81
80
84
87/19
VQ100
79
71
71
68/13
FG144
96
97
97/24
97/24
97/25
CS196
96
133
143/30
FG256
178/45
177/44
165/79
FG484
227/56
300/74
270/135
FG896
280/136 616/300
Your Hot Ideas … Our Cool Devices
2007 Roadshow
85
Pricing and Availability Actel IGLOO devices Immediate prototyping available with flash-based ProASIC3 family Evaluate using low-power Actel IGLOO in Q1 2007 Small footprint packages available (CS196 - 8x8mm) Pricing from $1.50 (250KU)
Software tools available September Reference designs Low-power storage solution application Available from PalmChip in September 2006
Additional reference designs in Q4 2006
Your Hot Ideas … Our Cool Devices
2007 Roadshow
86
Prototyping with ProASIC3 to IGLOO A3P030 A3P060 A3P125 A3P250 A3P600 Package AGL030 AGL060 AGL125 AGL250 AGL600 QN132 VQ100 FG144 TQ144 CS196 PQ208 FG256 FG484 FG896
√ √ N/A N/A N/A N/A N/A N/A N/A
A3P1000 A3PE600 A3PE3000 AGL1000 AGLE600 AGLE3000
N/A N/A N/A √ √ √ √ √ √ N/A N/A N/A N/A √ √ √ √ √ N/A N/A N/A N/A ProASIC3 only N/A N/A N/A Supported in IGLOO only N/A Supported in ProASIC3/E only N/A N/A PA3 only √ √ √ N/A N/A N/A √ √ √ N/A N/A N/A N/A N/A N/A
N/A N/A N/A N/A N/A N/A √ √
J Compatible J Package available for IGLOO only J Package available for ProASIC3 only Use ProASIC3 devices and starter kits to prototype for IGLOO Your Hot Ideas … Our Cool Devices
2007 Roadshow
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Summary Low-power flash-based FPGAs are well positioned to capture share in the portable market At 5µW, Actel’s new IGLOO family is THE low-power, high-density reprogrammable ASIC alternative The fully featured Actel IGLOO family is the best solution for portable electronics Lowest power at 5µW; delivers up to 5x longer battery life Single chip Only low-power FPGA solution to support 1.2V Quick and easy power control Small footprint Reprogrammability Lowest total system cost
Your Hot Ideas … Our Cool Devices
2007 Roadshow
88
IGLOO The Lowest Power FPGA
ASIC
SRAM FPGA
Single Chip Live at Power-Up Nonvolatile Lowest Power Secure Firm-Error Immune On-Chip NVM Low Unit Cost Low Total System Cost Flash*Freeze Technology No NRE Rapid Prototyping Low Production Lead Time In-System Programmable Your Hot Ideas … Our Cool Devices
2007 Roadshow
89
ARM7 in Fusion
Enabling Programmable Real-World Designs
Why Partner with ARM? ARM7 is the 32-bit embedded standard More than 1.2 Billion units shipped in 2004 ~75% market share The largest IP provider in the world
Huge hardware and software ecosystem Extensive third-party tool support for ARM Broad industry knowledge and experience with ARM New tools are developed first for the ARM architecture
ARM7 is the 8051 of the 32-bit embedded space
Your Hot Ideas … Our Cool Devices
2007 Roadshow
91
Actel and Partnership Actel and ARM partner to deliver a free license, soft ARM7TDMI core to the masses Collaborate to develop FPGA-optimized version of the ARM7 embedded processor Actel FPGAs with ARM7 are ideal for high-volume or cost-sensitive applications Low-cost alternative to ASICs Better SOC implementation solution
Your Hot Ideas … Our Cool Devices
2007 Roadshow
92
Why Fusion ARM? The real world is analog Growing requirement to move information from the analog domain to the digital to process it Increasing level of performance in electronics moving embedded processors from 8-bit to 32-bit Integration of analog, logic and memory functions into fewer devices for “real-world” system-level designs Comprehensive and intuitive design infrastructure support is critical to designer’s ability to get products to market on schedule Your Hot Ideas … Our Cool Devices
2007 Roadshow
93
Fusion PCS with ARM7 Changes the competitive landscape Integrates analog, Flash, SRAM and FPGA with soft ARM7 IP core in a single chip Fusion and ARM7 unlock possibilities by increasing design flexibility and configurability while reduced power, footprint, board complexity and risk
Fusion ARM7 System Off-chip Memory SRAM or Flash
Cache Memory SRAM
NV Storage FLASH
CoreMP7 FPGA MPUOptimized / MCU
Flash FPGA
ARM7
Analog Interface
Power Mgmt
Clock Mgmt
Your Hot Ideas … Our Cool Devices
Discrete Analog
2007 Roadshow
94
Only From Actel Actel is in a unique position to integrate Analog, Soft ARM7, Flash, SRAM, and FPGA Logic For analog integration High-voltage transistors Triple-well process
For soft ARM7 integration AES-based security with maximum usability
For nonvolatile storage integration Embedded flash memory
For SRAM integration High-performance CMOS
For programmable logic integration Flash-based FPGA fabric
Embedded flash process is the best technology for realworld ARM7 programmable system-chip solutions Your Hot Ideas … Our Cool Devices
2007 Roadshow
95
Fusion CoreMP7 Benefits Single chip solution Analog, ARM7, Flash, SRAM, FPGA all in one device Reduced power, footprint, board complexity Increased reliability
ARM7 industry-standard architecture Large volume of existing software programs and legacy code Speeds application and program development and reduces design risk No ARM7 license or royalty fees
Analog configurability
On-the-fly analog dynamic range selection Multiple configurable clocks sources and PLL
FPGA flexibility and fast time to market More flexible than 32-bit microcontrollers Designers can include the functionality they want and need Programmability makes bug fixes and field upgrades easy Your Hot Ideas … Our Cool Devices
2007 Roadshow
96
CoreAI - Analog Interface CoreAI brings CoreMP7 and Fusion together Configurable IP block (150-460 tiles) Simplifies Fusion analog interface to CoreMP7
Advantages for designers Parameterizable control of Fusion Analog Block (AB) and I/O Controlled by CoreMP7 via APB bus Flash Memory
CoreMP7 CoreMP7
Static Memory Static Memory Controller Controller
Interrupt Interrupt Controller Controller
Fusion Hardware
AHB
AHB2APB AHB2APB bridge bridge APB
UART UART
Watchdog Watchdog
Timers Timers
Your Hot Ideas … Our Cool Devices
GPIO GPIO
2007 Roadshow
CoreAI
AB
Analog I/O
RTL IP Components
AB is logically but not physically implemented inside of CoreAI
97
SmartGen with CoreAI Analog System Builder Configure the Fusion Analog Block Set ADC system clock and resolution for each peripheral Outputs as acm.mem file
CoreConsole Imports acm.mem CoreAI uses the acm.mem file to write ACM at initialization Can also configure AB without using SmartGen Your Hot Ideas … Our Cool Devices
2007 Roadshow
98
New Tools: CoreConsole IP Deployment Platform A complete design in three clicks Click - Add parts Add IP to design from list of available IP
Click - Design Configure and stitch IP Can be done in design or schematic window
Click - Generate Generates IP (design) RTL and other output items (test benches, etc.)
SPIRIT supported Structure for Packaging, Integrating and Re-using IP within Tool flows (SPIRIT) Your Hot Ideas … Our Cool Devices
2007 Roadshow
99
Fusion ARM Hardware Solution Implementation with Fusion IP and CoreMP7 Available using existing elements Interconnected through CoreGPIO
SmartGen used to configure Fusion IP Flash Memory
CoreMP7 CoreMP7
Static Memory Static Memory Controller Controller
Interrupt Interrupt Controller Controller AHB
Fusion Hardware
Flash Memory
AHB2APB AHB2APB bridge bridge
Fusion AB IP
APB
RTL IP Components
UART UART
Watchdog Watchdog
Timers Timers
GPIO GPIO
I/O
RAM
Your Hot Ideas … Our Cool Devices
2007 Roadshow
100
M7 Fusion Development Flow RealView or GNU Determine HW & SW Requirements
Develop/Edit SW Program
SW Design Fail
C Compile
SW Simulation & Debug
Dev Kit
Develop or Acquire User IP
Design Start
CoreConsole
Pass
Program SW to FPGA Device
Actel IP Vault
Development Board
Libero Configure IP Cores
Stitch System Together
Behavioral Simulation
Back-Annotate
Edit Edit Edit Sub-Block Sub-Block IP Sub-Block IP IP & Testbench
Layout
Fail
SW Debug & Coverification
Pass
Design Complete
Program FPGA Device HW
HW Design
Fail Fail
Timing Driven Simulation Pass
Circuit Synthesis
Compile
Your Hot Ideas … Our Cool Devices
Encrypted Bitstream/STAPL
2007 Roadshow
101
M7 ProASIC3 Flash Devices
Broad selection of ARM-ready M7 devices M7 ProASIC3: 250k – 1M gates, up to 144kb SRAM & 288 I/O M7 ProASIC3E: 600k – 3M gates, up to 504kb SRAM & 616 I/O
Devices deliver innovative ProASIC3 features FlashLockTM security and secure in-system programming Single-chip, live at power-up, firm-error immune Device Æ Package
M7A3P 250
M7A3P 400
M7A3P6 00
M7A3P10 00
M7A3PE 600
M7A3PE1 500
M7A3PE3 000
147/65
147/65
280/136
280/136
VQ100
68/19
FG144
97/37
97/24
97/24
97/25
PQ208
151/34
151/33
154/35
154/35
147/65
FG256
178/38
179/45
179/45
165/79
FG484
194/38
227/56
300/74
270/135
FG676
439/209
FG896
616/300
Note: The data in the table is the I/O / differential pairs available on the device in the package
Your Hot Ideas … Our Cool Devices
2007 Roadshow
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CoreMP7 in M7 Fusion No changes to CoreMP7 for ARM Fusion Optimized for size and speed in M7 Fusion FPGAs Two variants (with and without debug)
Maximum Usability CoreMP7 is user programmed to FPGA All CoreMP7 I/O accessible in the fabric Easy routing of user added IP
Easy User Implementation Firm macro implementation Preserves speed and size optimization Includes timing shell and BFM
Fully compatible with ARM7TDMI-S Implements full functionality CoreMP7 passes the ARM7 Instruction Validation Suite Your Hot Ideas … Our Cool Devices
2007 Roadshow
103
Single-Chip M7 Fusion Power Interface to the Real World Analog inputs ±12V Temp, current, voltage sensing ADC – up to 600KSPS, up to 12 bits On-the-fly analog dynamic range select High current outputs (PWM / FET)
M7AFS600-FG484
Single chip solution On chip FLASH and SRAM Secure flash FPGA fabric In System Programmable
On chip resources 13.5K-33.7K SRAM 512K-1M Flash 600K-1.5M system gates 32kHz to 20MHz Xtal OSC
M7 Fusion Devices Package
M7AFS600
M7AFS1500
PQ208
95/40
FG256
119/40
119/40
FG484
172/40
228/40 278/40
FG676
Note: The data in the table shows the digital I/Os / Analog I/Os available for the device in the package.
Your Hot Ideas … Our Cool Devices
2007 Roadshow
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Programme Universitaire CNFM/ACTEL Mise en place dès maintenant Distribution gratuite de la partie CAO Prix spécifiques pour des plateformes universitaires Contact CNFM Thierry Gil,
[email protected]
Your Hot Ideas … Our Cool Devices
2007 Roadshow
105
Low Cost University Kit
ProASIC3 Board (Fusion kit will be similar) Parallel Port Programmer Programming header for FlashPro3
2-Line LCD Display
Key Pad
Your Hot Ideas … Our Cool Devices
2007 Roadshow
106
ProASIC3 and Fusion kits Features and contents Contents of the University kit
ProASIC3 and Fusion University Kit features 16 × 2 alphanumeric LCD Programming Through parallel port cable Also through FlashPro3
Starter kit board FPGA parts ProASIC3 kit has A3P250-PQ208 Fusion Kit has AFS600-PQ208
6-key keyboard as 2 × 3 matrix
Parallel port cable
32 bidirectional I/Os (LEDs and DIP switches)
Power supply
Power-on reset circuit with reset key 1 on-board 40 MHz oscillator and 1 optional oscillator Socket for user expansion
Software CD including Libero IDE Gold with FlashPro software Training CD Documentation created by Reanu
** Fusion kit has Temperature sensor on board
Your Hot Ideas … Our Cool Devices
2007 Roadshow
107
ProASIC3 and Fusion Education kits
Development Boards: Starter Kits Pricing for Universities
Unit price (HT) of
Qrder
Unit price (HT) of Additional discounts for Volume purchase
Quantity
A3PE-EVAL-KIT
AFS-EVAL-KIT
University Kits
University Kits
1-9
114 €
148 €
-
10-24
108 €
142 €
2 Copies of Libero Platinum Free
25-49
103 €
137 €
5 Copies of Libero Platinum Free
50-100
98 €
132 €
10 Copies of Libero Platinum Free
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2007 Roadshow
108
A3PE-PROTO-KIT Prix unitaire : 515 € HT (1 cartes achetée, une carte gratuite) Descriptif : Starter kit ProAsic3, contient un A3PE600 sur socket, un programmateur FlashPro3, une licence Libero IDE Gold. Plus: Le Fpga monté sur socket est connecté à :
•2 connecteurs RJ45, LCD, au quartz, aux Leds, aux Bouton Poussoirs, au JTAG •Toutes les broches sont accessibles via des broches •Espace disponible pour « wrapper ».
COREMP7-1000-DEV-KIT-FP3 Prix : 690 € HT (1 cartes achetée, une carte gratuite) Descriptif : Starter kit ARM ProAsic3, contient un M7A3P1000 soudé, un programmateur FlashPro3, une licence Libero IDE Gold. Plus: Le Fpga est connecté à : •2 RJ45, 2 UART, 1 CAN, 1 USB •aux quartzs, aux Led, aux boutons poussoir, au JTAG •Mémoire 2MB de SRAM et 2MB de Flash •3 connecteurs 40 broches Le jeu « Riversi » fourni en design de démonstration
Your Hot Ideas … Our Cool Devices
2007 Roadshow
109
AFS-EVAL-KIT Prix : 460 € HT (1 carte achetée, une carte gratuite) Descriptif : Starter kit Fusion, contient un AFS600 soudé, un programmateur FlashPro3, une licence Libero IDE Gold. Plus: Le Fpga est connecté à : 1.Partie numérique : a.LCD, au quartz, aux Led, aux BP et au JTAG b.1 connecteur 40 broches
2.Partie analogique : a.potentiomètre, capteur de température, à la Led tricolore b.connecteur pour ventilateur, I/O analogique
3.Toutes les broches sont accessibles via des broches + espace pour « wrapper ». est disponible
SYSMGMT-DEV-KIT-FP3 Prix : 1265 € HT (1 carte achetée, une carte gratuite) Descriptif : Starter kit ARM Fusion, contient un M7AFS600 soudé, un A3P250 soudé, un programmateur FlashPro3, une licence Libero IDE Gold. Plus: Les FPGA sont connectés à : 1)M7AFS600 : a.Mémoire 4Mo de SRAM et 2Mo de Flash b.2 I2C/SMBus, RS232, RS485, RJ45, JTAG c.Ventilateur, Resistance 7.5Ω, Batterie Nimh, alimentation (9v) d.2 PCI, connecteur I/O + espace pour « wrapper » e.Gestion Alim ATX (connecteur I/O) + potentiomètre + capteur T° 2)A3P250: l’interface humaine (LCD, keypad, switch, LED)
L’A3P250 communique via RS232 avec le M7AFS.
Your Hot Ideas … Our Cool Devices
2007 Roadshow
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