User’s Manual (SMDK6410 Rev0.2) S3C6410X RISC Microprocessor July 24, 2008 REV 1.0
Confidential Proprietary of Samsung Electronics Co., Ltd Copyright © 2008 Samsung Electronics, Inc. All Rights Reserved
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Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages.
"Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur. Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product
S3C6410X RISC Microprocessor SMDK6410 User’s manual, Revision 1.00 Copyright © 2008 Samsung Electronics Co.,Ltd. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics Co.,Ltd. Samsung Electronics Co., Ltd. San #24 Nongseo-Dong, Giheung-Gu Yongin-City Gyeonggi-Do, Korea 446-711
Home Page: http://www.samsungsemi.com/ E-Mail:
[email protected] Printed in the Republic of Korea
SMDK6410_USER’S MANUAL_REV 1.00
Revision History Revision No
Description of Change
Refer to
Author(s)
Date
0.00
- Initial Release (SMDK6410 Rev0.1)
-
O. P. Shin
May 16, 2008
0.10
- Second Release (SMDK6410 Rev0.2)
-
O. P. Shin
June 18, 2008
1.00
- Public Release
-
-
July 24, 2008
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Table of contents
SYSTEM OVERVIEW ................................................................................................................ 1 SMDK6410 OVERVIEW............................................................................................................. 2 Features ...................................................................................................................................................................................... 3 CIRCUIT DESCRIPTION ....................................................................................................................................................... 4 SMDK6410 CPU BOARD REAL VIEW................................................................................................................................. 7 SMDK6410 BASE BOARD REAL VIEW .............................................................................................................................. 9
SMDK6410 SYSTEM CONFIGURATIONS.............................................................................. 12 Clock Source SELECTION .................................................................................................................................................... 13 Boot Mode SELECTION ........................................................................................................................................................ 14 1. Muxed OneNAND Boot............................................................................................................................................... 14 2. AMD NOR/SROM Boot .............................................................................................................................................. 14 3. Modem Boot ................................................................................................................................................................. 15 4. Internal ROM Boot...................................................................................................................................................... 15 Configuration switch description in CPU Board .................................................................................................................. 16 CFG1: FOR USING CONTROLABLE REGULATOR .................................................................................................. 16 CFG4: FOR USING NAND/ONENAND........................................................................................................................... 18 CFG5: FOR USING MMC ................................................................................................................................................. 18 CFG6: FOR USING IIS 5.1 CHANNEL ........................................................................................................................... 19 Configuration switch description in BASE Board ................................................................................................................ 20 CFGB1: SROM BANK0 SELECTOR............................................................................................................................... 20 CFGB2: SROM BANK1 SELECTOR............................................................................................................................... 20 CFGB3: SROM BANK2 SELECTOR............................................................................................................................... 20 CFGB4: SROM BANK3 SELECTOR............................................................................................................................... 21 CFGB5: SROM BANK4 SELECTOR............................................................................................................................... 21 CFGB6: SROM BANK5 SELECTOR............................................................................................................................... 21 CFGB7: CF CARD TRANSFER MODE SELECTOR.................................................................................................... 22 CFG1: AUDIO CONNECTOR SELECTOR.................................................................................................................... 22 CFG2: AUDIO PORT SELECTOR................................................................................................................................... 23 CFG3: COM PORT2 CONTROL...................................................................................................................................... 24 CFG4: KEYPAD CONTROL............................................................................................................................................. 24 CFG5: WM8580 MASTER CLOCK SELECTOR........................................................................................................... 25 CFG6: ETHERNET SELECTOR...................................................................................................................................... 25 CFG7: NAND FLASH WRITE PROTECTION SELECTOR........................................................................................ 25 JUMPER SETTING CONFIGURATION ............................................................................................................................ 26 J1: SELECT DEBUGER (CPU BOARD) ........................................................................................................................ 26
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CONNECTORS ........................................................................................................................ 27 CPU BOARD............................................................................................................................................................................ 27 JTAG..................................................................................................................................................................................... 27 USB........................................................................................................................................................................................ 28 SPI ......................................................................................................................................................................................... 28 FPC cable for MIPI HSI ..................................................................................................................................................... 29 SD host (Ver2.0) SD/MMC interface ................................................................................................................................. 30 EXTERNAL ONE-NAND connector................................................................................................................................. 32 Camera Interface Connector .............................................................................................................................................. 33 ADC connector..................................................................................................................................................................... 33 PMIC connector................................................................................................................................................................... 34 BASE BOARD.......................................................................................................................................................................... 35 COMPOSITE & S-VIDEO Connector .............................................................................................................................. 35 LINE IN, MIC IN & SPEAKER OUT connector ............................................................................................................. 36 ETHERNET connector ....................................................................................................................................................... 37 UART interface .................................................................................................................................................................... 38 xD Picture Card Connector ................................................................................................................................................ 38 CF Card Slot ........................................................................................................................................................................ 39 PWM connector ................................................................................................................................................................... 39 external connector interface.................................................................................................................................................... 40 ROM BUS Interface ............................................................................................................................................................ 40 HOST/MODEM INTERFACE........................................................................................................................................... 42 EXTERNAL KEYPAD CONNECTOR ............................................................................................................................ 44 MODULE1 INTERFACE CONNECTOR (FOR GPS DAUGHTER BOARD)............................................................ 46 MODULE2 INTERFACE CONNECTOR (FOR MOBILE TV, HD RADIO DAUGHTER BOARD)....................... 48 MODULE3 INTERFACE CONNECTOR (FOR BLUETOOTH DAUGHTER BOARD) .......................................... 50 MODULE4 INTERFACE CONNECTOR (FOR AUDIO DAUGHTER BOARD) ...................................................... 52 MODULE5 INTERFACE CONNECTOR (FOR LCD BOARD) (with Touch Screen)................................................ 54
SMDK SCHEMATIC REVISION POINTS ................................................................................ 57 REVISION POINTS TABLE ................................................................................................................................................. 57
SMDK SCHEMATIC................................................................................................................. 58
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FIGURE INDEX Figure 1 SMDK6410 Function Diagram .......................................................................................................2 Figure 2 SMDK6410 Power Plane ...............................................................................................................5 Figure 3 SMDK6410 Board Diagram ...........................................................................................................6 Figure 4 SMDK6410 CPU Board Real View ................................................................................................8 Figure 5 SMDK6410 BASE Board Real View ............................................................................................11 Figure 6 JTAG Connector ..........................................................................................................................27 Figure 7 Dual USB ports & OTG port.........................................................................................................28 Figure 8 SPI Socket (IEEE1394 type)........................................................................................................28 Figure 9 FPC cable connector ...................................................................................................................29 Figure 10 SD card Socket ..........................................................................................................................31 Figure 11 External ONE-NAND B’d Connector .........................................................................................32 Figure 12 Camera Interface Connector .....................................................................................................33 Figure 13 ADC Connector..........................................................................................................................33 Figure 14 PMIC Connector ........................................................................................................................34 Figure 15 Composite & S-VIDEO Connector.............................................................................................35 Figure 16 Audio Line In, Mic In & Speaker Out Connector........................................................................36 Figure 17 Ethernet Socket .........................................................................................................................37 Figure 18 UART Sockets ...........................................................................................................................38 Figure 19 xD Picture Card Socket .............................................................................................................38 Figure 20 CF/ATA Interface Connector .....................................................................................................39 Figure 21 PWM out pins.............................................................................................................................39 Figure 22 External ROM Bus Connector ...................................................................................................40 Figure 23 Host/Modem Interface Connector..............................................................................................42 Figure 24 External Keypad Connector.......................................................................................................44 Figure 25 External Qwerty Keypad Connector ..........................................................................................45 Figure 26 Module1 Connector ...................................................................................................................46 Figure 27 Module2 Connector ...................................................................................................................48 Figure 28 Module3 Connector ...................................................................................................................50
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Figure 29 Module4 Connector ...................................................................................................................52 Figure 30 Module5 TFT LCD Connector (4.8”)..........................................................................................55
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ABOUT SMDK6410 BOARD SMDK6410 CPU and Base board revision number. CPU Board Version
Rev 0.2
Base Board Version
Rev 0.2
LCD Board Version
Rev 0.1
SYSTEM OVERVIEW SMDK6410 (6410 Development Kit) is a platform for code development of SAMSUNG's S3C6410X 16/32-bit RISC microcontroller (ARM1176JZF-S). S3C6410X is used in hand-held devices and general applications. The S3C6410X is a 16/32-bit RISC microprocessor, which is designed to provide a cost-effective, low-power capabilities, high performance Application Processor solution for mobile phones and general applications. To provide optimized H/W performance for the 2.5G & 3G communication services, the S3C6410 adopts 64/32-bit internal bus architecture. The 64/32-bit internal bus architecture is composed of AXI, AHB and APB buses. It also includes many powerful hardware accelerators for tasks such as motion video processing, audio processing, 2D graphics, display manipulation and scaling. An integrated Multi Format Codec (MFC) supports encoding and decoding of MPEG4/H.263/H.264 and decoding of VC1. This H/W Encoder/Decoder supports real-time video conferencing and TV out for both NTSC and PAL mode. Graphic 3D (hereinafter 3D Engine) is 3D Graphics Hardware Accelerator which can accelerate OpenGL ES 1.1 & 2.0 rendering. This 3D Engine includes two programmable shaders: one vertex shader and one pixel shader. The S3C6410 has an optimized interface to external memory. This optimized interface to external memory is capable of sustaining the high memory bandwidths required in high-end communication services. The memory system has dual external memory ports, DRAM and Flash/ROM/DRAM port. The DRAM port can be configured to support mobile DDR, DDR, mobile SDRAM and SDRAM. The Flash/ROM/DRAM port supports NOR-Flash, NAND-Flash, OneNAND, CF, ROM type external memory and mobile DDR, DDR, mobile SDRAM and SDRAM. To reduce total system cost and enhance overall functionality, the S3C6410 includes many hardware peripherals such as a Camera Interface, TFT 24-bit true color LCD controller, System Manager (power management & etc.), 4-channel UART, 32-channel DMA, 4-channel Timers, General Purpose I/O Ports, I2S-Bus interface, I2C-BUS interface, USB Host, USB OTG Device operating at high speed (480Mbps), 3-channel SD/MMC Host Controller and PLLs for clock generation. The ARM subsystem is based on the ARM1176JZF-S core. It includes separate 16KB Instruction and 16KB data caches, 16KB Instruction and 16KB Data TCM. It also includes a full MMU to handle virtual memory management. The ARM1176JZF-S is a single chip MCU, which includes support for JAVA acceleration. The ARM1176JZF-S includes a dedicated vector floating point coprocessor allowing efficient implementation of various encryption schemes as well as high quality 3D graphics applications. The S3C6410X adopts the de-facto standard AMBA bus architecture. These powerful, industry standard features allow the S3C6410X to support many of the industry standard Operating Systems. The SMDK6410 consists of S3C6410X, bootable (NAND, OneNAND, NOR FLASH), LCD interface, two serial communication ports, configuration switches, JTAG interface, status LEDs and etc.
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SMDK6410 OVERVIEW The SMDK6410 (6410 Development Kit) highlights the basic system-based hardware design which uses the S3C6410X. It can evaluate the basic operations of the S3C6410X and assist in developing codes. SMDK6410 is manufactured by MERITECH Co., Ltd and company website is www.mcukorea.com
Multimedia Acceleration
System Peripheral
ARM Core
RTC
ARM1176JZF-S
PLL x 3
I/D-Cache 16KB I/D-TCM 16KB 533/667MHz @ TBD V
Timer w/ PWM
Camera I/F Multi Format CODEC (H.264/MPEG4/VC1) NTSC, PAL TV out (with Image Enhancement)
Watch-Dog Timer
JPEG
DMA(32 ch)
2D Graphics
Keypad (8 x 8)
3D Graphics
Connectivity
X64 / 32 Multi – Layer AHB / AXI Bus
I2S
Memory Subsystem
I2C x 2 UART x 4
SRAM/ROM/NOR/ OneNAND
GPIO
Mobile SDRAM
IrDA v1.1
Mobile DDR SDRAM
SPI (Full Duplex) NAND Flash HIS (Modem I/F) USB OTG 2.0 USB Host 1.1
Power Management
TFT LCD Controller
Normal, Idle Stop, Sleep
Resolution typically 800x480 Color-TFT LCD
HS-MMC/SD AC97 / PCM Audio I/F
Figure 1 SMDK6410 Function Diagram
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FEATURES The features of SMDK6410 include: -
-
S3C6410X : 16/32 bit RISC microcontroller, ARM1176JZF-S X-tal operation or oscillator Boot Device : AMD 8Mbit 1EA (support halfword size boot ROM) SAMSUNG NAND flash 1EA (with Socket) SAMSUNG OneNAND 1EA (External Board Option) SAMSUNG 8Mbit SRAM 1EA Internal ROM Modem Boot (External Connector) SDRAM : Memory Port0: None Memory Port1: 128MB mDDR (64MB x 2, K4X51163) JTAG port TFT LCD & Touch panel interface ADC interface TV Out interface (S-Video, Composite) USB Host , USB OTG 2.0 interface MMC interface (Socket x 2) SPI interface 2 port UART interface IIS/AC97/PCM Interface : WM9713, WM8580 Camera Interface Ethernet Interface : 10/100Mbps CF/ATA interface Keypad interface Module Connector (M1 ~ M5) M1 (Module1): For GPS Daughter Board (UART0, SPI0) SMC673: Samsung GPD14B01 (SiRFSTAR III GSD3) (Optional) M2 (Module2): For Mobile TV Daughter Board (SPI1, IIC) or For HD Radio (SPI1, IIS for Module4) Mobile TV: Samsung S3C4F31 (TBD, Optional) HD Radio: SiPORT SD1010 (TBD, Optional) , Samsung (TBD, Optional) M3 (Module3): For Bluetooth Daughter Board (UART1, PCM for PMIC Audio Codec) Bluetooth: Atheros (TBD, Optional) M4 (Module4): For Audio Daughter Board (AC97, IIS, IIC) Audio: Wolfson WM8990 (Optional) M5 (Module5): For LCD Module LCD: Samsung WVGA 4.8” (Default) PMIC (200-FBGA Connector) Samsung S5M8750 Board (Optional): with Audio Codec Dialog DA9050 Board (Optional): with Audio Codec Wolfson WM8350 Board (Optional): with Audio Codec
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CIRCUIT DESCRIPTION The SMDK6410 is designed to test S3C6410 and develop software while hardware is being developed. Figure 3 highlights the SMDK6410's block diagram. POWER SUPPLY SMDK6410 is operated by 1.2V for Internal, 1.8V for Memory and 3.3V for Input/Output pad and several peripherals. SMDK6410 is supplied by 5V/3A DC Adaptor Power. The SMDK6410 has distributed power plane, with power going separately to the MCU and the main power plane. Due to this specific reason, power jumpers including JP01~JP27 on the CPU board, JP1~JP3 on the base board are inserted. U13
Base Board Power Plane
Regulator
Q1
FB3
Bead B_PWR_5V
M1 ~ 5
Module Connector
JACK11
DC-Adapter (5V/3A) Supply
FET (Switch)
AVDD_ext5V
Q3
FET (Switch)
U45
Regulator
VDD_18V
(1.8V)
VDD_CF
(3.3V)
VDD_Ethernet
(1.8V)
U34
VDD3.3V
Regulator
JP3
JP2 FB1 JP1
Bead
VDD3.3V
B_PWR_5V
VDD_EXHI AVDD_ext VDD_ext
(3.3V)
(3.3V)
(3.3V)
(5V)
Connector (JB1, JB2) PVCCAUX1
PVCCM2MTV
PVCCM3BT
M1
M2
M3
Module Connector
Module Connector
Module Connector
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Figure 2 SMDK6410 Power Plane
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Figure 3 SMDK6410 Board Diagram
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SMDK6410 CPU BOARD REAL VIEW
JTAG
USB OTG
USB
SPI
FPC cable Camera I/F
CFG3
CFG4 CFG6
CFG1 Batt. Con. DC Jack
CFG5 SW5
ONE-NAND
SD/MMC
CFG2
MMC - MOVINAND
(Top View)
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PMIC Connector 200-FBGA
(Bottom View) Figure 4 SMDK6410 CPU Board Real View
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SMDK6410 BASE BOARD REAL VIEW
LCD Module
CPU Board Base Board
(SMDK6410 CPU/Base/LCD Board)
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Module 5 Connector Module 2
Module 4
Connector
Connector
JOG Button
CFG4 CFG3 CFG2 CFG1 CFG6
CFGB7 CFGB6 CFGB5 Module 1
Module 3
CFGB4
Connector
Connector
CFGB3 CFGB2 CFGB1
xD card IrDA
CFG5
5.1ch SPK OUT NOR
MIC IN
Socket
LINE IN
EXT ROM BUS CFG7
DC Jack
NAND PWM
Socket MODEM I/F
(Base Top View)
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Power On Switch
CF/ATA I/F S-VIDEO
COMPOSITE
Ethernet 100Mbps
Ethernet 10Mbps
Ext._Keypad I/F
UART0
UART1/2/3 Ext. Qwerty KeyPad I/F
(Base Bottom View) Figure 5 SMDK6410 BASE Board Real View
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SMDK6410 SYSTEM CONFIGURATIONS Perform the following steps to use SMDK6410 board:
1. Set the Jumper J1 on CPU board Please refer to ‘JUMPER SETTING CONFIGURATION’ on page 26
2. Select the Clock source Please refer to ‘CLOCK SOURCE SELECTION’ , on page 13
3. Set the Regulator mode (Fixed or Controllable voltage , VDD_ARM & VDD_INT) Please refer to ‘CONFIGURATION SWITCH DESCRIPTION IN CPU BOARD CFG1’ , on page 16
4. Select the Boot mode and set by configuration switches ( There are 5 boot modes) Please refer to ‘BOOT MODE SELECTION’ , on page 14
5. Set the each IP which you want to use by CPU and Base boards configuration switches -
For MMC Please refer to ‘CONFIGURATION SWITCH DESCRIPTION IN CPU BOARD’ , on page 18
-
For CF CARD, LCD, Audio Controller, Audio Port(IIS,AC97,PCM), UART, IrDA, KEYPAD, Host I/F Please refer to ‘CONFIGURATION SWITCH DESCRIPTION IN BASE BOARD’ , on page 20
6. Check the Connector Please refer to ‘CONNECTORS’ , on page 27 -
JTAG, USB, HS-SPI, MIPI HSI, SD/MMC, External MMC & MOVI-NAND & CF-ATA, External OneNAND
-
Composite & S-video, Line in/ MIC in/ Speaker out, Ethernet, UART, Camera I/F, ADC, MMC, xD, PWM, External SPI, TFT LCD, Touch screen, External Rom bus, External Modem I/F, External LCD, External KEYPAD, Module 1 ~ 5.
Configuration Switch (DIP Switch)
1 ――→ 2 ――→ 3 ――→ 4 ――→
Off ――→On
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CLOCK SOURCE SELECTION EXTCLK or X-TAL can be selected for the S3C6410 system clock by setting the XOM[0] values. The Clock Source selection must be X-tal Clock (CFG3[1] on CPU Board). Description
CFG3[1] (XOM[0])
External Oscillator Clock
ON
X-tal Clock
OFF CPU
BASE
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BOOT MODE SELECTION 1. Muxed OneNAND Boot A.
Set CFG3 on CPU Board, Select OneNAND
B.
Set CFG4 on CPU Board, Select OneNAND
C. SMDK6410 support external OneNAND Board, Connect it on CON12 connecter on CPU Board Note. CFG3[6] must be set as “OFF” to use OneNAND CFG3[6:2] Description OneNAND (used External OneNAND B’d)
[6]
[5]
[4]
[3]
[2]
OFF
OFF
ON
ON
OFF
CFG4 Description OneNAND(CS2)
[4]
[3]
[2]
[1]
ON
ON
OFF
OFF CPU
BASE
2. AMD NOR/SROM Boot A.
Set CFG3 on CPU Board, Select Data width
B.
Set CFGB1 on Base Board, Select NOR flash CFG3[6:2] Description [6]
[5]
[4]
[3]
[2]
NOR Boot ( 8bit Data Width)
Don’t Care
OFF
ON
OFF
OFF
NOR Boot (16bit Data Width)
Don’t Care
OFF
ON
OFF
ON CPU
BASE
CFGB1[4:1] Description Connected NorFlash to Xm0CSn0
[4]
[3]
[2]
[1]
OFF
OFF
OFF
ON CPU
BASE
Note. NOR Boot is connected to Bank0. Only Nor Flash can be used for NOR Boot
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3. Modem Boot A.
Set CFG3 on CPU board to select Modem Boot
B.
Connect External Modem to JF2 Connector on Base board CFG3[6:2] Description
Modem Boot
[6]
[5]
[4]
[3]
[2]
Don’t Care
OFF
ON
ON
ON CPU
BASE
4. Internal ROM Boot A.
Set CFG3 on CPU board to select Internal ROM Boot
B.
Set J6, J7 and J8 on BASE board to select the booting device such as SD/MMC, OneNAND and NAND Flash CFG3[6:2] Description [6]
[5]
[4]
[3]
[2]
Internal ROM Boot for OneNAND
OFF
ON
ON
ON
ON
Internal ROM Boot for NAND
ON
ON
ON
ON
ON
Internal ROM Boot for SD/MMC
Don’t Care
ON
ON
ON
ON
Description
J8
J7
J6
SD/MMC CH0
1-2
1-2
1-2
OneNAND
1-2
1-2
2-3
Normal NAND, 512-byte page, 3 addr. Cycle
1-2
2-3
1-2
Normal NAND, 512-byte page, 4 addr. Cycle
1-2
2-3
2-3
Large Page NAND, 2K-byte page, 4 addr. Cycle
2-3
1-2
1-2
Large Page NAND, 2K-byte page, 5 addr. Cycle
2-3
1-2
2-3
Large Page NAND, 4K-byte page, 5 addr. Cycle
2-3
2-3
1-2
SD/MMC CH1
2-3
2-3
2-3
CPU
BASE
CPU
BASE
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CONFIGURATION SWITCH DESCRIPTION IN CPU BOARD CFG1: FOR USING CONTROLABLE REGULATOR CFG1 component is used to select default value of the VDD_ARM/INT. CFG1 Description [4]
[3]
[2]
[1]
VDD_ARM= 1.0V
Don’t Care
Don’t Care
ON
ON
VDD_ARM= 1.1V
Don’t Care
Don’t Care
ON
OFF
VDD_ARM= 1.2V
Don’t Care
Don’t Care
OFF
ON
VDD_ARM= 1.3V
Don’t Care
Don’t Care
OFF
OFF
VDD_INT= 1.0V
Don’t Care
ON
Don’t Care
Don’t Care
VDD_INT= 1.2V
Don’t Care
OFF
Don’t Care
Don’t Care
PWR Control Enable
ON
Don’t Care
Don’t Care
Don’t Care
PWR Control Disable
OFF
Don’t Care
Don’t Care
Don’t Care
Description of the Regulator Control Signal Latch Output Enable
XhiADDR9(GPL9), “H” => Output Enable
Latch Enable of the ARM Regulator
XhiADDR8(GPL8), “H” => Latch Enable
Latch Enable of the INT Regulator
XhiADDR10(GPL10), “H” => Latch Enable
Regulator Control Signal(VID0)
XEINT11(GPN11)
Regulator Control Signal(VID1)
XEINT11(GPN12)
Regulator Control Signal(VID2)
XEINT11(GPN13)
Regulator Control Signal(VID3)
XEINT11(GPN14)
Regulator Control Signal(VID4)
XEINT11(GPN15)
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LTC3714 (U7, U11) Voltage VID4
VID3
VID2
VID1
VID0
1.300V
0
1
0
0
1
1.250V
0
1
0
1
0
1.200V
0
1
0
1
1
1.150V
0
1
1
0
0
1.100V
0
1
1
0
1
1.050V
0
1
1
1
0
1.000V
0
1
1
1
1
0.975V
1
0
0
0
0
0.950V
1
0
0
0
1
0.925V
1
0
0
1
0
0.900V
1
0
0
1
1
0.875V
1
0
1
0
0
0.850V
1
0
1
0
1
0.825V
1
0
1
1
0
0.800V
1
0
1
1
1
0.775V
1
1
0
0
0
0.750V
1
1
0
0
1
0.725V
1
1
0
1
0
0.700V
1
1
0
1
1
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CFG2: Below table is when use PMIC Module Board. SW5
CFG2
JACK1 (DC)
CON3 CON4 (USB OTG) (Battery)
Power Off
X
X
X
Operation & Charging by DC
O
X
O
Charging by USB
X
O
O
X : Don't care
O : Insertion (Placement)
CFG3: Refer to clock source selection and boot mode selection chapter CFG4: FOR USING NAND/ONENAND CFG4 component is used for selecting NAND/OneNAND Controller (CS2). Using 4 switches in this component, appropriate Controller can be selected. CFG4 Description [4]
[3]
[2]
[1]
NAND(CS2)
OFF
OFF
ON
ON
OneNAND(CS2)
ON
ON
OFF
OFF
Note. CFG3[6] must be set as “OFF” to use OneNAND CFG3[6] must be set as “ON” to use NAND CPU
BASE
CFG5: FOR USING MMC CFG5 component is used to select MMC Port. Using 2 switches in this component, appropriate MMC can be selected. CFG5 Description [2]
[1]
Disconnect MMC Port to MMC Socket
ON
Don’t Care
MMC Port 0 to MMC Socket
OFF
ON
MMC Port 1 to MMC Socket
OFF
OFF CPU
BASE
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CFG6: FOR USING IIS 5.1 CHANNEL CFG6 component is used IIS Port. CFG6 Description [4]
[3]
[2]
[1]
Disconnect IIS 5.1Channel
OFF
OFF
OFF
OFF
Connect IIS 5.1Channel
ON
ON
ON
ON CPU
BASE
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CONFIGURATION SWITCH DESCRIPTION IN BASE BOARD CFGB1: SROM BANK0 SELECTOR CFGB1 component is used to select devices as SROM BUS I/F 0(Xm0CSn0). CFGB1 Description [3]
[2]
[1]
NOR (AMD) Flash
OFF
OFF
ON
SRAM
OFF
ON
OFF
External Device
ON
OFF
OFF CPU
BASE
CFGB2: SROM BANK1 SELECTOR CFGB2 component is used to select devices as SROM BUS I/F 1(Xm0CSn1). CFGB2 Description [4]
[3]
[2]
[1]
NOR (AMD) Flash
OFF
OFF
OFF
ON
SRAM
OFF
OFF
ON
OFF
Ethernet
OFF
ON
OFF
OFF
External Device
ON
OFF
OFF
OFF CPU
BASE
CFGB3: SROM BANK2 SELECTOR CFGB3 component is used to select devices as SROM BUS I/F 2(Xm0CSn2). CFGB3 Description [4]
[3]
[2]
[1]
NAND Flash
OFF
OFF
OFF
ON
XD Picture Card
OFF
OFF
ON
OFF
Ethernet
OFF
ON
OFF
OFF
External Device
ON
OFF
OFF
OFF CPU
BASE
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SMDK6410_USER’S MANUAL_REV 1.00
CFGB4: SROM BANK3 SELECTOR CFGB4 component is used to select devices as SROM BUS I/F 3(Xm0CSn3). CFGB4 Description [4]
[3]
[2]
[1]
NAND Flash
OFF
OFF
OFF
ON
XD Picture Card
OFF
OFF
ON
OFF
Ethernet
OFF
ON
OFF
OFF
External Device
ON
OFF
OFF
OFF CPU
BASE
CFGB5: SROM BANK4 SELECTOR CFGB5 component is used to select devices as SROM BUS I/F 4(Xm0CSn4). CFGB5 Description [4]
[3]
[2]
[1]
CF0
OFF
OFF
OFF
ON
NOR (AMD) Flash
OFF
OFF
ON
OFF
SRAM
OFF
ON
OFF
OFF
Ethernet
ON
OFF
OFF
OFF CPU
BASE
CFGB6: SROM BANK5 SELECTOR CFGB6 component is used to select devices as SROM BUS I/F 5(Xm0CSn5). CFGB6 Description [4]
[3]
[2]
[1]
CF1
OFF
OFF
OFF
ON
NOR (AMD) Flash
OFF
OFF
ON
OFF
SRAM
OFF
ON
OFF
OFF
Ethernet
ON
OFF
OFF
OFF CPU
BASE
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SMDK6410_USER’S MANUAL_REV 1.00
CFGB7: CF CARD TRANSFER MODE SELECTOR CFGB7 component is used to select CF transfer mode. CFGB7 Description [2]
[1]
Direct Mode
OFF
ON
Indirect Mode
ON
OFF CPU
BASE
Note. * Direct Mode: Mode which has Control signal for CF through the dedicated CF pin * Indirect Mode: Mode which has Control signal for CF through the EBI * Sequence for using CF 1. Turn ON CFGB5[1], CFGB6[1] 2. Turn ON CFG4[2] 3. Connect JP22[1] & JP22[2] in CPU Board
CFG1: AUDIO CONNECTOR SELECTOR CFG1 component is used to select direction of MIC, Line-In and Speaker to (from) Audio codec from (to) those audio connector. ON
OFF
[1] : Select Speaker (Note1)
WM9713/PMIC
WM8580
[2] : Select Mic
WM9713/PMIC
WM8580
[3] : Select LineIn
WM9713/PMIC
WM8580
CFG1
NOTE 1: There are 3 Speak Out components of WM8580, No 1 pin of CFG1 select only Front LR Speak out. CPU
BASE
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SMDK6410_USER’S MANUAL_REV 1.00
CFG2: AUDIO PORT SELECTOR CFG2 component is used to select S3C6410 Audio port. S3C6410 supports 2 audio channels; therefore IIS and one of AC97/PCM can be selected at the same time. Description CFG2
[1]
(Note1)
: Internal Path Selection
[2] Internal/External Port 0 Selection
[2] Internal/External Port 1 Selection [4] Reserved
(Note2)
ON
OFF
Port 0 : to WM9713(AC97)
Port 0 : to WM8580 SAIF(IIS/PCM)
Port 1 : to WM8580 SAIF(IIS/PCM)
Port 1 : to WM9713(AC97)
Turn On the Path that from Port 0 to internal Codecs
Turn Off the Path that from Port 0 to internal Codecs. If Codec Board is connected on Module Connector that uses port 0, Internal Codec path must be turned off.(Note3)
Turn On the Path that from Port 1 to internal Codecs
Turn Off the Path that from Port 1 to internal Codecs. If Codec Board is connected on Module 4 Connector that uses port 1, Internal Codec path must be turned off.
-
CPU
BASE
Note 1. * It is possible that One Audio Port is connected on WM9713 (AC97), the other on WM9713 (PCM/I2S), if the Board is modified. Note 2. * Default External Codec Module is Module 4. It is possible to use Module 2(Port 0) or Module 3(Port 1). Note 3. * If it is needed that External codec is connected on Module 4, It must be connect R48. Default R48 connection is off.
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SMDK6410_USER’S MANUAL_REV 1.00
CFG3: COM PORT2 CONTROL CFG3 component is used to control COM Port 2. CFG3 Description [4]
[3]
[2]
[1]
UART1
Don’t Care
Don’t Care
Don’t Care
OFF
UART2
OFF
OFF
OFF
ON
UART3
OFF
ON
ON
ON
IrDA(U2)
OFF
ON
Don’t Care
Don’t Care
IrDA(U3)
OFF
OFF
Don’t Care
Don’t Care CPU
BASE
CFG4: KEYPAD CONTROL CFG4 component is used to control Keypad. CFG4
ON
OFF
[1] : Column pin selection
MMC
Host I/F
[2] : Row pin selection
XEINT
Host I/F
[3] : Key Enable 1
Key Disable(Low 4x4)
Key Enable(Low 4x4)
[4] : Key Enable 2
Key Disable(High 4x4)
Key Enable(High 4x4) CPU
BASE
Note. * Column pin selection: Keypad’s Column pin and MMC’s Host I/F pin has muxed, therefore you must select one. * Row pin selection: Keypad’s Row pin has muxed with XEINT and Host I/F pin, therefore you must select one between the two.
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SMDK6410_USER’S MANUAL_REV 1.00
CFG5: WM8580 MASTER CLOCK SELECTOR CFG5 component change source of WM8580 Master clock. CFG5
DESCRIPTION
1–2
CDCLK of I2SMULTI Port is source of WM8580 Master clock
2–3
CDCLK of AUDIO Port 0 or Port1 is source of WM8580 Master clock.(NOTE) CPU
BASE
CPU
BASE
CPU
BASE
Note. * Selection of Port 0 and Port 1 is on CFG2.
CFG6: ETHERNET SELECTOR CFG6 is select LAN9115 or CS8900. CFG6
DESCRIPTION
1 – 2 (4 – 5)
Select LAN9115 (100Mbps)
2 – 3 (5 – 6)
Select CS8900 (10Mbps)
CFG7: NAND FLASH WRITE PROTECTION SELECTOR CFG7 is selected write protection function of NAND when power on. CFG5
DESCRIPTION
1 – 2 (4 – 5)
NAND is write protection when power on.
2 – 3 (5 – 6)
NAND is not written protection when power on. (Default)
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SMDK6410_USER’S MANUAL_REV 1.00
JUMPER SETTING CONFIGURATION J1: SELECT DEBUGER (CPU BOARD)
ARM core JTAG “XDBGSEL = GND” Peripheral JTAG “XDBGSEL = VDD_D” Note. * We are basically debugging by ARM core JTAG, #1 and #2 pin must be connected
26
SMDK6410_USER’S MANUAL_REV 1.00
CONNECTORS CPU BOARD JTAG Part Name: CON11 (CPU) VDD_D
R163
R164
NC/R1005 10K/R1005
VDD_D
R165
R166
10K/R1005
10K/R1005
[3] XTRSTn [3] XTDI [3] XTMS [3] XTCK [3] XRTCK [3] XTDO [2,3,6,16] XnRESET
R167
0/R1005
R169 470/R1005
R171
CON11 1 3 5 7 9 11 13 15 17 19
1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20
2 4 6 8 10 12 14 16 18 20
HIF3F-20PA-2.54DS (Box,Male,Right Angle)
10K/R1005
JTAG Figure 6 JTAG Connector CPU
BASE
Note. * This must be connected on ARM11 to use XRTCK,
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SMDK6410_USER’S MANUAL_REV 1.00
USB Two Dual USB ports A-type (CON2A & CON2B, HOST) and one USB OTG port mini AB-type (CON3) are supported by the SMDK6410. C_PWR_5V R66
R65 15K/R1005
33/R1005
XusbhDN XusbhDP R67
CON2A 1 2 3 4
R69
33/R1005
VBUS DD+ GND
USB(HOST) SOCKET
USB DUAL Port - A Ty pe (Host)
15K/R1005
CON3 C_PWR_5V R71 15K/R1005 USBH_DTP10 USBH_D+ TP11
R74 15K/R1005
CON2B 5 6 7 8
VBUS DD+ GND
1 2 3 4 5
XVBUS XotgDM XotgDP XotgID C16
USB(HOST) SOCKET
100nF
USB DUAL Port - A Ty pe (Host)
+ CT9
VBUS DD+ ID GND USB-MINIAB
10uF/6.3V/T2012
Figure 7 Dual USB ports & OTG port CPU
BASE
CPU
BASE
SPI Two IEEE-1394 connectors are used as SPI connecter.
CON8 [3] XspiCS0 [3] XspiMISO0/ADDR_CF0 [3] XspiMOSI0/ADDR_CF2 [3] XspiCLK0/ADDR_CF1
1 2 3 4
D1+ D1D2+ D2-
GND GND
5 6
IEEE1394/SD-54030
CON9 [3] XspiCS1 [3] XspiMISO1/mmcCMD2 [3] XspiMOSI1 [3] XspiCLK1/mmcCLK2
1 2 3 4
D1+ D1D2+ D2-
GND GND
5 6
IEEE1394/SD-54030
Figure 8 SPI Socket (IEEE1394 type)
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SMDK6410_USER’S MANUAL_REV 1.00
FPC cable for MIPI HSI FPC cable is used as a MIPI HIS connector
CON10 [4] Xhi_D1/rxWAKE/DATA_CF1 [4] Xhi_D3/rxDATA/DATA_CF3 [4] Xhi_D2/rxFLAG/DATA_CF2 [4] Xhi_D0/rxREADY /DATA_CF0
[16] [16] [16] [16]
Xhi_D1/DATA_CF1 Xhi_D3/DATA_CF3 Xhi_D2/DATA_CF2 Xhi_D0/DATA_CF0
RA6
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AXK7L16227G
Xhi_D5/txWAKE/DATA_CF5 [4] Xhi_D7/txDATA/DATA_CF7 [4] Xhi_D6/txFLAG/DATA_CF6 [4] Xhi_D4/txREADY /DATA_CF4 [4]
RA7
0
Xhi_D5/DATA_CF5 Xhi_D7/DATA_CF7 Xhi_D6/DATA_CF6 Xhi_D4/DATA_CF4
[16] [16] [16] [16]
MIPI Connector
Figure 9 FPC cable connector CPU
BASE
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SMDK6410_USER’S MANUAL_REV 1.00
SD host (Ver2.0) SD/MMC interface SD/MMC is provided by the 6410 and SD card sockets are supported in the SMDK6410. VDD_MMCD
B_MMC_DATA2 B_MMC_DATA3
4
B_MMC_CMD R153 NC/R1005
B_MMC_DATA0
26
B_MMC_DATA1
[3,6,16] XEINT12 [3,6,16] XEINT13
13 14 15 16 17 18 19 20 21 22 23 24 25
B_MMC_CLK
[3] XmmcCDN0/mmcCDN1
VDD_MMCD
5 6 7 8 9 10 11 12
R156
0/R1005
27
R157
NC/R1005
28
R158
NC/R1005
30
DAT2 DAT3 DAT4 NC CMD NC DAT5 NC VSS NC NC VDD NC NC CLK NC DAT6 NC VSS NC DAT7 NC DAT0 DAT1 SD_CD SD_WP
SD/HSMMC Socket (Taisol 156-1001000901))
P29/GND
3
NC NC
29
1 2 R147 R148 R149 R150 R151
SDDATA & CLK path must be same length and route
CON7
P30/GND
50K/R1005 50K/R1005 10K/R1005 50K/R1005 50K/R1005
Channel 0
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SMDK6410_USER’S MANUAL_REV 1.00
VDD_MMCD
[3] XmmcDATA1_2 [3] XmmcDATA1_3
4
[3] XmmcDATA1_4/mmcDATA2_0/ADDR_CF0 [3] XmmcCMD1/ADDR_CF1 [3] XmmcDATA1_5/mmcDATA2_1/ADDR_CF1 R152
VDD_MMCD
NC/R1005
[3] XmmcDATA1_6/mmcDATA2_2/ADDR_CF2
[3] XmmcDATA1_7/mmcDATA2_3 [3] XmmcDATA1_0/ADDR_CF2
26
[3] XmmcDATA1_1
27
[3] XmmcCDN0/mmcCDN1 [3,8,16] XPWM_ECLK
NC/R1005
13 14 15 16 17 18 19 20 21 22 23 24 25
[3] XmmcCLK1/ADDR_CF0
R155
5 6 7 8 9 10 11 12
SD0_nWP
28
30 P30/GND
3
NC NC DAT2 DAT3 DAT4 NC CMD NC DAT5 NC VSS NC NC VDD NC NC CLK NC DAT6 NC VSS NC DAT7 NC DAT0 DAT1 SD_CD SD_WP
SD/HSMMC Socket (Taisol 156-1001000901))
P29/GND
1 2
29
50K/R1005 50K/R1005 50K/R1005 10K/R1005 50K/R1005 50K/R1005 50K/R1005 50K/R1005 50K/R1005 50K/R1005 50K/R1005
CON6
R136 R137 R138 R139 R140 R141 R142 R143 R144 R145 R146
SDDATA & CLK path must be same length and route
Channel 1
Figure 10 SD card Socket CPU
BASE
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SMDK6410_USER’S MANUAL_REV 1.00
EXTERNAL ONE-NAND connector External connector is supported for connecting ONE_NAND external board VDD_SMEM
VDD_SMEM
CON12
CTB31
+
100K/R1005 R176 100K/R1005
R177
nCS_EXT_TWO nCS_EXT_ONE [2,11] Xm0WEn/nIOWR_CF [2] Xm0ADV RPn_EXT [2] Xm0SMCLK [2,10,11] Xm0DATA[15:0]
Xm0DATA0 Xm0DATA2 Xm0DATA4 Xm0DATA6 Xm0DATA8 Xm0DATA10 Xm0DATA12 Xm0DATA14
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
CB83
100nF 10uF/6.3V/T2012
INT_EXT_TWO RDY _EXT_TWO Xm0OEn/nIORD_CF [2,11,12] INT_EXT_ONE RDY _EXT_ONE
Xm0DATA1 Xm0DATA3 Xm0DATA5 Xm0DATA7
Xm0DATA[15:0] [2,10,11]
Xm0DATA9 Xm0DATA11 Xm0DATA13 Xm0DATA15
QSH-030-01-F-D-A
oneNAND Connector
Figure 11 External ONE-NAND B’d Connector CPU
BASE
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SMDK6410_USER’S MANUAL_REV 1.00
Camera Interface Connector SMDK6410 provides Camera Interface Connector. (VDDA 2.8V) VDD_CAM_EXT
(VDDIO 2.8V) VDD_CAM_EXT
R195
VDD_CAM_1.5V
CON13
0/R1005
1 3 5 7 9 11 13 15 17 19
[3,9,16] Xi2cSDA0 [3,9,16] Xi2cSCL0 B_CAMRST B_CAMPCLK B_CAMVSY NC
2 4 6 8 10 12 14 16 18 20
B_CAMDATA[7:0]
B_CAMCLK
B_CAMDATA7 B_CAMDATA6 B_CAMDATA5 B_CAMDATA4
B_CAMHREF B_CAMDATA3 B_CAMDATA2 B_CAMDATA1 B_CAMDATA0
AXK8L20125B_Header
CAM IF Figure 12 Camera Interface Connector CPU
BASE
CPU
BASE
ADC connector SMDK6410 provides ADC Interface Connector.
ADC
CON1 Xadc_AIN0 Xadc_AIN1 Xadc_AIN2 Xadc_AIN3
1 3 5 7 9
2 4 6 8 10
HDR10-2.54-MALE
Xadc_AIN4 Xadc_AIN5 Xadc_AIN6 Xadc_AIN7 R27 R28 R29 R30
0/R1005 0/R1005 0/R1005 0/R1005
Xadc_AIN4_Y M [16] Xadc_AIN5_Y P [16] Xadc_AIN6_XM [16] Xadc_AIN7_XP [16]
Figure 13 ADC Connector
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SMDK6410_USER’S MANUAL_REV 1.00
PMIC connector SMDK6410 provides 200-FBGA Connector for PMIC Module Board. PMIC_MIC1_N [16] PMIC_MIC1_P [16] PMIC_MIC2_N [16] PMIC_MIC2_P [16]
[16] WLED_OUT1 [16] WHITE_LED
VBAT
PVDD_RTC
TP15 TP14 TP16
TP17
TP28 TP27 TP19 TP21TP23 TP25 TP18 TP20 TP22TP24 TP26
1
VCHGR TP13
LED3
PMIC
E19 F19
PVDD_PLL PVDD_HI
F4 G4 E17 F17
PVCCAUX3 PVDD_UH_MMC PVCCAUX2 PVDD_EXT
H7 J7 E3 E4 H6 J6 H14 J14
PVCCM3BT TP38
PVDD_OTGI
F2 G2 G8 H13 J13
PVDD_SYS PVCCM2MTV
H18 J18 H3 J3
PVDD_LCD PVDD_SS
H15 J15 F3 G3
PVDD_OTG PVDD_ALIVE
H17 J17 H2 J2
PVDD_AUDIO TP44
J5 H4 H5
J16 J4 H16 G7 E18 C2 Reserved Reserved Reserved Reserved Reserved Reserved
C3 C4 C5 C6 ADC_IN4 ADC_IN5 ADC_IN6 ADC_IN7
F11 F12 E11 E12
G19 VVIB
TSI_XM TSI_XP TSI_YM TSI_YP
H8 J8 G14 G15 H19 J19 MIC1_N MIC1_P MIC2_N MIC2_P MIC_BIAS_INT MIC_BIAS_EXT
G16 G17 G18 WLED_BOOST WLED_OUT1 WLED_OUT2
G12 G13 D12 LED_DRV1 LED_DRV2 FLASH_EN
E9 E10 D9 D10 D2 VCHGR VCHGR VCHGR VCHGR TBAT
H12 J12 VRTC_VDDRTC VRTC_VDDRTC
BUCK2_VDDINT BUCK2_VDDINT
PCM_CLK PCM_FSY NC PCM_SDI PCM_SDO
BUCK3_VDDMEM0/VDDMEM1 BUCK3_VDDMEM0/VDDMEM1 BUCK3_VDDMEM0/VDDMEM1 BUCK3_VDDMEM0/VDDMEM1 BUCK3_VDDMEM0/VDDMEM1 BUCK3_VDDMEM0/VDDMEM1
I2C_SCL I2C_SDA
VLDO1_VCCAUX1 VLDO1_VCCAUX1
PWR_I2C_SCL PWR_I2C_SDA
VLDO2_VDDMPLL/VDDAPLL/VDDEPLL VLDO2_VDDMPLL/VDDAPLL/VDDEPLL
nVDD_FAULT nBATT_FAULT SY S_EN PWR_EN nPMIC_IRQ nSLEEP EXT_WAKEUP1 EXT_WAKEUP0 nONKEY nEXTON nRST_IN REM_IN nRST_OUT
VLDO3_VDDHI VLDO3_VDDHI VLDO4_VCCAUX3 VLDO4_VCCAUX3
CON5
VLDO5_VDDUH/VDDMMC VLDO5_VDDUH/VDDMMC VLDO6_VCCAUX2 VLDO6_VCCAUX2
SEAM-20-02.0-SM-10-2-A
VLDO7_VDDEXT VLDO7_VDDEXT VLDO8_VCCM3BT VLDO8_VCCM3BT LDO8_EN(Reserv ed) VLDO9_VDDOTGI VLDO9_VDDOTGI VLDO10_VDDSY S VLDO10_VDDSY S
VMID AUD_AMP_EN AUDIO_LINEOUT STEREO_CH2 STEREO_CH1 BEAR_SPK_N BEAR_SPK_P MONO_SPK_N MONO_SPK_P AUD_AUX3_IN AUD_AUX2_IN AUD_AUX1_IN
E2
R97
0/R1005
D18 D16 D17 F8 E8
R98 R99 R100 R101 R102
0/R1005 0/R1005 0/R1005 0/R1005 0/R1005
C10 C9 C8 C7
R103 R104 R105 R106
0/R1005 0/R1005 0/R1005 0/R1005
B8 B9 D11 C11 B15 B13 B12 B11 B10 B5 B4 B3 B2 D19 D7 D6 D5 C17 D8 C19 C18 C16 C15 C14 C13 C12 B19 B18 B17
XPCM_EXTCLK1/I2S_CDCLK1/AC97_RSTn0 [3,16] XPCM_EXTCLK0/I2S_CDCLK0/AC97_RSTn0/ADDR_CF1 [3,16] XPCM_DCLK0/I2S_CLK0/AC97_BITCLK0/ADDR_CF0 [3,16] XPCM_FSY NC0/I2S_LRCLK0/AC97_SY NC0/ADDR_CF2 [3,16] XPCM_SIN0/I2S_DI0/AC97_SDI0 [3,16] XPCM_SOUT0/I2S_DO0/AC97_SDO0 [3,16] XPCM_DCLK1/I2S_CLK1/AC97_BITCLK0 [3,16] XPCM_FSY NC1/I2S_LRCLK1/AC97_SY NC0 [3,16] XPCM_SIN1/I2S_DI1/AC97_SDI0 [3,16] XPCM_SOUT1/I2S_DO1/AC97_SDO0 [3,16] Xi2cSCL0 [3,15,16] Xi2cSDA0 [3,15,16] TP29 TP30 TP31 XnBATF [2,3] TP32 XPWRRGTON [3,7] PMIC_XEINT12_IRQn [3] TP33 TP34 TP35 PMIC_ONKEY n [2] TP36 nRESET [2] PMIC_REM_IN [16] PMIC_nRST_OUT [2] PMIC_STEREO_VMID [16] TP37 PMIC_MODEM_MIC_P [16] PMIC_STEREO_CH2 [16] PMIC_STEREO_CH1 [16] PMIC_BEAR_SPK_N [16] PMIC_BEAR_SPK_P [16] PMIC_MONO_SPK_N [16] PMIC_MONO_SPK_P [16] TP39 PMIC_MODEM_SPK_N [16] PMIC_MODEM_SPK_P [16]
VLDO11_VCCM2MTV VLDO11_VCCM2MTV VLDO12_VDDLCD VLDO12_VDDLCD
Reserv ed Reserv ed Reserv ed Reserv ed Reserv ed Reserv ed Reserv ed Reserv ed Reserv ed
VLDO13_VDDGPS/VCCM1GPS VLDO13_VDDGPS/VCCM1GPS VLDO14_VDDOTG VLDO14_VDDOTG VLDO15_VDDALIVE VLDO15_VDDALIVE VLDO_AUDIO_VDDPCM/VDDADC/VDDDAC VLDO_ADC(Reserv ed) VBUS_XVBUS
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
PVCCAUX1
E5 E6 E7 F5 F6 F7
MCLK I2S_CDCLK I2S_BITCLK I2S_SY NC I2S_DATAOUT I2S_DATAIN
GND GND GND GND
B16 B14 B7 B6 D4 D3 D15 D14 D13
TP40 TP41 TP42 TP43
J20 J1 H20 H1
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 E1 E16 E20 F1 F9 F10 F16 F20 B1 B20
PVDD_MEM
[3,7] XVBUS
LED_PC G5 G6
BUCK1_VDDARM BUCK1_VDDARM BUCK1_VDDARM BUCK1_VDDARM BUCK1_VDDARM BUCK1_VDDARM
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
PVDD_INT
E13 E14 E15 F13 F14 F15
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 C1 C20 D1 D20 G1 G20
PVDD_ARM
H9 H10 H11 J9 J10 J11 G9 G10 G11
R96 1K/R1005
VBAT_IN VBAT_IN VBAT_IN VBAT_IN VBAT_IN VBAT_IN VBAT_IN VBAT_IN VBAT_IN
F18
2
LED-Red (SMD 3216)
Figure 14 PMIC Connector CPU
BASE
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SMDK6410_USER’S MANUAL_REV 1.00
BASE BOARD COMPOSITE & S-VIDEO Connector SMDK6410 provides COMPOSITE & S-VIDEO output connector
JACK9 R387 0/R1608
R389
1
VIDEO
GND
2
COMPOSITE RCA
0/R1608
JACK10
3 Y 4 C
2 Yn
Cn 1
CONN_SVIDEO_12P (MD-40S)
Figure 15 Composite & S-VIDEO Connector CPU
BASE
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SMDK6410_USER’S MANUAL_REV 1.00
LINE IN, MIC IN & SPEAKER OUT connector SMDK6410 provides LINE IN, MIC IN and SPEAKER OUT as an audio connector. AVDD_ext
CTB20 10uF,6.3V/T2012 AVDD_ext
+
0 : NC ON 1 : NO ON
R78
Line In
CB21
GND
9
COM2
2
Line In Right 5
IN1
1
7
IN2
R81
LineIn_nWM8753/WM9713 [4] CTB26 10uF,6.3V/T2012 AVDD_ext
100nF/C1608
Headphone/Front LR
NO2
NO2
IN1
GND
IN2
3
9
2 1
5 7
PJ-327-2
MAX4764ETB
CTB27 10uF,6.3V/T2012
AVDD_ext
1
VCC COM1 COM2 IN1 IN2
3
3
9
2
5 7
CB24
Center/Sub
100nF/C1608
U9
1
PJ-327-2
[7] WM8580_OUT_Center
Rear LR
MAX4764ETB [4] Speaker_nWM8753/WM9713 L
[7] WM8580_OUT_RR
2
10
NC2 NO1 NO2 GND
JACK4 VCC COM1 COM2 IN1 IN2
1 3
3
9
2
5 7
1
PJ-327-2
MAX4764ETB Speaker_nWM8753/WM9713 [4]
Gnd
1
[2] PMIC_STEREO_CH2
2
6
3
R
[7] WM8580_OUT_RL
[2] PMIC_STEREO_CH1
8
NC1
Gnd
JACK5
[7] WM8580_OUT_Sub
4
R
GND
COM2
NO1
3
L
6
NO1
COM1
+
10
6
JACK3
Gnd
[6] WM9713_OUT_R
2
NC2
C3
R
[6] WM9713_OUT_L
8
NC1
10
L
[7] WM8753_OUT_FR
4
1.5K/R1608
NC2
1
Mic_nWM8753/WM9713 [4]
U8 [7] WM8753_OUT_FL
+ CTB25
2
220pF/C1608 10uF,6.3V/T2012
+ CB23
8 [2,6] PMIC_MIC1_N [2,6] WM9713_MIC
JACK2 VCC
NC1
Gnd
PJ-327-2
Mic In 100nF/C1608
U7 4
[7] WM8580_MIC
R80 1.5K/R1608
MAX4764ETB
CB22
CTB22 47uF,6.3V/T3528
R
6
NO2
+
3
L
10
COM1
Line In Left
Gnd
[6] WM9713_LINE_R
NO1
3
6.8K/R1608
AVDD_ext
R
2
[6] WM9713_LINE_L
NC2
R79
JACK1 1
VCC
L
8
[7] WM8580_LINEIN_R
NC1
+
U6 4
[7] WM8580_LINEIN_L
AVDD_ext CTB21 10uF,6.3V/T2012
100/R1608
100nF/C1608
PJ-327-2
Figure 16 Audio Line In, Mic In & Speaker Out Connector CPU
BASE
36
SMDK6410_USER’S MANUAL_REV 1.00
ETHERNET connector SMDK6410 provides Ethernet 10Mbps (CON6) and 100Mbps (JACK8) connector. R235
8 ohm, 1%/R1608
C39 580pF/C1608
CON6
9 10
Shield Shield
CT_T2 TDCT_T1 TD+ RD+ CT_R1 RDCT_R2
R239
1 2 3 4 5 6 7 8
8 ohm, 1%/R1608
R240 100 ohm,1%/R1608
Single_Ports_Combo (XFMRS / XF10B11A-COMBO1-4S)
C42 C40
C43
C41
100nF/C1608
0.1uF 2KV(NC) 0.1uF 2KV (NC) NC (100nF)/C1608
49.9 ohm/R1608
49.9 ohm/R1608
49.9 ohm/R1608
49.9 ohm/R1608
R260
R261
R262
R263
JACK8
R268 49.9 ohm/R1608 R273 0/R1608
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9 RJHS-5380
R269 49.9 ohm/R1608
C49 NC (1000pF,2KV)
Figure 17 Ethernet Socket CPU
BASE
37
SMDK6410_USER’S MANUAL_REV 1.00
UART interface The S3C6410 UART unit provides three independent asynchronous serial I/O (SIO) ports including IrDA. In SMDK6410 board, COM1 port is only used for UART0. No jumper setting is required. You can change UART by setting related jumpers.
COM2 port UART1/2/3 JACK7
COM1 port UART0 Only JACK6 nDTR0 TXD0 nCTS0 RXD0 nRTS0 nDSR0
1 6 2 7 3 8 4 9 5
1 6 2 7 3 8 4 9 5
TXD1/2/3 nCTS1 RXD1/2/3 nRTS1
BOXCONN_DB9
BOXCONN_DB9
Figure 18 UART Sockets CPU
BASE
CPU
BASE
xD Picture Card Connector SMDK6410 provides xD Picture Card Connector.
XD PICTURE CARD VDD3.3V
[2,8,10..12] B_DATA[15:0]
R23 4.7K/R1608 B_DATA7 B_DATA6 B_DATA5 B_DATA4 B_DATA3 B_DATA2 B_DATA1 B_DATA0
[2] B_FWEn [2] B_ALE [2] B_CLE nCS_XD [2] B_FREn [2] B_RnB
CON1 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 19
VCC D7 D6 D5 D4 D3 D2 D1 D0 GND WP WE ALE CLE CE RE R/B GND GND
xD_CARD Socket
Figure 19 xD Picture Card Socket
38
SMDK6410_USER’S MANUAL_REV 1.00
CF Card Slot SMDK6410 provides CF/ATA Card Slot Connector. TP29 TP28 TP31 TP27 TP30 VDD_CF
CB42
CB43
VDD_CF
CTB41
+
R150
10uF,6.3V/T2012 100nF/C1608
[2,10,13] Xhi_A3/KP_COL3/Xm0INTata [2] B_INTata VDD_CF [2] B_INPACKata [2,10,13,14] Xhi_A5/KP_COL5/Xm0INPACKata [2,10,13,14] Xhi_A6/KP_COL6/Xm0REGata [2] B_REGata VDD_CF
10K/R1608
CON4
100nF/C1608
R151 R152
NC/R1608 0/R1608
R154 R155 R156 R157 R159 R160
10K/R1608 10K/R1608 0/R1608 NC/R1608 NC/R1608 0/R1608
7 32 34 35 42 1 37 38 39 40 41 24 43 44 45 46 9 13 33 36 26 25 8 10 11
CE_CF0 CE_CF1 nIORD_CF nIOWR_CF IORDY_CF
R158 10K/R1608
R161 R162
10K/R1608 10K/R1608
[2] B_OEata
[2] B_WEata CD1_CF CD2_CF [2,3,10..12] B_ADDR[19:0]
[2] B_RESET [2,10,13] Xhi_A4/KP_COL4/Xm0RSTata
B_ADDR10 B_ADDR9 B_ADDR8 R164 R165
0/R1608 NC/R1608
D0 nCE1 D1 nCE2 D2 nIORD D3 nIOWR D4 nWAIT D5 GND1 D6 IREQ D7 VCC2 D8 nCSEL D9 nVS2/OPEN D10 RESET D11 WP D12 nINPACK D13 nREG D14 nSPKR D15 nSTSCHG GND2 nOE A7 VCC1 A6 nVS1/GND A5 nWE A4 CD1 A3 CD2 A2 A10 A1 A9 A0 A8
P_DATA[15:0] 21 22 23 2 3 4 5 6 47 48 49 27 28 29 30 31 50 12 14 15 16 17 18 19 20
P_DATA0 P_DATA1 P_DATA2 P_DATA3 P_DATA4 P_DATA5 P_DATA6 P_DATA7 P_DATA8 P_DATA9 P_DATA10 P_DATA11 P_DATA12 P_DATA13 P_DATA14 P_DATA15 B_ADDR7 B_ADDR6 B_ADDR5 B_ADDR4 B_ADDR3
B_ADDR[19:0] [2,3,10..12]
P_ADDR[2:0] P_ADDR2 P_ADDR1 P_ADDR0
CompactFlash (55358-5021)
Figure 20 CF/ATA Interface Connector CPU
BASE
CPU
BASE
PWM connector SMDK6410 provides PWM out0&1.
J1 [2,16] PWM_TOUT1 [2,16] PWM_TOUT0 [2,16] XPWM_ECLK
1 2 3 4 A2-4PA-2.54DSA (HDR4-2.54-MALE)
Figure 21 PWM out pins
39
SMDK6410_USER’S MANUAL_REV 1.00
EXTERNAL CONNECTOR INTERFACE ROM BUS Interface
VDD_EXHI
CTB44
+
R216 10K/R1608
CB52 100nF/C1608
10uF,6.3V/T2012
[3] nCS_EXT [2,3,8,11,12] B_WEn/nIOWR_CF [2,3,8,11,12] B_ADDR[19:0]
R215
RP4
10K/R1608
B_ADDR0 B_ADDR2 B_ADDR4 B_ADDR6 B_ADDR8 B_ADDR10 B_ADDR12 B_ADDR14 B_ADDR16 B_ADDR18
[2,3,8,11,12] B_DATA[15:0]
VDD_EXHI
B_DATA0 B_DATA2 B_DATA4 B_DATA6 B_DATA8 B_DATA10 B_DATA12 B_DATA14
TP42 [2,13,15,16] XEINT4/KP_ROW4 [2,13,15] XEINT3/KP_ROW3 [2,3,11] B_nBE1 [2,3] B_nBE0 [2,8,9] XuTXD_2/ExdACK/IrTXD/ADDR_CF1 [2,5,9] XuTXD_3/ExdACK/IrTXD/Xi2cSDA1
RP5
0/R1608
0/R1608
R217 10K/R1608
JF1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
B_ADDR1 B_ADDR3 B_ADDR5 B_ADDR7
B_OEn/nIORD_CF [2,3,8,11,12] B_ADDR[19:0] [2,3,8,11,12]
B_ADDR9 B_ADDR11 B_ADDR13 B_ADDR15 B_ADDR17 B_ADDR19
B_DATA1 B_DATA3 B_DATA5 B_DATA7
B_DATA[15:0] [2,3,8,11,12]
B_DATA9 B_DATA11 B_DATA13 B_DATA15
Modem_nReset [2] XnRSTOUT [2,11..16] B_WAITn/IORDY [2,8,11] R229 0/R1608 XuRXD_0 [2,9,14] R230 0/R1608 XuTXD_0 [2,9,14] XuRXD_2/ExdREQ/IrRXD/ADDR_CF0 [2,8,9] XuRXD_3/ExdREQ/IrRXD/ADDR_CF2/Xi2cSCL1 [2,5,8,9]
QTE-040-01-L-D-EM2
ROM Bus Figure 22 External ROM Bus Connector
40
SMDK6410_USER’S MANUAL_REV 1.00
# of pin
Descriptions
# of pin
Descriptions
# of pin
Descriptions
# of pin
Descriptions
1
VDD_3.3V
21
B_ADDR10
41
B_DATA0
61
-
2
VDD_3.3V
22
B_ADDR11
42
B_DATA1
62
-
3
nCS_EXT
23
B_ADDR12
43
B_DATA2
63
-
4
-
24
B_ADDR13
44
B_DATA3
64
-
5
B_WEn/nIOW R_CF
25
B_ADDR14
45
B_DATA4
65
-
6
B_OEn/IORD _CF
26
B_ADDR15
46
B_DATA5
66
Modem_nRes et
7
-
27
GND
47
B_DATA6
67
XEINT4
8
GND
28
GND
48
B_DATA7
68
XnRSTOUT
9
B_ADDR0
29
B_ADDR16
49
GND
69
XEINT3
10
B_ADDR 1
30
B_ADDR17
50
GND
70
XrWAITn
11
B_ADDR 2
31
B_ADDR18
51
B_DATA8
71
B_nBE1
12
B_ADDR 3
32
B_ADDR19
52
B_DATA9
72
XuRXD_0
13
B_ADDR 4
33
-
53
B_DATA10
73
B_nBE0
14
B_ADDR 5
34
-
54
B_DATA11
74
XuTXD_0
15
B_ADDR 6
35
-
55
B_DATA12
75
XuTXD_2
16
B_ADDR 7
36
-
56
B_DATA13
76
XuRXD_2
17
GND
37
-
57
B_DATA14
77
XuTXD_3
18
GND
38
-
58
B_DATA15
78
XuRXD_3
19
B_ADDR 8
39
-
59
-
79
GND
20
B_ADDR 9
40
GND
60
-
80
GND CPU
BASE
41
SMDK6410_USER’S MANUAL_REV 1.00
HOST/MODEM INTERFACE [2,8] XhiCSn/CE_CF0
0/R1608
10K/R1608
10K/R1608 10K/R1608 R223 R224
0/R1608 RP6
VDD_EXHI
RP7
10K/R1608 R221
CB53
CTB45
10K/R1608 10K/R1608 10K/R1608
+
R218 R219 R220
A2-3PA-2.54DSA [2,8] XhiCSnmain/CE_CF1
VDD_EXHI
100nF/C1608
R222
1 2 3
J3
JF2 10uF,6.3V/T2012 [2,8] XhiWEn/CF_IOWR
R226
[2,8,13] Xhi_A1/ADDR_CF1/KP_COL1 [2,8,13] Xhi_A3/KP_COL3/Xm0INTata [2,8,13,14] Xhi_A5/KP_COL5/Xm0INPACKata [2,8,13,14] Xhi_A7/KP_COL7/Xm0CData [2,8,14] Xhi_A9/CE_CF1 [2,8,15] Xhi_A11/IOWR_CF
R228 NC/R1608
[2,8] Xhi_D0/DATA_CF0 [2,8] Xhi_D2/DATA_CF2 [2,8] Xhi_D4/DATA_CF4 [2,8,14] Xhi_D6/DATA_CF6 [2,8,13] Xhi_D8/DATA_CF8/KP_ROW0 [2,8,13] Xhi_D10/DATA_CF10/KP_ROW2 [2,8,13] Xhi_D12/DATA_CF12/KP_ROW4 [2,8,13] Xhi_D14/DATA_CF14/KP_ROW6 [2] Xhi_D16/DATA_CF8
[2,16] XhiINTR [2] AP_nReset [2,13,16] XEINT5/KP_ROW5 [2,8,9] XuTXD_2/ExdACK/IrTXD/ADDR_CF1 [2,5,9] XuTXD_3/ExdACK/IrTXD/Xi2cSDA1
R231 NC/R1608
0/R1608
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
R225
R227 100K/R1608
0/R1608
XhiCSn_sub/CF_IORD [2,8,15] XhiOEn/CF_IORDY [2,8,15]
Xhi_A0/ADDR_CF0/KP_COL0 Xhi_A2/ADDR_CF2/KP_COL2 Xhi_A4/KP_COL4/Xm0RSTata Xhi_A6/KP_COL6/Xm0REGata
[2,8,13] [2,8,13] [2,8,13] [2,8,13,14]
Xhi_A8/CE_CF0 [2,8] Xhi_A10/IORD_CF [2,8,15] Xhi_A12/IORDY _CF [2,8]
TP39 TP40 TP41 Xhi_D1/DATA_CF1 Xhi_D3/DATA_CF3 Xhi_D5/DATA_CF5 Xhi_D7/DATA_CF7
[2,8] [2,8,14] [2,8,14] [2,8,14]
Xhi_D9/DATA_CF9/KP_ROW1 [2,8,13] Xhi_D11/DATA_CF11/KP_ROW3 [2,8,13] Xhi_D13/DATA_CF13/KP_ROW5 [2,8,13] Xhi_D15/DATA_CF15/KP_ROW7 [2,8,13] Xhi_D17/DATA_CF9 [2] XEINT8/ADDR_CF0 [2,8,14]
XuRXD_2/ExdREQ/IrRXD/ADDR_CF0 [2,8,9] XuRXD_3/ExdREQ/IrRXD/ADDR_CF2/Xi2cSCL1 [2,5,8,9] R232 NC/R1608
QSE-040-01-L-D-EM2
Host/MODEM I/F
Figure 23 Host/Modem Interface Connector
42
SMDK6410_USER’S MANUAL_REV 1.00
# of pin
Descriptions
# of pin
Descriptions
# of pin
Descriptions
# of pin
Descriptions
1
VDD_3.3V
21
Xhi_A9
41
Xhi_D0
61
-
2
VDD_3.3V
22
Xhi_A10
42
Xhi_D1
62
-
3
XhiCSn
23
Xhi_A11
43
Xhi_D2
63
-
4
XhiCsn_sub
24
Xhi_A12
44
Xhi_D3
64
-
5
XhiWEn
25
-
45
Xhi_D4
65
-
6
XhiOEn
26
-
46
Xhi_D5
66
XEINT8
7
XhiCSnmain
27
GND
47
Xhi_D6
67
XhiINTR
8
GND
28
GND
48
Xhi_D7
68
-
9
-
29
-
49
GND
69
AP_nReset
10
Xhi_A0
30
-
50
GND
70
-
11
Xhi_A1
31
-
51
Xhi_D8
71
-
12
Xhi_A2
32
-
52
Xhi_D9
72
-
13
Xhi_A3
33
-
53
Xhi_D10
73
-
14
Xhi_A4
34
-
54
Xhi_D11
74
-
15
Xhi_A5
35
-
55
Xhi_D12
75
XuTXD_2
16
Xhi_A6
36
-
56
Xhi_D13
76
XuRXD_2
17
GND
37
-
57
Xhi_D14
77
XuTXD_3
18
GND
38
-
58
Xhi_D15
78
XuRXD_3
19
Xhi_A7
39
GND
59
Xhi_D16
79
GND
20
Xhi_A20
40
GND
60
Xhi_D17
80
GND CPU
BASE
43
SMDK6410_USER’S MANUAL_REV 1.00
EXTERNAL KEYPAD CONNECTOR VDD3.3V CTB52
CB69
+
VDD3.3V
100nF/C1608 10uF,6.3V/T2012
CON8 kp_ROW0 kp_ROW1 kp_ROW2 kp_ROW3 kp_ROW4 kp_ROW5 kp_ROW6 kp_ROW7
1 3 5 7 9 11 13 15 17 19 21 23
2 4 6 8 10 12 14 16 18 20 22 24
kp_COL0 kp_COL1 kp_COL2 kp_COL3 kp_COL4 kp_COL5 kp_COL6 kp_COL7
HIF3H-24DA-2.54DS (Female,Right Angle)
Figure 24 External Keypad Connector
# of pin
Descriptions
# of pin
Descriptions
1
VDD_3.3V
13
Kp_ROW4
2
VDD_3.3V
14
Kp_COL4
3
VDD_3.3V
15
Kp_ROW5
4
VDD_3.3V
16
Kp_COL5
5
Kp_ROW0
17
Kp_ROW6
6
Kp_COL0
18
Kp_COL6
7
Kp_ROW1
19
Kp_ROW7
8
Kp_COL1
20
Kp_COL7
9
Kp_ROW2
21
GND
10
Kp_COL2
22
GND
11
Kp_ROW3
23
GND
12
Kp_COL3
24
GND CPU
BASE
44
SMDK6410_USER’S MANUAL_REV 1.00
VDD3.3V
CON7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
kp_COL0 kp_COL1 kp_COL2 kp_COL3 kp_COL4 kp_ROW0 kp_ROW1 kp_ROW2 kp_ROW3 kp_ROW4 TP46 [2,10..12,14..16] XnRSTOUT TP47 kp_ROW5 kp_ROW6 kp_ROW7 kp_COL5 kp_COL6 kp_COL7
TP48
GF056-30S-LSS-P2000
Figure 25 External Qwerty Keypad Connector
# of pin
Descriptions
# of pin
Descriptions
1
VDD_3.3V
16
TP47
2
VDD_3.3V
17
GND
3
GND
18
Kp_ROW5
4
Kp_COL0
19
Kp_ROW6
5
Kp_COL1
20
Kp_ROW7
6
Kp_COL2
21
Kp_COL5
7
Kp_COL3
22
Kp_COL6
8
Kp_COL4
23
Kp_COL7
9
Kp_ROW0
24
VDD_3.3V
10
Kp_ROW1
25
VDD_3.3V
11
Kp_ROW2
26
GND
12
Kp_ROW3
27
VDD_3.3V
13
Kp_ROW4
28
GND
14
TP46
29
GND
15
XnRSTOUT
30
GND
45
SMDK6410_USER’S MANUAL_REV 1.00
MODULE1 INTERFACE CONNECTOR (FOR GPS DAUGHTER BOARD) VDD3.3V
PVDD_SS
CB71
CTB54
+ 10uF,6.3V/T2012
100nF/C1608
[2,8..10] XuTXD_2/ExdACK/IrTXD/ADDR_CF1 [2,8..10] XuRXD_2/ExdREQ/IrRXD/ADDR_CF0 [2,9,10] XuTXD_0 [2,9,10] XuRXD_0 [2,9] XuRTSn_0/ADDR_CF1 [2,9] XuCTSn_0/ADDR_CF0 [2,8,10] XEINT8/ADDR_CF0 [2,17] XEINT9/ADDR_CF1 [2,11,12,17] XEINT10/ADDR_CF2 [2,16,17] XEINT15
R458 R459
0/R1608 0/R1608
R307 R308 R309 R310
NC/R1608 NC/R1608 0/R1608 0/R1608
R311 R312 R313 R315
0/R1608 0/R1608 0/R1608 0/R1608
TP50 TP51
TP54 MODEM_WAKEUP MODEM_RI MODEM_PWR_ON MODEM_RST
TP56 TP58 TP59 TP60 TP61 [2,10..13,15,16] XnRSTOUT
TP62
R305
R304 0/R1608 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
CB70
M1
+ 10uF,6.3V/T2012
0/R1608 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
CTB53
100nF/C1608 PVCCAUX1
TP49 R306
0/R1608 MODEM_RTC_PWR(2.8V) CTB55 CB72
TP52 TP53
+ 10uF,6.3V/T2012
100nF/C1608
TP55
R314
0/R1608
XEINT13 [2,16,17]
TP57 R316 R317 R318 R319
0/R1608 0/R1608 0/R1608 0/R1608
B_SPI0_CLK/ADDR_CF1 [2,16] B_SPI0_MOSI/ADDR_CF2 [2,3,15,16] B_SPI0_MISO/ADDR_CF0 [2,15,16] B_SPI0_CSn [2,16]
B_PWR_5V
CB73
+ CTB56 10uF,16V/T3216
QSH-030-01-F-D-A
100nF/C1608
GPS (UART0, SPI0) MODULE 1 Figure 26 Module1 Connector
46
SMDK6410_USER’S MANUAL_REV 1.00
# of pin
Descriptions
# of pin
Descriptions
# of pin
Descriptions
1
PVDD_SS
21
XuCTSn_0/ADDR_CF0
41
TP
2
VDD3.3V
22
-
42
B_SPI0_CLK/ADDR_CF1
3
PVDD_SS
23
TP
43
TP
4
VDD3.3V
24
TP
44
B_SPI0_MOSI/ADDR_CF2
5
-
25
GND
45
-
6
TP
26
-
46
B_SPI0_MISO/ADDR_CF0
7
-
27
XEINT8/ADDR_CF0
47
TP
8
PVCCAUX1
28
GND
48
B_SPI0_CSn
9
TP
29
XEINT9/ADDR_CF1
49
GND
10
GND
30
-
50
B_PWR_5V
11
TP
31
XEINT10/ADDR_CF2
51
-
12
-
32
XEINT13
52
B_PWR_5V
13
-
33
XEINT15
53
XnRSTOUT
14
TP
34
-
54
B_PWR_5V
15
XuTXD_0
35
-
55
TP
16
TP
36
-
56
B_PWR_5V
17
XuRXD_0
37
TP
57
-
18
-
38
TP
58
B_PWR_5V
19
XuRTSn_0/ADDR_CF 1
39
TP
59
GND
20
-
40
GND
60
GND CPU
BASE
47
SMDK6410_USER’S MANUAL_REV 1.00
MODULE2 INTERFACE CONNECTOR (FOR MOBILE TV, HD RADIO DAUGHTER BOARD) VDD3.3V
PVCCM2MTV
CB74
CTB57
+ 10uF,6.3V/T2012
100nF/C1608
TP65 [4] M2_Port0_I2SCDCLK/AC_RSTn [4] M2_Port0_I2SLRCLK/AC_SY NC [4] M2_Port0_I2SSCLK/AC_BITCLK [4] M2_Port0_I2SSDI/AC_SDI [4] M2_Port0_I2SDO/AC97_SDO [2,8,10,13] Xhi_A5/KP_COL5/Xm0INPACKata [2,8,10,13] Xhi_A6/KP_COL6/Xm0REGata [2,8,10,13] Xhi_A7/KP_COL7/Xm0CData [2,8,10] Xhi_D3/DATA_CF3 [2,8,10] Xhi_A9/CE_CF1 [2,8,10] Xhi_D5/DATA_CF5 [2,8,10] Xhi_D6/DATA_CF6 [2,8,10] Xhi_D7/DATA_CF7 [2,10..13,15,16] XnRSTOUT TP74 TP75
R324 R325 R326 R327 R328
0/R1608 0/R1608 0/R1608 0/R1608 0/R1608
R329 R330 R331 R332
0/R1608 0/R1608 0/R1608 NC/R1608
R333 R334 R335 R336
0/R1608 NC/R1608 NC/R1608 NC/R1608
R338
R321
R320
0/R1608
M2
0/R1608 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
0/R1608 2 4 6 8 10 12 R322 14 R323 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 R337 50 52 54 56 58 60
CB75
CTB58
+ 10uF,6.3V/T2012
100nF/C1608
0/R1608 0/R1608
TP63 TP64 Xi2cSCL0 [2,5,7,15] Xi2cSDA0 [2,5,7,15] TP66 TP67 TP68 TP69 TP70 TP71 TP72 TP73
0/R1608
B_SPI1_CLK/MMC2_CLK/i2sV40_DO1 [2,7,15] B_SPI1_MOSI [2,15] B_SPI1_MISO/MMC2_CMD/i2sV40_DO0 [2,7,15] B_SPI1_CSn/i2sV40_DO2 [2,7,15]
B_PWR_5V
CB76
+ CTB59 10uF,16V/T3216
QSH-030-01-F-D-A
100nF/C1608
Mobile TV (SPI1, IIC) HD Radio (SPI1, IIS for Module 4) MODULE 2 Figure 27 Module2 Connector
48
SMDK6410_USER’S MANUAL_REV 1.00
# of pin
Descriptions
# of pin
Descriptions
# of pin
Descriptions
1
PVCCM2MTV
21
M2_Port0_I2SLRCLK/A C_SYNC
41
Xhi_A9/CE_CF1
2
VDD3.3V
22
TP
42
B_SPI1_CLK/MMC2_CLK/i 2sV40_DO1
3
PVCCM2MTV
23
M2_Port0_I2SSCLK/AC _BITCLK
43
Xhi_D5/DATA_CF5
4
VDD3.3V
24
TP
44
B_SPI1_MOSI
5
GND
25
M2_Port0_I2SSDI/AC_S DI
45
Xhi_D6/DATA_CF6
6
-
26
TP
46
B_SPI1_MISO/MMC2_CM D/i2sV40_DO0
7
-
27
M2_Port0_I2SDO/AC97 _SDO
47
Xhi_D7/DATA_CF7
8
TP
28
-
48
B_SPI1_CSn/i2sV40_DO2
9
-
29
GND
49
-
10
TP
30
-
50
B_PWR_5V
11
-
31
Xhi_A5/KP_COL5/Xm0I NPACKata
51
-
12
Xi2cSCL0
32
TP
52
B_PWR_5V
13
-
33
Xhi_A6/KP_COL6/Xm0 REGata
53
XnRSTOUT
14
Xi2cSDA0
34
TP
54
B_PWR_5V
15
-
35
Xhi_A7/KP_COL7/Xm0 CData
55
TP
16
GND
36
TP
56
B_PWR_5V
17
TP
37
Xhi_D3/DATA_CF3
57
TP
18
-
38
TP
58
B_PWR_5V
19
M2_Port0_I2SCDCLK /AC_RSTn
39
GND
59
GND
20
TP
40
GND
60
GND CPU
BASE
49
SMDK6410_USER’S MANUAL_REV 1.00
MODULE3 INTERFACE CONNECTOR (FOR BLUETOOTH DAUGHTER BOARD) PVCCM3BT
CB77
VDD3.3V
CTB60
10uF,6.3V/T2012 100nF/C1608 BT_PCM_SDO BT_PCM_FSYNC
[4] M3_Port1_PCM_SOUT [4] M3_Port1_FSY NC [2,9] XuCTSn_1/ADDR_CF0 [2,9] XuRTSn_1/ADDR_CF1
[2,8,10] Xhi_A11/IOWR_CF [2,8,10] Xhi_A10/IORD_CF [2,13] XEINT2/KP_ROW2 [2,7,14] B_SPI1_CLK/MMC2_CLK/i2sV40_DO1 [2,14] B_SPI1_MOSI [2,7,14] B_SPI1_MISO/MMC2_CMD/i2sV40_DO0 [2,9] XuTXD_1 [2,9] XuRXD_1 [2,8,10] XhiOEn/CF_IORDY
[2,10..14,16] XnRSTOUT
R342 R343
0/R1608 0/R1608
R344 R345 R346 R347 R348 R349 R350 R351 R353
0/R1608 0/R1608 0/R1608 0/R1608 0/R1608 0/R1608 0/R1608 0/R1608 0/R1608
TP77
R340
R339
+
NCD_SD0 WP_SD0 SD_PWR_EN
0/R1608
CB78
CTB61
+
M3
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
0/R1608 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
10uF,6.3V/T2012 100nF/C1608 BT_PCM_SDI BT_PCM_CLK R341 0/R1608
R352
M3_Port1_PCM_SIN [4] M3_Port1_PCM_DCLK [4] M3_Port1_PCM_EXTCLK [4] TP76
0/R1608
XhiCSn_sub/CF_IORD [2,8,10]
B_PWR_5V
CB79
+ CTB62 10uF,16V/T3216
100nF/C1608
QSH-030-01-F-D-A
BT (UART1, PCM for PMIC Audio Codec) MODULE 3 Figure 28 Module3 Connector
50
SMDK6410_USER’S MANUAL_REV 1.00
# of pin
Descriptions
# of pin
Descriptions
# of pin
Descriptions
1
PVCCM3BT
21
-
41
XuTXD_1
2
VDD3.3V
22
-
42
-
3
PVCCM3BT
23
-
43
XuRXD_1
4
VDD3.3V
24
-
44
XhiCSn_sub/CF_IORD
5
M3_Port1_PCM_SOUT
25
-
45
XhiOEn/CF_IORDY
6
M3_Port1_PCM_SIN
26
-
46
-
7
M3_Port1_FSYNC
27
-
47
GND
8
M3_Port1_PCM_DCLK
28
-
48
GND
9
GND
29
Xhi_A11/IOWR_CF
49
GND
10
M3_Port1_PCM_EXTC LK
30
-
50
B_PWR_5V
11
-
31
Xhi_A10/IORD_CF
51
-
12
TP
32
-
52
B_PWR_5V
13
XuCTSn_1/ADDR_CF0
33
XEINT2/KP_ROW2
53
XnRSTOUT
14
GND
34
GND
54
B_PWR_5V
15
XuRTSn_1/ADDR_CF1
35
B_SPI1_CLK/MMC2_CLK /i2sV40_DO1
55
TP
16
-
36
-
56
B_PWR_5V
17
-
37
B_SPI1_MOSI
57
-
18
-
38
-
58
B_PWR_5V
19
-
39
B_SPI1_MISO/MMC2_C MD/i2sV40_DO0
59
GND
20
-
40
-
60
GND CPU
BASE
51
SMDK6410_USER’S MANUAL_REV 1.00
MODULE4 INTERFACE CONNECTOR (FOR AUDIO DAUGHTER BOARD) PVDD_AUDIO VDD3.3V
CB80
CTB63
R354 0/R1608
+ 10uF,6.3V/T2012
[4] [4] [4] [4] [4] [4]
R356 R357 R358 R360 R362 R364
M4_Port0_I2SLRCLK/AC_SYNC M4_Port0_I2SSCLK/AC_BITCLK M4_Port0_I2SCDCLK/AC_RSTn M4_Port0_I2SLRCLK/AC_SYNC M4_Port0_I2SSCLK/AC_BITCLK M4_Port0_I2SCDCLK/AC_RSTn
0/R1608 NC/R1608 0/R1608 NC/R1608 0/R1608 NC/R1608
100nF/C1608
[4] M4_Port1_I2SCDCLK/AC_RSTn [4] M4_Port0_I2SDO/AC97_SDO [4] M4_Port0_I2SSDI/AC_SDI
[4] M4_Port1_I2SDO/AC97_SDO
R368 R369
[2,5,7,14] Xi2cSDA0 [2,5,7,14] Xi2cSCL0 [4] M4_Port1_I2SSCLK/AC_BITCLK [4] M4_Port1_I2SLRCLK/AC_SYNC [4] M4_Port1_I2SLRCLK/AC_SYNC [4] M4_Port1_I2SSCLK/AC_BITCLK [4] M4_Port1_I2SSDI/AC_SDI
R359 R361 R363
R367
0/R1608 NC/R1608 0/R1608 NC/R1608 0/R1608
0/R1608 TP78 TP80 TP82 TP84
0/R1608 0/R1608
R372 R375 R377 R380 R382
0/R1608 0/R1608 0/R1608
[2,10,13] XEINT3/KP_ROW3 [2,10,13,16] XEINT4/KP_ROW4 TP86 [2,9,13,16] XEINT6/KP_ROW6 [2,9,13,16] XEINT7/KP_ROW7 [2,10..14,16] XnRSTOUT TP89 TP90
R370 R373
0/R1608 0/R1608
R378 R381
0/R1608 0/R1608
R383
0/R1608
R355
CB81
M4 0/R1608 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
CTB64
+ 10uF,6.3V/T2012
100nF/C1608 B_HSMMC_DAT5/i2sV40_CDCLK [2,7,8,13] B_HSMMC_DAT4/i2sV40_BCLK [2,7,8,13] B_SPI1_MISO/MMC2_CMD/i2sV40_DO0 [2,7,14] B_SPI1_CLK/MMC2_CLK/i2sV40_DO1 [2,7,14] B_SPI1_CSn/i2sV40_DO2 [2,7,14] B_HSMMC_DAT7/i2sV40_DI [2,7] B_HSMMC_DAT6/i2sV40_LRCLK [2,7,8]
TP79 TP81 TP83 TP85 R371 R374 R376 R379
QSH-030-01-F-D-A
NC/R1608 NC/R1608 0/R1608 0/R1608
B_SPI0_MISO/ADDR_CF0 [2,14,16] B_SPI0_MOSI/ADDR_CF2 [2,14,16] TP87 TP88
B_PWR_5V
CB82
+ CTB65 10uF,16V/T3216
100nF/C1608
Audio (AC97, IIS, IIC) MODULE 4 Figure 29 Module4 Connector
# of pin
Descriptions
# of pin
Descriptions
# of pin
Descriptions
41
XEINT3/KP_ROW3
1
PVDD_AUDIO
21
M4_Port1_I2SSCLK/AC _BITCLK (M4_Port1_I2SLRCLK/A C_SYNC)
2
VDD3.3V
22
-
42
B_SPI0_MISO/ADDR_CF0
43
XEINT4/KP_ROW4
3
PVDD_AUDIO
23
M4_Port1_I2SLRCLK/A C_SYNC (M4_Port1_I2SSCLK/A C_BITCLK)
4
VDD3.3V
24
-
44
B_SPI0_MOSI/ADDR_CF2
5
M4_Port1_I2SCDCLK /AC_RSTn
25
M4_Port1_I2SSDI/AC_S DI
45
TP
6
B_HSMMC_DAT5/i2s V40_CDCLK
26
-
46
TP
7
M4_Port0_I2SDO/AC 97_SDO
27
M4_Port1_I2SDO/AC97 _SDO
47
XEINT6/KP_ROW6
8
B_HSMMC_DAT4/i2s V40_BCLK
28
-
48
TP
52
SMDK6410_USER’S MANUAL_REV 1.00
9
M4_Port0_I2SSDI/AC _SDI
29
GND
49
XEINT7/KP_ROW7
10
B_SPI1_MISO/MMC2 _CMD/i2sV40_DO0
30
-
50
B_PWR_5V
11
M4_Port0_I2SLRCLK/ AC_SYNC (M4_Port0_I2SSCLK/ AC_BITCLK)
31
TP
51
GND
12
B_SPI1_CLK/MMC2_ CLK/i2sV40_DO1
32
TP
52
B_PWR_5V
13
M4_Port0_I2SCDCLK /AC_RSTn (M4_Port0_I2SLRCL K/AC_SYNC)
33
TP
53
XnRSTOUT
14
B_SPI1_CSn/i2sV40_ DO2
34
TP
54
B_PWR_5V
15
M4_Port0_I2SSCLK/ AC_BITCLK (M4_Port0_I2SCDCL K/AC_RSTn)
35
TP
55
TP
16
B_HSMMC_DAT7/i2s V40_DI
36
TP
56
B_PWR_5V
17
Xi2cSDA0
37
TP
57
TP
18
B_HSMMC_DAT6/i2s V40_LRCLK
38
TP
58
B_PWR_5V
19
Xi2cSCL0
39
-
59
GND
20
-
40
GND
60
GND CPU
BASE
53
SMDK6410_USER’S MANUAL_REV 1.00
MODULE5 INTERFACE CONNECTOR (FOR LCD BOARD) (with Touch Screen) TFT LCD controllers are equipped in the S3C6410X. TFT LCD, touch panel and LCD backlight driver are supported in the SMDK6410. Part Name
Module 5
Model Name
LTE480WV-F01
Pannel Size
4.8”
#pixels
800x480
I/F type
24bit RGB
Back-Light Unit
14 LED(4pin)
Connector type
60pin
54
SMDK6410_USER’S MANUAL_REV 1.00
[2] XVD[23:0]
U40 XVD0 XVD1 XVD2 XVD3 XVD4 XVD5 XVD6 XVD7
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
16 15 14 13 12 11 10 9
M5
ECLAMP2378P
ECLAMP2378P
17
1 2 3 4 5 6 7 8
17
U42 XVD16 XVD17 XVD18 XVD19 XVD20 XVD21 XVD22 XVD23
17
U41
XVD8 XVD9 XVD10 XVD11 XVD12 XVD13 XVD14 XVD15
16 15 14 13 12 11 10 9
ECLAMP2378P VDD3.3V R394
0/R1608
PVDD_LCD R395
NC/R1608
CB85
CTB68
TP92
[2] WHITE_LED
+
[2] XVCLK
10uF,6.3V/T2012 100nF/C1608
[2] XHSY NC [2] XVSY NC [2] XVDEN R447 R448
[2] WLED_OUT1
[2,10..15] XnRSTOUT [2,10,13] XEINT5/KP_ROW5 [2,14] B_SPI0_CLK/ADDR_CF1 [2,10,13,15] XEINT4/KP_ROW4 [2,14,15] B_SPI0_MOSI/ADDR_CF2 [2,9,13,15] XEINT6/KP_ROW6 [2,14,15] B_SPI0_MISO/ADDR_CF0 [2,9,13,15] XEINT7/KP_ROW7
R400 R401
NC/R1608 0/R1608
R402 R404
NC/R1608 0/R1608
R406 R410
NC/R1608 0/R1608
R411 R412
NC/R1608 0/R1608 VDD3.3V
0/R1608
TP91
C57 100pF/C1608
[2] [2] [2] [2]
R446
Xadc_AIN4_Y M Xadc_AIN5_Y P Xadc_AIN6_XM Xadc_AIN7_XP
0/R1608 0/R1608
R396 R397 R398 R399
0/R1608 0/R1608 0/R1608 0/R1608
R403 R405 R452
0/R1608 LCD_PANNEL_ON NC/R1608 LCD_RESET 0/R1608
[2,5] PWM_TOUT1 [2,5] XPWM_ECLK [2,5] PWM_TOUT0
[2,14] B_SPI0_CSn [2,10] XhiINTR R414
R449 R413
NC/R1608 0/R1608
0/R1608
B_PWR_5V
PVDD_LCD R415
NC/R1608
LCD_SPICLK LCD_SPIMOSI LCD_SPIMISO LCD_NSS
CB86
CTB69
+ 10uF,6.3V/T2012
100nF/C1608
CB87
+ CTB70 10uF,16V/T3216
100nF/C1608
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
GF056-60S-LSS-P2000
TFT LCD MODULE 5
Figure 30 Module5 TFT LCD Connector (4.8”)
55
SMDK6410_USER’S MANUAL_REV 1.00
# of pin
Descriptions
# of pin
Descriptions
# of pin
Descriptions
1
XVD0
21
XVD21
41
Xadc_AIN5_YP
2
XVD2
22
XVD22
42
Xadc_AIN6_XM
3
XVD3
23
XVD23
43
Xadc_AIN7_XP
4
XVD4
24
XVD24
44
GND
5
XVD5
25
GND
45
PWM_TOUT1
6
XVD6
26
VDD3.3V (PVDD_LCD)
46
GND
7
XVD7
27
VDD3.3V (PVDD_LCD)
47
XPWM_ECLK
8
XVD8
28
TP
48
XEINT5/KP_ROW5 (PWM_TOUT0, XnRSTOUT)
9
XVD9
29
WHITE_LED
49
XEINT5/KP_ROW5 (PWM_TOUT0, XnRSTOUT)
10
XVD10
30
WHITE_LED
50
GND
11
XVD11
31
TP
51
XEINT4/KP_ROW4 (B_SPI0_CLK/ADDR_CF1)
12
XVD12
32
XVCLK
52
XEINT6/KP_ROW6 (B_SPI0_MOSI/ADDR_CF2)
13
XVD13
33
XHSYNC
53
XEINT7/KP_ROW7 (B_SPI0_MISO/ADDR_CF0)
14
XVD14
34
XVSYNC
54
XhiINTR (B_SPI0_CSn)
15
XVD15
35
XVDEN
55
VDD3.3V (PVDD_LCD)
16
XVD16
36
-
56
VDD3.3V (PVDD_LCD)
17
XVD17
37
WLED_OUT1
57
B_PWR_5V
18
XVD18
38
WLED_OUT1
58
B_PWR_5V
19
XVD19
39
GND
59
GND
20
XVD20
40
Xadc_AIN4_YM
60
GND CPU
BASE
56
SMDK6410_USER’S MANUAL_REV 1.00
SMDK SCHEMATIC REVISION POINTS This document contains information of corrected points on the schematic of SMDK6410. The corrected points are highlighted in pink-circled in schematic of SMDK6410 Rev 0.2.
REVISION POINTS TABLE Boards
Page 9
Contents
Corrected points (ECN: Engineer Change Note)
Damping resistor
Add R969 0 ohm.
Support Battery by PMIC module
Jack1 peripheral circuit changed.
10
Changed mDDR
U20 and U22 are changed part number from K4X51163PCFGC3 to K4X51163PE-FGC3 (FGC6).
3
Selectable NAND write protection function
Add CFG7 switch, and write protection control signal changed from XEINT1/KP_ROW1 to B_SPIO_MOSI/ADDR_CF2.
14
M1 connector
R458 and R459 are added. R307 and R308 are changed from 0 ohm to NC (Not connection).
17
Over voltage protection
Add ZD1.
CPU Board
Base Board
57
SMDK6410_USER’S MANUAL_REV 1.00
SMDK SCHEMATIC There are 2 parts of SMDK Schematic. 1. CPU Board Rev0.2 (SMC805C) 2. Base Board Rev0.2 (SMC807C) 3. LCD Board Rev0.1 (SMT710B)
Note. It is easy to find schematic parts by using Bookmarks on PDF
58
5
4
3
2
1
SMDK6410 CPU B'd (S3C6410 Evaluation Board) Schematics Revision D
Rev 0.0 Rev 0.1 Rev 0.2
Description
Date 2008. 02.20 2008. 04.02 2008. 04.30 2008. 06.18
Preliminary Version Second Version (Refer to Sheet 2,4,6,7,8,9,13,14 and 15) Third Version (Refer to Sheet 3, 8, 9 and 10) Changed boot mode table (Refer to Sheet 14), U21 not available.
D
C
C
Table of Contents
B
Part Reference
Page Function ------------------------------------------------------01 Revision History 02 S3C6410 (Addr/Data)/SW-TACT 03 S3C6410 (I/O 1) 04 S3C6410 (I/O 2)/ADC 05 S3C6410 (Power) 06 Power (ARM,INT) 07 Power (PLL,Alive,RTC)/USB Host/USB OTG 08 Power (I/O) 09 PMIC Socket 10 Memory (mDDR) 11 Buffers (SROM IF) 12 Buffers Control (SROM IF) 13 SD_MMC/SPI 14 oneNAND/MIPI/JTAG/CLK 15 Camera Interface 16 B2B Connector
--------------------------------------------------U : Component or Regurator IC C : Capacitor CB : Capacitor Bypass CT : Capacitor Tantal CTB : Capacitor Tantal Bypass J : Jumper JB : CPU or Base connector JP : Jumper Power R : Resistor RA : Resistor Array RP : Resistor Power VR : Variable Resistor L : Inductor FB : Ferrite Bead OSC : Oscillator X : X-tal (Crystal) Q : Transistor or FET D : Diode ZD : Zener Diode LED : LED Diode SW : SWitch Tact/Push CON : CONnector CFG : ConFiGure switch (DIP/Slide) TP : Test Point (SMD) TPH : Test Point Hole (Through Hole) MTH: Mount Through Hole MOD : MODule Interface connector
A
B
A
SAMSUNG ELECTRONICS CO.,LTD Title SMDK6410 CPU Board (S3C6410 Evaluation Board) Size A3 Date: 5
4
3
2
Document Number Revision History Wednesday, June 18, 2008
Rev 0.2 Sheet 1
1
of
16
5
4
3
2
1
B
Xm1WEn Xm1CASn Xm1RASn Xm1SCLKn Xm1SCLK Xm1CKE1 Xm1CKE0
M19 L24 L22 A14 A13 M24 M18
R963 R964 R965 R966 R967
10/R1005 10/R1005 10/R1005 10/R1005 10/R1005
CB1
Xm1CSn1 [10] Xm1CSn0 [10] [10] [10] [10] [10] [10] [10] [10] [10]
5 3
WRESET TP2
4
XWRESET [3]
1 2
3
3 4
SN74LVC1G17DBV
WRESET
B
SW2 SW-TACT (Gray)
Xm0DQM1/BE1 [10,11] Xm0DQM0/BE0 [10,11]
VDD_D CB3
R11
3 4
100K/R1005
nRESET
5
5
100nF
U6
VCC nRESET
3
nMR
2
GND
XnRESET TP4
U5
2
4
SRT
1
nRESET [9]
4
MAX6412UK22
C1
SW3 1 2
VDD_D R14 10K/R1005
5
ONKEYn TP3
100nF
U4
100K/R1005
10K/R1005
SW-TACT (Red)
100nF A
R15
PMIC_ONKEYn [9] 0/R1005
XnRESET [3,6,14,16]
SN74LVC1G11DBV
SN74LVC1G17DBV 3
4
3 4
1 3 6
SAMSUNG ELECTRONICS CO.,LTD Title
2
SMDK6410 CPU Board (S3C6410 Evaluation Board) 1 2
PMIC ON
SW4 SW-TACT (Red)
5
100nF
U3
2 Xm0AP [10] Xm0WEndmc [10] Xm0DQS1 [10] Xm0DQS0 [10] Xm0CKE [10] Xm0SCLKn [10] Xm0SCLK [10] Xm0CASn [10] Xm0RASn [10]
R12
NC/R1005
C
SW-TACT (Gray)
100K/R1005
CB4
R18
XnBATF [3,9]
SW1
CB2
VDD_D
[9] PMIC_nRST_OUT
4 SN74LVC1G17DBV
nBATF
Xm1WEn [10] Xm1CASn [10] Xm1RASn [10] Xm1SCLKn [10] Xm1SCLK [10] Xm1CKE1 [10] Xm1CKE0 [10]
C_PWR_5V
0/R1005 0/R1005
nBATF TP1
U2
2
3 4
Xm1DQS3 Xm1DQS2 Xm1DQS1 Xm1DQS0 Xm1DQM3 Xm1DQM2 Xm1DQM1 Xm1DQM0
100K/R1005
[12] Xm0INTata/SS_REAL_IN [12] Xm0RSTata/SS_IMG_IN [12] Xm0INPACKata/SS_TCXO_CLK [12] Xm0REGata/SS_GPO0 [12] Xm0WEata/SS_GPO1 [12] Xm0OEata/SS_GPO2 [12] Xm0CData/SS_GPO3
R16 R17
100nF
R10
[11] Xm0WAITn/IORDY [11,14] Xm0RDY0/ALE [11,14] Xm0RDY1/CLE [11,14] Xm0INTsm0/FWEn [11,12,14] Xm0INTsm1/FREn [14] Xm0RPn/RnB
[9] nRESET [16] AP_nRESET [16] Modem_nRESET
D
VDD_D
Xm0CSn0 Xm0CSn1 Xm0CSn2 Xm0CSn3 Xm0CSn4 Xm0CSn5
R13
[11] [11] [11] [11]
R9
[10,12] Xm0CSn7
A
10K/R1005
10/R1005 10/R1005 10/R1005 10/R1005 10/R1005 10/R1005 10/R1005 10/R1005
10K/R1005
R955 R956 R957 R958 R959 R960 R961 R962
R8
E25 B14 G9 D9 H22 D14 G8 A5
10K/R1005
Xm1DQS3 Xm1DQS2 Xm1DQS1 Xm1DQS0 Xm1DQM3 Xm1DQM2 Xm1DQM1 Xm1DQM0
R7
L18 L23
R5
Xm1CSn1 Xm1CSn0
Xm0ADDR16 Xm0ADDR17 Xm0ADDR18 Xm0ADDR19
VDD_D
5
Xm0RAS/ADDR18/GPQ0 Xm0CAS/ADDR19/GPQ1 Xm0SCLK/GPQ2 Xm0SCLKn/GPQ3 Xm0CKE/GPQ4 Xm0DQS0/GPQ5 Xm0DQS1/GPQ6 Xm0WEndmc/ADDR17/GPQ7 Xm0APdmc/ADDR16/GPQ8
Xm0DQM0/BE0 Xm0DQM1/BE1
L25 M17 K22 K24 K19 M23 J22 K23 K18 J25 K25 L19 H25 J23 J24 H24
U2 P8 T1 U1 V3 T4 V2 U3 J1
L1 K7
Xm0INTata/SS_REALIN/GPP8 Xm0RSTata/SS_IMGIN/GPP9 Xm0INPACKata/SS_TCXO/GPP10 Xm0REGata/SS_GPO0/GPP11 Xm0WEata/SS_GPO1/GPP12 Xm0OEata/SS_GPO2/GPP13 Xm0CData/SS_GPO3/GPP14
Xm1ADDR[15:0] [10] Xm1ADDR15 Xm1ADDR14 Xm1ADDR13 Xm1ADDR12 Xm1ADDR11 Xm1ADDR10 Xm1ADDR9 Xm1ADDR8 Xm1ADDR7 Xm1ADDR6 Xm1ADDR5 Xm1ADDR4 Xm1ADDR3 Xm1ADDR2 Xm1ADDR1 Xm1ADDR0
Xm1ADDR15 Xm1ADDR14 Xm1ADDR13 Xm1ADDR12 Xm1ADDR11 Xm1ADDR10 Xm1ADDR9 Xm1ADDR8 Xm1ADDR7 Xm1ADDR6 Xm1ADDR5 Xm1ADDR4 Xm1ADDR3 Xm1ADDR2 Xm1ADDR1 Xm1ADDR0
1 2
[11,12] [11,12] [14] [14] [11,12] [11,12]
R7 W3 AA2 AA3 V4 AB3 U7
Xm0OEn/nIORD_CF Xm0WEn/nIOWR_CF Xm0ADV/GPP0 Xm0SMCLK/GPP1
Xm0WAITn/IORDY/GPP2 Xm0RDY0/ALE/GPP3 Xm0RDY1/CLE/GPP4 Xm0INTsm0/FWEn/GPP5 Xm0INTsm1/FREn/GPP6 Xm0RPn/RnB/GPP7
L4 J2 Y2 L3
Xm0OEn/nIORD_CF Xm0WEn/nIOWR_CF Xm0ADV Xm0SMCLK
R4 R8 W2 Y3 U4 Y1
Xm0DATA0 Xm0DATA1 Xm0DATA2 Xm0DATA3 Xm0DATA4 Xm0DATA5 Xm0DATA6 Xm0DATA7 Xm0DATA8 Xm0DATA9 Xm0DATA10 Xm0DATA11 Xm0DATA12 Xm0DATA13 Xm0DATA14 Xm0DATA15
U1A S3C6410
NC/R1005 NC/R1005 NC/R1005 NC/R1005 10K/R1005
H23 G25 G23 E24 G24 F25 F24 F23 D16 B15 D15 C15 C13 A12 B13 B12 D10 C11 B10 A11 D11 C12 A10 D12 C9 A9 C8 C6 B7 C7 A6 B6 N2 N1 M7 N3 M8 P2 N4 P3 M2 M4 L7 M3 L8 L2 K4 K1
N7 R3 P4 R2 T3 N8 T2 P7
[11,12,14] [11,14] [14] [14]
Xm0DATA0 Xm0DATA1 Xm0DATA2 Xm0DATA3 Xm0DATA4 Xm0DATA5 Xm0DATA6 Xm0DATA7 Xm0DATA8 Xm0DATA9 Xm0DATA10 Xm0DATA11 Xm0DATA12 Xm0DATA13 Xm0DATA14 Xm0DATA15
Xm0ADDR0 Xm0ADDR1 Xm0ADDR2 Xm0ADDR3 Xm0ADDR4 Xm0ADDR5 Xm0ADDR6/GPO6 Xm0ADDR7/GPO7 Xm0ADDR8/GPO8 Xm0ADDR9/GPO9 Xm0ADDR10/GPO10 Xm0ADDR11/GPO11 Xm0ADDR12/GPO12 Xm0ADDR13/GPO13 Xm0ADDR14/GPO14 Xm0ADDR15/GPO15
Xm0CSn0 Xm0CSn1 Xm0CSn2/GPO0 Xm0CSn3/GPO1 Xm0CSn4/GPO2 Xm0CSn5/GPO3 Xm0CSn6/GPO4 Xm0CSn7/GPO5
C
C1 E3 D1 D2 H7 E1 F2 G4 F1 J8 G2 G1 H4 H2 J4 H3
Memory Port1
[10,11,14] Xm0DATA[15:0]
Xm0ADDR0 Xm0ADDR1 Xm0ADDR2 Xm0ADDR3 Xm0ADDR4 Xm0ADDR5 Xm0ADDR6 Xm0ADDR7 Xm0ADDR8 Xm0ADDR9 Xm0ADDR10 Xm0ADDR11 Xm0ADDR12 Xm0ADDR13 Xm0ADDR14 Xm0ADDR15
Xm1DATA31 Xm1DATA30 Xm1DATA29 Xm1DATA28 Xm1DATA27 Xm1DATA26/Xm0ADDR26 Xm1DATA25/Xm0ADDR25 Xm1DATA24/Xm0ADDR24 Xm1DATA23/Xm0ADDR23 Xm1DATA22/Xm0ADDR22 Xm1DATA21/Xm0ADDR21 Xm1DATA20/Xm0ADDR20 Xm1DATA19/Xm0ADDR19 Xm1DATA18/Xm0ADDR18 Xm1DATA17/Xm0ADDR17 Xm1DATA16/Xm0ADDR16 Xm1DATA15 Xm1DATA14 Xm1DATA13 Xm1DATA12 Xm1DATA11 Xm1DATA10 Xm1DATA9 Xm1DATA8 Xm1DATA7 Xm1DATA6 Xm1DATA5 Xm1DATA4 Xm1DATA3 Xm1DATA2 Xm1DATA1 Xm1DATA0
[10,11] Xm0ADDR[15:0]
Memory Port0
D
R1 R2 R3 R4
[10] Xm0AP [10] Xm0WEndmc [10] Xm0RASn [10] Xm0CASn
R6
Xm1DATA31 Xm1DATA30 Xm1DATA29 Xm1DATA28 Xm1DATA27 Xm1DATA26 Xm1DATA25 Xm1DATA24 Xm1DATA23 Xm1DATA22 Xm1DATA21 Xm1DATA20 Xm1DATA19 Xm1DATA18 Xm1DATA17 Xm1DATA16 Xm1DATA15 Xm1DATA14 Xm1DATA13 Xm1DATA12 Xm1DATA11 Xm1DATA10 Xm1DATA9 Xm1DATA8 Xm1DATA7 Xm1DATA6 Xm1DATA5 Xm1DATA4 Xm1DATA3 Xm1DATA2 Xm1DATA1 Xm1DATA0
Xm1DATA[31:0] [10]
4
3
2
Size A3
Document Number S3C6410 (Addr/Data)/SW-TACT
Date:
Wednesday, June 18, 2008
Rev 0.2 Sheet 1
2
of
16
5
4
3
[14] [14] [14] [14] [14] D
2
XEFFVDD XnRSTOUT TP5 TP6
XOM4 XOM3 XOM2 XOM1 XOM0
XPWRRGTON TP7
XPWRRGTON [7,9] XnBATF [2,9] XSELNAND [14]
[14] XDBGSEL [14] XRTCK [14] XTDO [14] XTDI [14] XTCK [14] XTMS [14] XTRSTn
XnRESET [2,6,14,16] XWRESET [2] XnRSTOUT [16]
XspiMISO0/ADDR_CF0/GPC0 XspiCLK0/ADDR_CF1/GPC1 XspiMOSI0/ADDR_CF2/GPC2 HS-SPI XspiCS0/GPC3 XspiMISO1/mmcCMD2/GPC4/Xi2sV40_DO0 XspiCLK1/mmcCLK2/GPC5/Xi2sV40_DO1 XspiMOSI1/GPC6 XspiCS1/GPC7/Xi2sV40_DO2
N22 P22
XusbDP XusbDN
OTG2.0
A18 G13 B18 H13 C18 G12
B
XmmcCLK0/ADDR_CF0/GPG0 XmmcCMD0/ADDR_CF1/GPG1 XmmcDATA0_0/ADDR_CF2/GPG2 XmmcDATA0_1/GPG3 XmmcDATA0_2/GPG4 XmmcDATA0_3/GPG5
XotgDP XotgDM XotgTI XotgTO XREXT XVBUS XotgID XotgDRV_VBUS
HS-MMC
V9 AD15 AD16
AD14 AE15 AB16 T7
XnRESET XWRESET XnRSTOUT
B20 H14 A19 C20 B19 H12 C19 D17
U1B S3C6410
CLOCK XEXTCLK XXTO XXTI X27MXTO X27MXTI XrtcXTO XrtcXTI
W11 AC17 AC16 AB14 AB15 AD12 AB9
XEXTCLK [14] XXTO [14] XXTI [14] X27MXTO [14] X27MXTI [14] XrtcXTO [14] XrtcXTI [14]
D23 H16 C23
XPWM_TOUT1 XPWM_TOUT0 XPWM_ECLK [8,13,16]
AE17 V10 AD17 AB17 AE18 AC18 V11 AC19 W12 AE19 AB18 AD19 V12 AE20 W13 AD20
XEINT0/KP_ROW0 [16] XEINT1/KP_ROW1 [16] XEINT2/KP_ROW2 [16] XEINT3/KP_ROW3 [16] XEINT4/KP_ROW4 [16] XEINT5/KP_ROW5 [16] XEINT6/KP_ROW6 [16] XEINT7/KP_ROW7 [8,16] XEINT8/ADDR_CF0 [16] XEINT9/ADDR_CF1 [16] XEINT10/ADDR_CF2 [16] XEINT11 [6,16] R20
PWM Timer XpwmTOUT1/GPF15 XpwmTOUT0/XCLKOUT/GPF14 XpwmECLK/GPF13 XEINT0/kpROW0/GPN0 XEINT1/kpROW1/GPN1 XEINT2/kpROW2/GPN2 XEINT3/kpROW3/GPN3 XEINT4/kpROW4/GPN4 XEINT5/kpROW5/GPN5 XEINT6/kpROW6/GPN6 XEINT7/kpROW7/GPN7 XEINT8/ADDR_CF0/GPN8 XEINT9/ADDR_CF1/GPN9 XEINT10/ADDR_CF2/GPN10 XEINT11/GPN11 XEINT12/GPN12 XEINT13/GPN13 XENT14/GPN14 XEINT15/GPN15
EINT
XpcmDCLK0/I2sCLK/BITCLK/ADDR_CF0/GPD0 XpcmEXTCLK0/i2sCDCLK/RESETn/ADDR_CF1/GPD1 XpcmFSYNC0/i2sLRCK/SYNC/ADDR_CF2/GPD2 XpcmSIN0/i2sDI/SDI/GPD3 XpcmSOUT0/i2sDO/SDO/GPD4 XpcmDCLK1/i2sCLK/BITCLK/GPE0 XpcmEXTCLK1/i2sCDCLK/RESETn/GPE1 XpcmFSYNC1/i2sLRCK/SYNC/GPE2 XpcmSIN1/i2sDI/SDI/GPE3 XpcmSOUT1/i2sDO/SDO/GPE4
Xi2cSCL0/GPB5 Xi2cSDA0/GPB6
I2C
XPWRRGTON XnBATF XSELNAND XEFFVDD
AD13 W9 AC13 V8 AE14
A20 G14
AE10 AE9 AD7 AD8 AC8 AD9 AD10 AE11
[7] XotgDP [7] XotgDM [7] XotgTI [7] XotgTO [7] XREXT [7,9] XVBUS [7] XotgID [7] XotgDRV_VBUS
XOM0 XOM1 XOM2 XOM3 XOM4
XuRXD0/GPA0 XuTXD0/GPA1 XuCTSn0/GPA2/ADDR_CF0 JTAG XuRTSn0/GPA3/ADDR_CF1 XuRXD1/GPA4 XuTXD1/GPA5 XuCTSn1/GPA6/ADDR_CF0 UART/IrDA XuRTSn1/GPA7/ADDR_CF1 XuRXD2/ExdREQ/IrRXD/GPB0/ADDR_CF0 XuTXD2/ExdACK/IrTXD/GPB1/ADDR_CF1 XuRXD3/IrRXD/ExdREQ/GPB2/ADDR_CF2/Xi2cSCL1 XuTXD3/IrTXD/ExdACK/GPB3/Xi2cSDA1 XirSDBW/XcamFIELD/BUF_DIR/GPB4
USBH [7] XusbhDP [7] XusbhDN
R19
XEINT13 [6,13,16] XEINT14 [6,16] XEINT15 [6,16]
R21
C
0/R1005
XEINT12 [6,13,16]
NC/R1005
PMIC_XEINT12_IRQn [9]
Audio
B
D7 B5 D6 B4 A3 C5 B3 C4 B2 C3
[13] XspiMISO0/ADDR_CF0 [13] XspiCLK0/ADDR_CF1 [13] XspiMOSI0/ADDR_CF2 [13] XspiCS0 [13] XspiMISO1/mmcCMD2 [13] XspiCLK1/mmcCLK2 [13] XspiMOSI1 [13] XspiCS1
XTRSTn XTMS XTCK XTDI XTDO XRTCK XDBGSEL
AB10 AE12 AB11 AB12 AC12 AE13 AB13 C
D20 A23 G16 A22 J15 B22 H15 C22 D19 A21 J14 B21 G15
XmmcCDN0/mmcCDN1/GPG6 XmmcCLK1/kpCOL0/ADDR_CF0/GPH0 XmmcCMD1/kpCOL1/ADDR_CF1/GPH1 XmmcDATA1_0/kpCOL2/ADDR_CF2/GPH2 XmmcDATA1_1/kpCOL3/GPH3 XmmcDATA1_2/kpCOL4/GPH4 XmmcDATA1_3/kpCOL5/GPH5 XmmcDATA1_4/mmcDATA2_0/kpCOL6/i2sV40_BCLK/ADDR_CF0/GPH6 XmmcDATA1_5/mmcDATA2_1/kpCOL7/i2sV40_CDCLK/ADDR_CF1/GPH7 XmmcDATA1_6/mmcDATA2_2/i2sV40_LRCLK/ADDR_CF2/GPH8 XmmcDATA1_7/mmcDATA2_3/i2sV40_DI/GPH9
[9,15,16] Xi2cSCL0 [9,15,16] Xi2cSDA0
D
0/R1005
A17 J11 A16 H11 C17 B16 H10 A15 G11 C16 H9
[16] XuRXD_0 [16] XuTXD_0 [16] XuCTSn_0/ADDR_CF0 [16] XuRTSn_0/ADDR_CF1 [16] XuRXD_1 [16] XuTXD_1 [16] XuCTSn_1/ADDR_CF0 [16] XuRTSn_1/ADDR_CF1 [16] XuRXD_2/ExdREQ/IrRXD/ADDR_CF0 [16] XuTXD_2/ExdACK/IrTXD/ADDR_CF1 [11,16] XuRXD_3/ExdREQ/IrRXD/ADDR_CF2/Xi2cSCL1 [16] XuTXD_3/ExdACK/IrTXD/Xi2cSDA1 [12,15,16] XirSDBW
1
VDD_D [13] XmmcCLK0/ADDR_CF0 [13] XmmcCMD0/ADDR_CF1 [13] XmmcDATA0_0/ADDR_CF2 [13] XmmcDATA0_1 [13] XmmcDATA0_2 [13] XmmcDATA0_3
Changed on 04/30/2008
[13] XmmcCDN0/mmcCDN1 [13] XmmcCLK1/ADDR_CF0 [13] XmmcCMD1/ADDR_CF1 [13] XmmcDATA1_0/ADDR_CF2 [13] XmmcDATA1_1 [13] XmmcDATA1_2 [13] XmmcDATA1_3 [13] XmmcDATA1_4/mmcDATA2_0/ADDR_CF0 [13] XmmcDATA1_5/mmcDATA2_1/ADDR_CF1 [13] XmmcDATA1_6/mmcDATA2_2/ADDR_CF2 [13] XmmcDATA1_7/mmcDATA2_3
R23
2K/R1005
2K/R1005
[9,15,16] Xi2cSDA0 [9,15,16] Xi2cSCL0
XCLKOUT TP8
[9,16] XPCM_DCLK0/I2S_CLK0/AC97_BITCLK0/ADDR_CF0 [9,16] XPCM_EXTCLK0/I2S_CDCLK0/AC97_RSTn0/ADDR_CF1 [9,16] XPCM_FSYNC0/I2S_LRCLK0/AC97_SYNC0/ADDR_CF2 [9,16] XPCM_SIN0/I2S_DI0/AC97_SDI0 [9,16] XPCM_SOUT0/I2S_DO0/AC97_SDO0 [9,16] XPCM_DCLK1/I2S_CLK1/AC97_BITCLK0 [9,16] XPCM_EXTCLK1/I2S_CDCLK1/AC97_RSTn0 [9,16] XPCM_FSYNC1/I2S_LRCLK1/AC97_SYNC0 [9,16] XPCM_SIN1/I2S_DI1/AC97_SDI0 [9,16] XPCM_SOUT1/I2S_DO1/AC97_SDO0
A
R22
XPWM_TOUT0 XPWM_TOUT1
R24 R25
0/R1005 0/R1005
PWM_TOUT0 [16] PWM_TOUT1 [16] A
SAMSUNG ELECTRONICS CO.,LTD Title SMDK6410 CPU Board (S3C6410 Evaluation Board) Size A3 Date:
5
4
3
2
Document Number S3C6410 (I/O 1) Wednesday, June 18, 2008
Rev 0.2 Sheet 1
3
of
16
4
D
[16] [16] [16] [16] [16] [16] [16] [16]
Xhi_A0/ADDR_CF0/KP_COL0 Xhi_A1/ADDR_CF1/KP_COL1 Xhi_A2/ADDR_CF2/KP_COL2 Xhi_A3/KP_COL3/Xm0INTata Xhi_A4/KP_COL4/Xm0RSTata Xhi_A5/KP_COL5/Xm0INPACKata Xhi_A6/KP_COL6/Xm0REGata Xhi_A7/KP_COL7/Xm0CData [6,16] Xhi_A8/CE_CF0 [6,16] Xhi_A9/CE_CF1 [6,16] Xhi_A10/IORD_CF [16] Xhi_A11/IOWR_CF [16] Xhi_A12/IORDY_CF
[16] [16] [16] [16] [16]
C
VDD_DAC C2
100nF
XciCLK/GPF0 XciHREF/GPF1 XciPCLK/GPF2 XciRSTn/GPF3 XciVSYNC/GPF4 XciYDATA0/GPF5 XciYDATA1/GPF6 XciYDATA2/GPF7 XciYDATA3/GPF8 XciYDATA4/GPF9 XciYDATA5/GPF10 XciYDATA6/GPF11 XciYDATA7/GPF12
AC6 AE5 AE6 AE7 AC7
XdacOUT_0 XdacOUT_1 XdacIREF XdacVREF XdacCOMP
AC1 AC2 AD2 AD3 AE3 AD4 AE4 AC3
Xadc_AIN0 Xadc_AIN1 Xadc_AIN2 Xadc_AIN3 Xadc_AIN4 Xadc_AIN5 Xadc_AIN6 Xadc_AIN7
[15] XciYDATA[7:0] [16] XdacOUT_0 [16] XdacOUT_1
DAC(TV)
DACVREF TP9
XciYDATA0 XciYDATA1 XciYDATA2 XciYDATA3 XciYDATA4 XciYDATA5 XciYDATA6 XciYDATA7
G22 D25 F22 H19 D24 C25 E23 C24 G18 H17 B24 G17 B23
100nF 6.49K/R1005
Xadc_AIN0 Xadc_AIN1 Xadc_AIN2 Xadc_AIN3 Xadc_AIN4 Xadc_AIN5 Xadc_AIN6 Xadc_AIN7
Y4
XpllEFLITER
B
DISPLAY
1.8nF
1
D
XhiCSnmain/CE_CF1 XhiCSn/CE_CF0 XhiCSn_sub/CF_IORD XhiWEn/CF_IOWR XhiOEn/CF_IORDY [8,12,16] XhiINTR
XhiINTR/BUF_DIR/GPM5 XhiOEn/CF_IORDY/EINT27/GPM4 XhiWEn/CF_IOWR/EINT26/GPM3 XhiCSn_sub/CF_IORD/EINT25/GPM2 XhiCSn/CE_CF0/EINT23/GPM0 XhiCSnmain/CE_CF1/EINT24/GPM1
XhiDATA17/EINT22/GPL14 XhiDATA16/EINT21/GPL13 XhiDATA15/kpROW7/CF_DATA15/GPK15 XhiDATA14/kpROW6/CF_DATA14/GPK14 XhiDATA13/kpROW5/CF_DATA13/GPK13 XhiDATA12/kpROW4/CF_DATA12/GPK12 XhiDATA11/kpROW3/CF_DATA11/GPK11 XhiDATA10/kpROW2/CF_DATA10/GPK10 XhiDATA9/kpROW1/CF_DATA9/GPK9 XhiDATA8/kpROW0/CF_DATA8/GPK8 XhiDATA7/txDATA/CF_DATA7/GPK7 XhiDATA6/txFLAG/CF_DATA6/GPK6 XhiDATA5/txWAKE/CF_DATA5/GPK5 XhiDATA4/txREADY/CF_DATA4/GPK4 XhiDATA3/rxDATA/CF_DATA3/GPK3 XhiDATA2/rxFLAG/CF_DATA2/GPK2 XhiDATA1/rxWAKE/CF_DATA1/GPK1 XhiDATA0/rxREADY/CF_DATA0/GPK0
AE21 XvVD0/GPI0 W14 XvVD1/GPI1 AE22 XvVD2/GPI2 V13 XvVD3/GPI3 AD21XvVD4/GPI4 AB20 XvVD5/GPI5 W15 XvVD6/GPI6 AE23 XvVD7/GPI7 V14 XvVD8/GPI8 AC21XvVD9/GPI9 AC22XvVD10/GPI10 W16 XvVD11/GPI11 V15 XvVD12/GPI12 AD23XvVD13/GPI13 W17 XvVD14/GPI14 AC24XvVD15/GPI15 V16 XvVD16/GPJ0 AD24XvVD17/GPJ1 Y22 XvVD18/GPJ2 AC25XvVD19/GPJ3 AB25 XvVD20/GPJ4 AB24 XvVD21/GPJ5 W18 XvVD22/GPJ6 AB23 XvVD23/GPJ7
C3
S3C6410
Host I/F
R26
U1C
ADC
CB5
XhiADDR12/EINT20/GPL12 XhiADDR11/EINT19/GPL11 XhiADDR10/EINT18/GPL10 XhiADDR9/EINT17/GPL9 XhiADDR8/EINT16/GPL8 XhiADDR7/kpCOL7/Xm0CData/GPL7 XhiADDR6/kpCOL6/Xm0REGata/GPL6 XhiADDR5/kpCOL5/Xm0INPACKata/GPL5 XhiADDR4/kpCOL4/Xm0RSTata/GPL4 XhiADDR3/kpCOL3/Xm0INTata/GPL3 XhiADDR2/kpCOL2/CF_ADDR2/GPL2 XhiADDR1/kpCOL1/CF_ADDR1/GPL1 XhiADDR0/kpCOL0/CF_ADDR0/GPL0
XciCLK XciHREF XciPCLK XciRSTn XciVSYNC
CAM I/F
[15] [15] [15] [15] [15]
2
Xhi_D8/DATA_CF8/KP_ROW0 Xhi_D9/DATA_CF9/KP_ROW1 Xhi_D10/DATA_CF10/KP_ROW2 Xhi_D11/DATA_CF11/KP_ROW3 Xhi_D12/DATA_CF12/KP_ROW4 Xhi_D13/DATA_CF13/KP_ROW5 Xhi_D14/DATA_CF14/KP_ROW6 Xhi_D15/DATA_CF15/KP_ROW7 [16] Xhi_D16/DATA_CF8 [16] Xhi_D17/DATA_CF9
R19 U23 U24 T19 U25 T18 V23 V25 U22 W23 U18 W24 U19
[16] [16] [16] [16] [16] [16] [16] [16]
3
W25 V22 Y23 Y24 AA23 V18
C
M25 N17 N23 N18 N24 N25 P18 P23 P19 P25 R25 R24 R22 R23 T23 T24 T22 T25
AA25 XvHSYNC/GPJ8 W22 XvVSYNC/GPJ9 AA24 XvVDEN/GPJ10 V19 XvVCLK/GPJ11
5
B
XVD23 XVD22 XVD21 XVD20 XVD19 XVD18 XVD17 XVD16 XVD15 XVD14 XVD13 XVD12 XVD11 XVD10 XVD9 XVD8 XVD7 XVD6 XVD5 XVD4 XVD3 XVD2 XVD1 XVD0
[16] [16] [16] [16] [16]
XVD[23:0] XHSYNC XVSYNC XVDEN XVCLK
ADC
CON1 [14] [14] [14] [14] [14] [14] [14] [14]
Xhi_D0/rxREADY/DATA_CF0 Xhi_D1/rxWAKE/DATA_CF1 Xhi_D2/rxFLAG/DATA_CF2 Xhi_D3/rxDATA/DATA_CF3 Xhi_D4/txREADY/DATA_CF4 Xhi_D5/txWAKE/DATA_CF5 Xhi_D6/txFLAG/DATA_CF6 Xhi_D7/txDATA/DATA_CF7
Xadc_AIN0 Xadc_AIN1 Xadc_AIN2 Xadc_AIN3
1 3 5 7 9
2 4 6 8 10
Xadc_AIN4 Xadc_AIN5 Xadc_AIN6 Xadc_AIN7
HDR10-2.54-MALE
A
R27 R28 R29 R30
0/R1005 0/R1005 0/R1005 0/R1005
Xadc_AIN4_YM Xadc_AIN5_YP Xadc_AIN6_XM Xadc_AIN7_XP
[16] [16] [16] [16]
A
SAMSUNG ELECTRONICS CO.,LTD Title SMDK6410 CPU Board (S3C6410 Evaluation Board) Size A3 Date: 5
4
3
2
Document Number S3C6410 (I/O 2)/ADC Wednesday, June 18, 2008
Rev 0.2 Sheet 1
4
of
16
5
4
3
2
VDD_LCD
VDD_SYS
VDD_MMC
VDD_PCM
VDD_UH
AE2 AD1 AD25 AE24 B25 A24 A2 B1
VDD_RTC
1
VDD_ARM0 VDD_ARM1 VDD_ARM2 VDD_ARM3 VDD_ARM4 VDD_ARM5 VDD_ARM6 VDD_ARM7 VDD_ARM8 VDD_ARM9
A7 D13 D18 H1 J18 L17 M22 P1 W1 Y25 AC20 AE16
VDD_INT0 VDD_INT1 VDD_INT2 VDD_INT3 VDD_INT4 VDD_INT5 VDD_INT6 VDD_INT7 VDD_INT8 VDD_INT9 VDD_INT10 VDD_INT11
R18 U15 AB19 W10
VDD_ALIVE0 VDD_ALIVE1 VDD_ALIVE2 VDD_ALIVE3
CTB2 CB7
+ VSS_SS
A8 B11 C2 C10 D3 D8 E2 F3 J3 K3
VDD_INT
U1D
S3C6410
P9
100nF
VSS_OTGI VSS_OTG1 VSS_OTG0
AB8 AE8 AB7
VSS_DAC VSS_ADC
AC5 AD5
VSS_PERI7 VSS_PERI6 VSS_PERI5 VSS_PERI4 VSS_PERI3 VSS_PERI2 VSS_PERI1 VSS_PERI0
AC14 V17 U14 U12 U11 R17 J13 H18
VSS_MEM5 VSS_MEM4 VSS_MEM3 VSS_MEM1 VSS_MEM0
AB6 W8 U8 M9 J7
VSS_MPLL VSS_EPLL VSS_APLL
T8 V7 W4
0/R1005
CTB4 CB10
10uF/6.3V/T2012
VDD_EXT
CTB5 CB11
+
CTB6 CB12
+
100nF 100nF
10uF/6.3V/T2012
VDD_HI
CB9
+ 100nF
10uF/6.3V/T2012 R204
CTB3 CB8
+
100nF
10uF/6.3V/T2012
VDD_OTGI
+ 100nF
100nF
10uF/6.3V/T2012
1uF/6.3V/T2012
VDD_OTG
VDD_OTG1
FB1
CTB7 CB13 CB14
CTB8 CB15
+
BLM18BPG121 CTB10 CB19 CB20 CB21
CTB9 CB16 CB17 CB18
+
+
+ 1uF
100nF 100nF
CTB11 CB22
+ 1uF
100nF
10uF/6.3V/T2012
100nF 10nF
10uF/6.3V/T2012
D
100nF 10nF
10uF/6.3V/T2012
1uF
10uF/6.3V/T2012 10uF/6.3V/T2012
VDD_ALIVE
AC4 VDD_ADC AD6 VDD_DAC
AC15VDD_SYS0 AD18VDD_SYS1 AC23VDD_LCD0 AD22VDD_LCD1 B17 VDD_MMC A4 VDD_PCM P24 VDD_HI0 V24 VDD_HI1 C21 VDD_EXT N19 VDD_UH AC9 VDD_OTG0 AD11VDD_OTG1 AC10VDD_OTGI
VDD_MEM0_0 VDD_MEM0_1 VDD_MEM0_2 VDD_MEM0_3 VDD_MEM0_4
VDD_MEM1_0 VDD_MEM1_1 VDD_MEM1_2 VDD_MEM1_3 VDD_MEM1_4 B8 B9 C14 G10 J19
V1
VDD_SS
VDD_APLL VDD_EPLL VDD_MPLL
F4 G3 K2 M1 R1
AA1 AB1 AB2
VDD_APLL VDD_EPLL VDD_MPLL
AC11VDD_RTC
C
CTB1 CB6
NC7 NC6 NC5 NC4 NC3 NC2 NC1 NC0
VDD_ARM D
VSS_IP7 VSS_IP6 VSS_IP5 VSS_IP4 VSS_IP3 VSS_IP2 VSS_IP1 VSS_IP0
C
VDD_MEM0
U13 P17 R9 N9 L9 K8 J12 H8
CTB12
VDD_MEM1
CTB13
+
CB23 CB24 CB25 CB26 CB27 CB28
+
CTB14
+
CTB15 CB29 CB30 CB31 CB32 CB33
+
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 10uF/6.3V/T2012 10uF/6.3V/T2012
VDD_DAC
VDD_ADC
10uF/6.3V/T2012 10uF/6.3V/T2012
VDD_DAC
VDD_MPLL
VDD_APLL
VDD_EPLL
VDD_ALIVE
VDD_SS
FB2
VDD_SS
BLM18BPG121 CTB16 CB34
VDD_RTC VDD_MEM0
100nF
100nF
VDD_OTG
VDD_LCD
+
CTB20 CB38
CTB21 CB39
+
CTB22 CB40
+
+
100nF
100nF
100nF
100nF
100nF
B
10uF/6.3V/T2012
10uF/6.3V/T2012
10uF/6.3V/T2012
10uF/6.3V/T2012
10uF/6.3V/T2012
10uF/6.3V/T2012
VDD_UH
VDD_MMC VDD_PCM
CTB19 CB37
+
10uF/6.3V/T2012
VDD_OTG1
VDD_SYS
CTB18 CB36
CTB17
VDD_OTGI
VDD_MEM1
B
+
+
CB35
VDD_EXT VDD_HI
VDD_ARM
VDD_INT
A
A
CTB23
+
CTB24
CB41 CB42 CB43 CB44 CB45 CB46 CB47
+
CTB25
+
CTB26
+
CTB27 CB48 CB49 CB50 CB51 CB52 CB53 CB54 CB55 CB56
+
SAMSUNG ELECTRONICS CO.,LTD 100nF 100nF 100nF 100nF 100nF 100nF 100nF
Title
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
SMDK6410 CPU Board (S3C6410 Evaluation Board) 10uF/6.3V/T2012 10uF/6.3V/T2012
Size A3
10uF/6.3V/T2012 10uF/6.3V/T2012 10uF/6.3V/T2012
Date: 5
4
3
2
Document Number S3C6410 (Power) Wednesday, June 18, 2008
Rev 0.2 Sheet 1
5
of
16
5
4
3
2
1
C_PWR_5V R34 100K/R1005
VDD_D R32 100K/R1005
R33 100K/R1005
CT1 R35 330K/R1005
[7] XPWRRGTON_SW [8] CORE_PWR_OK
R37
NC/R1005
10
R38 VDD_D
7 R36 100K/R1005
SN74LVC573APW C6
6.8nF
8
U9A R40
1 7 SN74LVC2G08DCTR 10K/R1005
PGDOD
VIN
27
TG
5
2
SW
4
FDS6982
BOOST
6
VID0 VID1 VID2 VID3 VID4
D
Q1A
C5
28 26
JP1
330pF
2
INTVCC EXTVCC
VON
14
ITH
20 22 19
SGND
18 17
OPOUT OP+
SENSE
3
FCB
BG
1
VFB
PGND
2
CT2
1
VDD_ARM
A2-2PA-2.54DSA L1 2.2uH (LQH32CN2R2M33)
D1
11
C9 500pF
4
R41
3
1
ARM
+
RP1 0/R1608
PVDD_ARM
CMPSH-3
Q1B
330uF/16V/T6032
4 R39
1/R1005
VOSENSE VRNG
23 13
FDS6982
OPVIN OP-
15 16
CT3
+ 4.7uF/6.3V/T3216
LTC3714EG C
VDD_D
5
nARM_REG_LE "Output H : Data Change"
12
C7 100pF
C8 100pF
20K/R1005
2
[4,16] Xhi_A8/CE_CF0 C
21
7 8 9 24 25
0/R1005
[2,3,14,16] XnRESET
ION
1
LE OE
RUN/SS
6
11 1
19 18 17 16 15 14 13 12
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
100uF/16V/T6032
5
20 D1 D2 D3 D4 D5 D6 D7 D8
VDD_D
2 3 4 5 6 7 8 9
XEINT11 XEINT12 XEINT13 XEINT14 XEINT15
C4 100nF
10
U8
GND
[3,16] [3,13,16] [3,13,16] [3,16] [3,16]
+
U7
VDD_ARM_VID1 VDD_ARM_VID2
VDD_D
10/R1005
3
D
R31
8
VDD_D
U10
1 4 2
CORE_REG_OE
SN74LVC1G00DBV R42
3
CORE_REG_OE "Output H : Latch Output Enable"
VDD_D 10K/R1005
U9B 8
C_PWR_5V
SN74LVC2G08DCTR
5
VDD_D
3
VDD_D
6
[4,16] Xhi_A10/IORD_CF
CT4
VDD_ARM_VID1 VDD_ARM_VID2 VDD_INT_VID CORE_REG_OE
11 1
LE OE
VDD_D
20 [4,16] Xhi_A9/CE_CF1
8 7 6 5
D1 D2 D3 D4 D5 D6 D7 D8
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
19 18 17 16 15 14 13 12
SN74LVC573APW
R60 C14 100pF
R63 100K/R1005 C15 500pF
A
[1] [2]
ON (1) VDD_ARM [2][1]
R51 6.8nF
8
R49
C12
20K/R1005
CFG1
R48
R58 100K/R1005
KHS04 R61 100K/R1005
B
10
RUN/SS
ION
21
12
PGDOD
VIN
27
TG
5
2
SW
4
FDS6982
BOOST
6
7 8 9 24 25
GND
R62 100K/R1005
CFG1 1 2 3 4
2 3 4 5 6 7 8 9
10
XEINT11 XEINT12 XEINT13 XEINT14 XEINT15
R57
R56
[3,16] [3,13,16] [3,13,16] [3,16] [3,16]
10K/R1005
10K/R1005
10K/R1005
R55
VDD_D
U12
100uF/16V/T6032 7
0/R1005
C10 100nF
VID0 VID1 VID2 VID3 VID4
11
VON
14
ITH
20 22 19
SGND
18 17
OPOUT OP+
C11
INTVCC EXTVCC
28 26
JP2
330pF
2
3
FCB
BG
1
VFB
PGND
2
CT5
1
3
VDD_INT
A2-2PA-2.54DSA L2 2.2uH (LQH32CN2R2M33)
D2
SENSE
C13 100pF
Q2A 1
R54 VDD_D
R50 330K/R1005
U11
6
NC/R1005
+
5
B
R53
10/R1005
1
INT
+
RP2 0/R1608
PVDD_INT
CMPSH-3
Q2B
330uF/16V/T6032
4 R59
1/R1005
FDS6982 3
VDD_INT_VID
100K/R1005
NC/R1005
R45
XPWRRGTON_SW [7]
100K/R1005
R52
R47
10K/R1005
100K/R1005
R44 0/R1005
NC/R1005
R46
4
R43
100K/R1005
INT_REG_LE
VOSENSE VRNG
23 13
OPVIN OP-
15 16
CT6
+ 4.7uF/6.3V/T3216
LTC3714EG
A
OFF (0) 11=1.0V 01=1.2V
10=1.1V 00=1.3V
SAMSUNG ELECTRONICS CO.,LTD Title SMDK6410 CPU Board (S3C6410 Evaluation Board)
[3]
VDD_INT 1.0V
VDD_INT 1.2V
[4]
PWRControl Enable
PWRControl Disable
Size A3 Date:
5
4
3
2
Document Number Power (ARM, INT) Wednesday, June 18, 2008
Rev 0.2 Sheet 1
6
of
16
5
4
Vout=0.8(1+R1/R2) R1=R2(Vout/0.8V-1)
[6] XPWRRGTON_SW
SHDN
VDD_D 1 2 D
CT7
IN0 IN1
+
10uF/6.3V/T2012
POK OUT1 OUT0
3 8 7
JP3
SET
6
GND
5
(1.2V) 100K/R1005
R64
VDD_APLL
RP3 0/R1608
R65 15K/R1005
PVDD_PLL
R66
R1 A2-2PA-2.54DSA
MAX1806EUA15
+
R70 169K,1%/R1005
R2
33/R1005
VBUS DD+ GND
CON3 [3,9] [3] [3] [3]
USB(HOST) SOCKET
MPLL
C16
VBUS DD+ ID GND
D
+
15K/R1005
USB-MINIAB
DN and DP should be routed evenly
1
1 2 3 4 5
XVBUS XotgDM XotgDP XotgID
USB DUAL Port - A Type (Host) VDD_MPLL
2
10uF/6.3V/T2012
1 2 3 4
R69 R67
JP4
CT8
CON2A
33/R1005
[3] XusbhDN [3] XusbhDP
84.5K,1%/R1005
1
C_PWR_5V
1
APLL R68
2
A2-2PA-2.54DSA
2
U13 4
3
CT9 100nF
RP4 0/R1608
10uF/6.3V/T2012 A2-2PA-2.54DSA
JP5
VDD_EPLL
2
R71 15K/R1005
1
EPLL
RP5 0/R1608
C_PWR_5V
C_PWR_5V
U14
CON2B 5 6 7 8
USBH_DTP10 R74 USBH_D+ TP11
VBUS DD+ GND
USB(HOST) SOCKET
[3] XotgDRV_VBUS
R72
0/R1005
R73
110K/R1005 2
USB DUAL Port - A Type (Host) C19
15K/R1005
1
nSKIP
OUT
8
nSHDN
CXP
7
CXN
6
PGND
5
3
IN
4
GND
XVBUS [3,9] C17
C18
0.47uF
2.2uF
MAX682ESA 1uF
Vout=0.8(1+R1/R2) R1=R2(Vout/0.8V-1)
SHDN
1 2
IN0 IN1
+
CT10
R76
3 8 7
POK OUT1 OUT0 SET
6
GND
5
A2-2PA-2.54DSA R77
(1.2V)
R1 84.5K,1%/R1005
MAX1806EUA15
10uF/6.3V/T2012
100K/R1005
R78 169K,1%/R1005
R2
JP6 2
+
Alive
RP6 0/R1608
1
[8,15] REG_EN CT13
RUN
SW VFB
10uF/6.3V/T2012
1
PVDD_ALIVE
L3 2.2uH (LQH32CN2R2M33) 3 5
1M,1%/R1005
C22
22pF
VDD_RTC 1
+
R2 R1
(2.5V) JP7 2
R79
VDD OE
OUT
3
GND
2
R75
XotgTO [3]
X1
44.2 ohm,1%/R1005
R946 NC (1M)/R1005
48MHz (SMD,SCO-103)
A2-2PA-2.54DSA
+ LTC3406ES5 2
B
VIN
4
10uF/6.3V/T2012
U16 GND
4
XotgTI [3] [3] XREXT
OSC1
Vout=0.6(1+R2/R1) R2=R1(Vout/0.6V-1) C_PWR_5V
XotgTO TP12
1
CT11
NC (48MHz,CRYSTAL_SX-8)
VDD_D VDD_Alive
2
4 VDD_D
3
[8,15] REG_EN
C
RTC
CT12
RP7 0/R1608
S3C6400 : 3.4K, 1% S3C6410 : 44.2 ohm, 1%
fundermental Oscillator tolerance +-100ppm peak jitter 100ps duty cycle 40/60~60/40 swing 3.3V
1
U15
4
C
XotgTO [3]
For USB Clock
C20
C21
15pF
15pF
PVDD_RTC
B
10uF/6.3V/T2012 R80 316K,1%/R1005
XPWRRGTON_SW [6]
2
1 A1 A2
C1
B1 B2
C_PWR_5V
C2
3
[3,9] XPWRRGTON
CFG5
CFG5
CAS220A1
Use PMIC
4
5
6
R950 100K/R1005
Use Adapter
A
A
VDD_D R952 NC (10K)/R1005
R951 100K/R1005
[8,15] REG_EN
SAMSUNG ELECTRONICS CO.,LTD Title SMDK6410 CPU Board (S3C6410 Evaluation Board) Size A3 Date:
5
4
3
2
Document Number Power (PLL, Alive, RTC)/USB Host/USB OTG Wednesday, June 18, 2008
Sheet 1
Rev 0.2 7
of
16
5
4
3
2
1
A2-2PA-2.54DSA
SYS VDD_PCM
PVDD_AUDIO
RP10 A2-2PA-2.54DSA
Vout=0.6(1+R2/R1) R2=R1(Vout/0.6V-1)
0/R1608
C_PWR_5V VDD_ADC
RP12
ADC A2-2PA-2.54DSA JP14
[7,15] REG_EN
VDD_DAC
4
VIN
1
RUN
+
1
SW
3
VFB
5
2
0/R1608
CT14 10uF/6.3V/T2012
DAC
R84 80K,1%/R1005
2
VDD_UH
UH
RP16 A2-2PA-2.54DSA
JP18 2
MMC
2
LED2
2
LED-Red (SMD 3216)
CORE
1 RP15
0/R1608
SMEM
[6] CORE_PWR_OK
R85
Q3
1
MMBT3904LT1
1K/R1005
A2-2PA-2.54DSA
VDD_SS
JP17
PVDD_SS
1 RP17
0/R1608
VDD_EXT
[3,13,16] XPWM_ECLK
VDD_D
PVDD_UH_MMC
[4,12,16] XhiINTR [3,16] XEINT7/KP_ROW7
PVDD_EXT RP19
R86
0/R1005
R87 R88
NC/R1005 NC/R1005
C
USB20_EN
NC/R1608
0/R1608
PVDD_AUDIO
A2-2PA-2.54DSA VDD_LCD 1 RP22
LCD
0/R1608
0/R1608
RP20
RP13
2
1
JP20
3.3V
1
VR1
A2-2PA-2.54DSA
EXT
SS
JP19
PVDD_LCD
RP21
NC/R1608
0/R1608
VDD_D
VDD_D
R89 10K/R1005
VDD_HI
1 2 3
A2-3PA-2.54DSA
33uF/6.3V/T3528
0/R1608
RP18
2
JP22
100nF
1
B
+
VDD_MMC
C
3
D
LED1
DMEM A2-2PA-2.54DSA JP15 VDD_SMEM
500K
R1
PVDD_UH_MMC
1
CT15 C23
1
A2-2PA-2.54DSA
JP16
500K,1%/R1005
R82 510/R1005
LED-Red (SMD 3216)
VDD_DMEM
R2
0/R1608
A2-2PA-2.54DSA
JP13
R83
LTC3406ES5 RP14
RP11
C_PWR_5V
R81 510/R1005
1
MEM1
L4 2.2uH (LQH32CN2R2M33)
2
2
0/R1608
2
VDD_1.8V
U17
1
GND
PCM JP12
VDD_D
0/R1608
3
1
D
2
RP9
MEM0 A2-2PA-2.54DSA JP11 VDD_MEM1
2
JP10
PVDD_MEM
1
A2-2PA-2.54DSA
2
VDD_MEM0
JP9 2
1
A2-2PA-2.54DSA
PVDD_SYS
0/R1608
2
RP8
2
VDD_SYS 1
1
JP8 2
2
VDD_D
Vout=0.8(1+R1/R2) R1=R2(Vout/0.8V-1)
PVDD_HI RP24
0/R1608
B
U18 4
VDD_1.8V
SHDN
C_PWR_5V CT16 10uF/6.3V/T2012
Added on 04/30/2008
1 2
+
SET
6
R91
GND
5
R2
100K,1%/R1005 A2-2PA-2.54DSA
(1.2V)
R1 84.5K,1%/R1005
+
VDD_OTGI
JP21 2
GND
GND
GND
MTH1
MTH2
MTH3
MTH4
PVDD_OTGI
1 RP23
GND
0/R1608
OTGI
R92 169K,1%/R1005
CT17 10uF/6.3V/T2012
U39
5
R953 0/R1005
R90
MAX1806EUA15
VDD_D
R968 10K/R1005
IN0 IN1
3 8 7
POK OUT1 OUT0
1
USB20_EN
4 2 R954 0/R1005
Vout=0.8(1+R1/R2) R1=R2(Vout/0.8V-1)
SN74AUC1G08DBV 3
[7,15] REG_EN
GND
GND
GND
GND
GND
GND
TPH1
TPH2
TPH3
TPH4
TPH5
TPH6
U19 4
A
C_PWR_5V 1 2 CT18 10uF/6.3V/T2012
+
SHDN IN0 IN1
POK OUT1 OUT0
3 8 7
R93
SET
6
R94
GND MAX1806EUA33
5
R2
100K,1%/R1005 A2-2PA-2.54DSA
(3.3V)
R1
75K,1%/R1005 R95 24.3K,1%/R1005
+
JP23 2
A
VDD_OTG PVDD_OTG
1 RP25
0/R1608
SAMSUNG ELECTRONICS CO.,LTD
OTG
Title
CT19 10uF/6.3V/T2012
SMDK6410 CPU Board (S3C6410 Evaluation Board) Size A3 Date:
5
4
3
2
Document Number Power (I/O) Wednesday, June 18, 2008
Rev 0.2 Sheet 1
8
of
16
2
1
ZD1
JACK1
Onsemi 1SMB5920BT3G (6.2V)
DC_5V
OFF
DC 5V,3A
D
PVDD_RTC
TP15 TP14 TP16
TP17
PWR ON
D
Battery Connector RP31 0/R1608
PVDD_MEM
PVCCAUX1
BUCK2_VDDINT BUCK2_VDDINT
E5 E6 E7 F5 F6 F7
BUCK3_VDDMEM0/VDDMEM1 BUCK3_VDDMEM0/VDDMEM1 BUCK3_VDDMEM0/VDDMEM1 BUCK3_VDDMEM0/VDDMEM1 BUCK3_VDDMEM0/VDDMEM1 BUCK3_VDDMEM0/VDDMEM1
E19 F19
PVDD_PLL
F4 G4
PVDD_HI
E17 F17
PVCCAUX3 PVDD_UH_MMC PVCCAUX2 B
PVDD_EXT
VLDO5_VDDUH/VDDMMC VLDO5_VDDUH/VDDMMC
H6 J6
VLDO6_VCCAUX2 VLDO6_VCCAUX2
F2 G2 G8
TP38
PVDD_OTGI PVDD_SYS PVCCM2MTV
VLDO9_VDDOTGI VLDO9_VDDOTGI VLDO10_VDDSYS VLDO10_VDDSYS
F3 G3
PVDD_OTG
H17 J17
PVDD_ALIVE
H2 J2
PVDD_AUDIO
J5 H4 H5
TP44
1
2
B1
J16 J4 H16 G7 E18 C2
0/R1005 0/R1005 0/R1005 0/R1005 0/R1005
PCM_CLK PCM_FSYNC PCM_SDI PCM_SDO
C10 C9 C8 C7
R103 R104 R105 R106
0/R1005 0/R1005 0/R1005 0/R1005
A2
CFG2
5268-02A
CAS220A1
4
C2
B2 6
5
Reserved Reserved Reserved Reserved Reserved Reserved
C3 C4 C5 C6 ADC_IN4 ADC_IN5 ADC_IN6 ADC_IN7
F11 F12 E11 E12
G19 VVIB
TSI_XM TSI_XP TSI_YM TSI_YP
H8 J8 G14 G15 H19 J19 MIC1_N MIC1_P MIC2_N MIC2_P MIC_BIAS_INT MIC_BIAS_EXT
G16 G17 G18
G12 G13 D12 LED_DRV1 LED_DRV2 FLASH_EN
H12 J12
E9 E10 D9 D10 D2 VCHGR VCHGR VCHGR VCHGR TBAT
WLED_BOOST WLED_OUT1 WLED_OUT2
R98 R99 R100 R101 R102
2 RP33 NC/R1608
+
0/R1608
XVBUS [3,7]
XPCM_EXTCLK1/I2S_CDCLK1/AC97_RSTn0 [3,16] XPCM_EXTCLK0/I2S_CDCLK0/AC97_RSTn0/ADDR_CF1 [3,16] XPCM_DCLK0/I2S_CLK0/AC97_BITCLK0/ADDR_CF0 [3,16] XPCM_FSYNC0/I2S_LRCLK0/AC97_SYNC0/ADDR_CF2 [3,16] XPCM_SIN0/I2S_DI0/AC97_SDI0 [3,16] XPCM_SOUT0/I2S_DO0/AC97_SDO0 [3,16]
C
XPCM_DCLK1/I2S_CLK1/AC97_BITCLK0 [3,16] XPCM_FSYNC1/I2S_LRCLK1/AC97_SYNC0 [3,16] XPCM_SIN1/I2S_DI1/AC97_SDI0 [3,16] XPCM_SOUT1/I2S_DO1/AC97_SDO0 [3,16]
B8 B9
Xi2cSCL0 [3,15,16] Xi2cSDA0 [3,15,16]
PWR_I2C_SCL PWR_I2C_SDA
D11 C11
TP29 TP30
nVDD_FAULT nBATT_FAULT SYS_EN PWR_EN nPMIC_IRQ nSLEEP EXT_WAKEUP1 EXT_WAKEUP0 nONKEY nEXTON nRST_IN REM_IN nRST_OUT
B15 B13 B12 B11 B10 B5 B4 B3 B2 D19 D7 D6 D5
TP31 XnBATF [2,3] TP32 XPWRRGTON [3,7] PMIC_XEINT12_IRQn [3] TP33 TP34 TP35 PMIC_ONKEYn [2] TP36 R969
VMID AUD_AMP_EN AUDIO_LINEOUT STEREO_CH2 STEREO_CH1 BEAR_SPK_N BEAR_SPK_P MONO_SPK_N MONO_SPK_P AUD_AUX3_IN AUD_AUX2_IN AUD_AUX1_IN
C17 D8 C19 C18 C16 C15 C14 C13 C12 B19 B18 B17
PMIC_STEREO_VMID [16] TP37 PMIC_MODEM_MIC_P [16] PMIC_STEREO_CH2 [16] PMIC_STEREO_CH1 [16] PMIC_BEAR_SPK_N [16] PMIC_BEAR_SPK_P [16] PMIC_MONO_SPK_N [16] PMIC_MONO_SPK_P [16] TP39 PMIC_MODEM_SPK_N [16] PMIC_MODEM_SPK_P [16]
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
B16 B14 B7 B6 D4 D3 D15 D14 D13
GND GND GND GND
J20 J1 H20 H1
Added on 04/30/2008 0/R1608
nRESET [2]
PMIC_REM_IN [16] PMIC_nRST_OUT [2] B
Changed on 04/30/2008
VLDO11_VCCM2MTV VLDO11_VCCM2MTV VLDO12_VDDLCD VLDO12_VDDLCD VLDO13_VDDGPS/VCCM1GPS VLDO13_VDDGPS/VCCM1GPS VLDO14_VDDOTG VLDO14_VDDOTG VLDO15_VDDALIVE VLDO15_VDDALIVE VLDO_AUDIO_VDDPCM/VDDADC/VDDDAC VLDO_ADC(Reserved) VBUS_XVBUS
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 C1 C20 D1 D20 G1 G20
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
[3,7] XVBUS
SEAM-20-02.0-SM-10-2-A
VLDO8_VCCM3BT VLDO8_VCCM3BT LDO8_EN(Reserved)
H18 J18
H15 J15
PVDD_SS
CON5
VLDO7_VDDEXT VLDO7_VDDEXT
H13 J13
H3 J3
PVDD_LCD
VLDO3_VDDHI VLDO3_VDDHI
E3 E4
D18 D16 D17 F8 E8
I2C_SCL I2C_SDA
VLDO2_VDDMPLL/VDDAPLL/VDDEPLL VLDO2_VDDMPLL/VDDAPLL/VDDEPLL
VLDO4_VCCAUX3 VLDO4_VCCAUX3
I2S_CDCLK I2S_BITCLK I2S_SYNC I2S_DATAOUT I2S_DATAIN
MCLK
VLDO1_VCCAUX1 VLDO1_VCCAUX1
H7 J7
H14 J14
PVCCM3BT
H9 H10 H11 J9 J10 J11 G9 G10 G11
G5 G6
0/R1005
RP32 0/R1608
RP27
VCHGR R97
1
A1
3
PVDD_INT
0/R1608
E2
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
C
RP26
SW5
CFG2
Power Off
X
CON3 (USB OTG) X
Operation & Charging by DC
O
X
O
Charging by USB
X
O
O
TP40 TP41 TP42 TP43
JACK1 (DC)
CON4 (Battery) X
A
X : Don't care
O : Insertion (Placement) SAMSUNG ELECTRONICS CO.,LTD
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 E1 E16 E20 F1 F9 F10 F16 F20 B1 B20
PVDD_ARM
BUCK1_VDDARM BUCK1_VDDARM BUCK1_VDDARM BUCK1_VDDARM BUCK1_VDDARM BUCK1_VDDARM
VRTC_VDDRTC VRTC_VDDRTC
LED_PC E13 E14 E15 F13 F14 F15
VBAT_IN VBAT_IN VBAT_IN VBAT_IN VBAT_IN VBAT_IN VBAT_IN VBAT_IN VBAT_IN
F18
2 1K/R1005
C1
LED-Red (SMD 3216)
CON4
RP30 NC/R1608
DC_5V
R96
A
NC/R1608
RP29 0/R1608
LED3
PMIC
RP28
CAS220A1
VBAT C_PWR_5V
1
VCHGR TP13
6
VBAT
TP28 TP27 TP19 TP21TP23 TP25 TP18 TP20 TP22TP24 TP26
1
3
POWER JACK (DC-JACK, DC-003)
2
SW5
B2
[16] WLED_OUT1 [16] WHITE_LED
[16] [16] [16] [16]
1
PMIC_MIC1_N PMIC_MIC1_P PMIC_MIC2_N PMIC_MIC2_P
F1 (1.5A, SMD, Poly Switch) MicroSMD150-2
B1
Changed on 04/30/2008
A1
2 3
2
A2
G G
1
4
1
2
P
C1
3
C2
4
5
5
Title SMDK6410 CPU Board (S3C6410 Evaluation Board) Size A3 Date:
5
4
3
2
Document Number PMIC Socket Wednesday, June 18, 2008
Rev 0.2 Sheet 1
9
of
16
5
4
U20
[2] Xm1ADDR[15:0] Xm1ADDR0 Xm1ADDR1 Xm1ADDR2 Xm1ADDR3 Xm1ADDR4 Xm1ADDR5 Xm1ADDR6 Xm1ADDR7 Xm1ADDR8 Xm1ADDR9 Xm1ADDR10 Xm1ADDR11 Xm1ADDR12
J8 J9 K7 K8 K2 K3 J1 J2 J3 H1 J7 H2 H3
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12
H8 H9
BA0 BA1
Xm1DQM0 Xm1DQM1 Xm1DQS0 Xm1DQS1
F8 F2 E8 E2
LDM UDM LDQS UDQS
[2] Xm1CKE0 [2] Xm1SCLK [2] Xm1SCLKn
G1 G2 G3
D
[2] Xm1ADDR14 [2] Xm1ADDR15
!!SAME ROUTE LENGTH VDD_DMEM
CTB28
3
[2] [2] [2] [2]
CB57 CB58 CB59 CB60 CB61 CB62
+ C
100nF 100nF 100nF 100nF 100nF 100nF 10uF/6.3V/T2012
1
Xm1DATA[31:0] [2] DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
A8 B7 B8 C7 C8 D7 D8 E7 E3 D2 D3 C2 C3 B2 B3 A2
nCS nRAS nCAS nWE
H7 G9 G8 G7
CKE CK nCK
NC NC
F3 F7
A9 F9 K9
VDD VDD VDD
VSS VSS VSS
A1 F1 K1
C9 E9 A7 B1 D1
VDDQ VDDQ VDDQ VDDQ VDDQ
VSSQ VSSQ VSSQ VSSQ VSSQ
C1 E1 A3 B9 D9
Changed on 04/30/2008
2
Xm1DATA0 Xm1DATA1 Xm1DATA2 Xm1DATA3 Xm1DATA4 Xm1DATA5 Xm1DATA6 Xm1DATA7 Xm1DATA8 Xm1DATA9 Xm1DATA10 Xm1DATA11 Xm1DATA12 Xm1DATA13 Xm1DATA14 Xm1DATA15
D
* Note: U21 not available on 06/18/2008 Xm1CSn0 [2] Xm1RASn [2] Xm1CASn [2] Xm1WEn [2]
C
K4X51163PE-L(F)E/GC6
Just Only PADS on Lines U22
[2] Xm1ADDR[15:0] Xm1ADDR0 Xm1ADDR1 Xm1ADDR2 Xm1ADDR3 Xm1ADDR4 Xm1ADDR5 Xm1ADDR6 Xm1ADDR7 Xm1ADDR8 Xm1ADDR9 Xm1ADDR10 Xm1ADDR11 Xm1ADDR12
B
[2] Xm1ADDR14 [2] Xm1ADDR15
!!SAME ROUTE LENGTH VDD_DMEM
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12
H8 H9
BA0 BA1
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
A8 B7 B8 C7 C8 D7 D8 E7 E3 D2 D3 C2 C3 B2 B3 A2
Xm1DATA16 Xm1DATA17 Xm1DATA18 Xm1DATA19 Xm1DATA20 Xm1DATA21 Xm1DATA22 Xm1DATA23 Xm1DATA24 Xm1DATA25 Xm1DATA26 Xm1DATA27 Xm1DATA28 Xm1DATA29 Xm1DATA30 Xm1DATA31
[2] Xm1ADDR0
TP45
M1A0
[2,11] Xm0ADDR0
TP46
M0A0
[2] Xm1DATA0
TP47
M1D0
[2,11,14] Xm0DATA0
TP48
M0D0
[2] Xm1CKE0
TP49
M1CKE0
[2] Xm0CKE
TP50
M0CKE0
[2] Xm1CKE1
TP51
M1CKE1
[2] Xm0SCLK
TP52
M0SCLK
[2] Xm1SCLK
TP53
M1SCLK
[2] Xm0SCLKn
TP54
M0SCLKn
[2] Xm1SCLKn
TP55
M1SCLKn
[2] Xm0WEndmc
TP56
M0WEn
[2] Xm1WEn
TP57
M1WEn
[2] Xm0CASn
TP58
M0CASn
[2] Xm1CASn
TP59
M1CASn
[2] Xm0RASn
TP60
M0RASn
[2] Xm1RASn
TP61
M1RASn
[2,11] Xm0DQM0/BE0
TP62
M0DQM0
[2] Xm1DQM0
TP63
M1DQM0
[2,11] Xm0DQM1/BE1
TP64
M0DQM1
[2] Xm1DQM1
TP65
M1DQM1
[2] Xm0DQS0
TP66
M0DQS0
[2] Xm1DQM2
TP67
M1DQM2
[2] Xm0DQS1
TP68
M0DQS1
[2] Xm1DQM3
TP69
M1DQM3
[2] Xm0AP
TP70
M0AP
[2] Xm1DQS0
TP71
M1DQS0
[2,12] Xm0CSn7
TP72
M0CSn7
TP74
Xm0A10
Xm1DQM2 Xm1DQM3 Xm1DQS2 Xm1DQS3
F8 F2 E8 E2
LDM UDM LDQS UDQS
[2] Xm1CKE0 [2] Xm1SCLK [2] Xm1SCLKn
G1 G2 G3
CKE CK nCK
NC NC
F3 F7
A9 F9 K9
VDD VDD VDD
VSS VSS VSS
A1 F1 K1
[2] Xm1DQS1
TP73
M1DQS1
[2] Xm1DQS2
TP75
M1DQS2
C9 E9 A7 B1 D1
VDDQ VDDQ VDDQ VDDQ VDDQ
VSSQ VSSQ VSSQ VSSQ VSSQ
C1 E1 A3 B9 D9
[2] Xm1DQS3
TP76
M1DQS3
[2] Xm1CSn1
TP77
M1CSn1
TP79
Xm1A13
[2] [2] [2] [2]
CTB30 CB69 CB70 CB71 CB72 CB73 CB74 A
J8 J9 K7 K8 K2 K3 J1 J2 J3 H1 J7 H2 H3
Xm1DATA[31:0] [2]
+
nCS nRAS nCAS nWE
H7 G9 G8 G7
Xm1CSn0 [2] Xm1RASn [2] Xm1CASn [2] Xm1WEn [2]
[2,11] Xm0ADDR10
B
A
100nF 100nF 100nF 100nF 100nF 100nF 10uF/6.3V/T2012
Changed on 04/30/2008
[2] Xm1ADDR13
[2] Xm1CSn0
TP78
Xm1CSn0
SAMSUNG ELECTRONICS CO.,LTD Title SMDK6410 CPU Board (S3C6410 Evaluation Board)
K4X51163PE-L(F)E/GC6 Size A3 Date:
5
4
3
2
Document Number Memory (mDDR) Wednesday, June 18, 2008
Rev 0.2 Sheet 1
10
of
16
5
VDD_D
4
3
2
1
VDD_BUF A2-2PA-2.54DSA
VDD_BUF
VDD_SMEM
JP24 2
1
VDD_BUF
VDD_SMEM
U23
BUF
CB75
100nF
42 31
VCCA0 VCCA1
CB77
100nF
D
42 31
VCCA0 VCCA1
VCCB0 VCCB1
CB78
7 18
[2,10] Xm0ADDR[15:0]
100nF
[2,12] Xm0CSn0 [2,12] Xm0CSn1 [12,14] M0CSn2 [12,14] M0CSn3 [2,12] Xm0CSn4 [2,12] Xm0CSn5 [2,10] Xm0DQM0/BE0 [2,10] Xm0DQM1/BE1
B_ADDR[15:0] [16]
47 46 44 43 41 40 38 37
Xm0ADDR0 Xm0ADDR1 Xm0ADDR2 Xm0ADDR3 Xm0ADDR4 Xm0ADDR5 Xm0ADDR6 Xm0ADDR7
47 46 44 43 41 40 38 37
1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8
1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8
2 3 5 6 8 9 11 12
B_ADDR0 B_ADDR1 B_ADDR2 B_ADDR3 B_ADDR4 B_ADDR5 B_ADDR6 B_ADDR7
Xm0ADDR8 Xm0ADDR9 Xm0ADDR10 Xm0ADDR11 Xm0ADDR12 Xm0ADDR13 Xm0ADDR14 Xm0ADDR15
36 35 33 32 30 29 27 26
2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8
2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8
13 14 16 17 19 20 22 23
B_ADDR8 B_ADDR9 B_ADDR10 B_ADDR11 B_ADDR12 B_ADDR13 B_ADDR14 B_ADDR15
48 25
1OE 2OE
1DIR 2DIR
1 24
R108
DIR L : B->A DIR H : A->B
[2,12,14] Xm0INTsm1/FREn [2,14] Xm0INTsm0/FWEn [2,14] Xm0RDY0/ALE [2,14] Xm0RDY1/CLE [12] Xm0OEata [12] Xm0WEata [12] Xm0RSTata [12] Xm0REGata
VDD_SMEM
sn74AVCA164245 (A(1.8V) B(3.3V)) A->B 1.6nS ~ 4.3nS B->A 1.8nS ~ 5.5nS
100K/R1005
Propagation Delay A->B 1.6nS ~ 4.3nS B->A 1.8nS ~ 5.5nS
45 39 34 28
C
GND0 GND1 GND2 GND3
GND7 GND6 GND5 GND4
4 10 15 21
CB76
100nF
VCCB0 VCCB1
7 18
1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8
1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8
2 3 5 6 8 9 11 12
B_CSn_0 [16] B_CSn_1 [16] B_CSn_2 [16] B_CSn_3 [16] B_CSn_4 [16] B_CSn_5 [16] B_nBE0 [16] B_nBE1 [16]
36 35 33 32 30 29 27 26
2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8
2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8
13 14 16 17 19 20 22 23
B_FREn [16] B_FWEn [16] B_ALE [16] B_CLE [16] B_OEata [16] B_WEata [16] B_RESET [16] B_REGata [16]
48 25
1OE 2OE
1DIR 2DIR
1 24
45 39 34 28
GND0 GND1 GND2 GND3
GND7 GND6 GND5 GND4
4 10 15 21
U24
D
VDD_SMEM
R107 100K/R1005
SN74AVCA164245DGG C
SN74AVCA164245DGG
VDD_BUF
VDD_SMEM
U25 CB79
100nF
42 31
VCCA0 VCCA1
Xm0DATA0 Xm0DATA1 Xm0DATA2 Xm0DATA3 Xm0DATA4 Xm0DATA5 Xm0DATA6 Xm0DATA7
47 46 44 43 41 40 38 37
Xm0DATA8 Xm0DATA9 Xm0DATA10 Xm0DATA11 Xm0DATA12 Xm0DATA13 Xm0DATA14 Xm0DATA15
CB80
VCCB0 VCCB1
7 18
1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8
1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8
2 3 5 6 8 9 11 12
B_DATA0 B_DATA1 B_DATA2 B_DATA3 B_DATA4 B_DATA5 B_DATA6 B_DATA7
36 35 33 32 30 29 27 26
2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8
2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8
13 14 16 17 19 20 22 23
B_DATA8 B_DATA9 B_DATA10 B_DATA11 B_DATA12 B_DATA13 B_DATA14 B_DATA15
48 25
1OE 2OE
1DIR 2DIR
1 24
45 39 34 28
GND0 GND1 GND2 GND3
GND7 GND6 GND5 GND4
4 10 15 21
100nF
[2,10,14] Xm0DATA[15:0]
VDD_BUF
VDD_SMEM
B_DATA[15:0] [16]
VDD_BUF
CB81 CB82 100nF
U26 100nF
42 31
VCCA0 VCCA1
VCCB0 VCCB1
7 18
47 46 44 43 41 40 38 37
1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8
1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8
2 3 5 6 8 9 11 12
36 35 33 32 30 29 27 26
2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8
2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8
13 14 16 17 19 20 22 23
48 25
1OE 2OE
1DIR 2DIR
1 24
45 39 34 28
GND0 GND1 GND2 GND3
GND7 GND6 GND5 GND4
4 10 15 21
R109
R110 4.7K/R1005
4.7K/R1005
B
[12] Xm0INTata [12] Xm0INPACKata [14] RnB [12] Xm0CData [2] Xm0WAITn/IORDY TP80 TP82 [2] [2] [2] [2]
Xm0ADDR16 Xm0ADDR17 Xm0ADDR18 Xm0ADDR19
[2,14] Xm0WEn/nIOWR_CF [2,12,14] Xm0OEn/nIORD_CF
B_INTata [16] B_INPACKata [16] B_RnB [16] B_CData [16] B_WAITn/IORDY [16] TP81 TP83 B_ADDR16 B_ADDR17 B_ADDR18 B_ADDR19
[16] [16] [16] [16]
B_WEn/nIOWR_CF [16] B_OEn/nIORD_CF [16]
VDD_SMEM R111 R112
0/R1005
B
BUF_DIR [12]
SN74AVCA164245DGG
100K/R1005
VDD_SMEM
VDD_SMEM 8
R113
SN74AVCA164245DGG
[12] BCtrl_I0
1
[12] BCtrl_I1
2
U27A
100K/R1005
7
3
R114
6
SN74AUC2G08DCT 4
A
U27B
5
A
NC/R1005
SN74AUC2G08DCT
[3,16] XuRXD_3/ExdREQ/IrRXD/ADDR_CF2/Xi2cSCL1
SAMSUNG ELECTRONICS CO.,LTD Title SMDK6410 CPU Board (S3C6410 Evaluation Board) Size A3 Date: 5
4
3
2
Document Number Buffers (SROM IF) Wednesday, June 18, 2008
Rev 0.2 Sheet 1
11
of
16
5
4
3
2
1
CON14 SN74AUC2G08 Propagation Delay (CL30pF) Typ: 1.5nS ( 1.2 ~ 2.1)
VDD_SMEM
VDD_SMEM R115
100K/R1005
R117
100K/R1005
D
1
[2,11,14] Xm0INTsm1/FREn
2
7
R118 7
2 SN74AUC2G08DCT
VDD_SMEM
[2,11] Xm0CSn5
1
[2,11] Xm0CSn4
2
0/R1005 SN74AUC2G08DCT
R127 0/R1005
U28B 5
MP0_DOEn
6
[3,15,16] XIrSDBW
3 R129 NC/R1005
SN74AUC2G08DCT
[4,8,16] XhiINTR
R125
NC/R1005
R128
NC/R1005
3
R119
100K/R1005
R123
100K/R1005
BCtrl_I1 [11]
6 SN74AUC2G08DCT
U31B
5
[2] Xm0REGata/SS_GPO0 R126 0/R1005
3 6
U29B
R1300/R1005
5
SN74AUC2G08DCT
VDD_SMEM
R122 4.7K/R1005
nOE_CF
U30B
7
BUF_DIR [11]
4 R121 NC/R1005
U30A
8
100K/R1005
U29A
1
4
[2,11,14] Xm0OEn/nIORD_CF
U28A
8
8
R116
SN74AUC2G08DCT
5 3 6 R131 0/R1005
SN74AUC2G08DCT C
VDD_SMEM SN74AUC2G08 Propagation Delay (CL30pF) Typ: 1.5nS ( 1.2 ~ 2.1)
R132
8
0/R1005
nOE
2
A
3
SN74AUC2G08DCT 100K/R1005
VDD_SMEM
R124
100K/R1005
[11,14] M0CSn2
5
[11,14] M0CSn3
6
8
R120
U32B
1
3
2
VCC
5
Y
4
R133 100K/R1005
GND
2
VDD_SMEM
C_PWR_5V
R135
[3,15,16] XIrSDBW
7
[2,11] Xm0CSn1
SS_TCXO_CLK
U31A
U33 1
MP0_DOEn
SN74AUC1G125DBV
U32A 7
BCtrl_I0 [11]
SN74AUC2G08DCT
B
4
SS_GPO0 SS_GPO1 SS_GPO3 SS_REAL_IN SS_GPO2
[2,10] Xm0CSn7
1
[2,11] Xm0CSn0
VDD_SMEM
NC (100K)/R1005
VDD_SMEM
B
GND
VDD_SMEM
VDD_SMEM
4
C
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120
4
D
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119
SN74AUC2G08DCT QSE-060-01-L-D-A
VDD_SMEM
VDD_SMEM
U34 [2] Xm0REGata/SS_GPO0 [2] Xm0WEata/SS_GPO1 [2] Xm0OEata/SS_GPO2 [2] Xm0CData/SS_GPO3 [2] Xm0INTata/SS_REAL_IN [2] Xm0RSTata/SS_IMG_IN [2] Xm0INPACKata/SS_TCXO_CLK
A
R932 R933 R934 R935 R936 R937 R938
0/R1005 0/R1005 0/R1005 0/R1005 0/R1005 0/R1005 0/R1005
R939 R940 R941 R942 R943 R944 R945
0/R1005 0/R1005 0/R1005 0/R1005 0/R1005 0/R1005 0/R1005
1 SS_GPO0 SS_GPO1 SS_GPO2 SS_GPO3 SS_REAL_IN
2 [2] Xm0OEata/SS_GPO2
3
IN
6
GND
VCC
5
NC
COM
4
NO
R134
0/R1005
XhiINTR [4,8,16]
nOE_CF
TS5A3159DBV_SPDT
SS_TCXO_CLK Xm0REGata [11] Xm0WEata [11] Xm0OEata [11] Xm0CData [11] Xm0INTata [11] Xm0RSTata [11] Xm0INPACKata [11]
A
SAMSUNG ELECTRONICS CO.,LTD Title SMDK6410 CPU Board (S3C6410 Evaluation Board) Size A3 Date: 5
4
3
2
Document Number Buffers Control (SROM IF)/GPS Wednesday, June 18, 2008
Rev 0.2 Sheet 1
12
of
16
5
4
3
2
1
VDD_MMCD
DAT3
5 6 7 8 9 10 11 12
DAT4 NC CMD NC DAT5 NC VSS NC
13 14 15
NC VDD NC
[3] XmmcDATA1_0/ADDR_CF2
16 17 18 19 20 21 22 23 24 25
NC CLK NC DAT6 NC VSS NC DAT7 NC DAT0
[3] XmmcDATA1_1
26
DAT1
[3] XmmcCDN0/mmcCDN1
27
SD_CD
28
SD_WP
[3] XmmcCMD1/ADDR_CF1 [3] XmmcDATA1_5/mmcDATA2_1/ADDR_CF1 R152
VDD_MMCD
[3] XmmcCLK1/ADDR_CF0 [3] XmmcDATA1_6/mmcDATA2_2/ADDR_CF2 C
[3] XmmcDATA1_7/mmcDATA2_3
R155
[3,8,16] XPWM_ECLK
SD0_nWP
NC/R1005
VDD_MMCD
JP25
A2-3PA-2.54DSA
MMCD
B_MMC_CMD R153 NC/R1005
PVDD_UH_MMC
VDD_MMCD B_MMC_DATA0
1
29
MMC CD 2
For HS-SPI test
[3] XmmcDATA0_0/ADDR_CF2 [3] XmmcDATA0_1 [3] XmmcDATA0_2 [3] XmmcDATA0_3
CON8 [3] XspiCS0 [3] XspiMISO0/ADDR_CF0 [3] XspiMOSI0/ADDR_CF2 [3] XspiCLK0/ADDR_CF1
1 2 3 4
D1+ D1D2+ D2-
GND
5
GND
6
[3] XmmcCLK0/ADDR_CF0 [3] XmmcCMD0/ADDR_CF1
RA1
R159 R160
0
0/R1005 0/R1005
13 14 15
NC VDD NC
16 17 18 19 20 21 22 23 24 25
NC CLK NC DAT6 NC VSS NC DAT7 NC DAT0
26
DAT1
0/R1005
27
SD_CD
R157
NC/R1005
28
SD_WP
R158
NC/R1005
B_MMC_DATA0 B_MMC_DATA1 B_MMC_DATA2 B_MMC_DATA3
CON9 [3] XspiCS1 [3] XspiMISO1/mmcCMD2 [3] XspiMOSI1 [3] XspiCLK1/mmcCLK2
1 2 3 4
D1+ D1D2+ D2-
GND
5
GND
6
IEEE1394/SD-54030
XspiCS0 XspiMISO0/ADDR_CF0 XspiMOSI0/ADDR_CF2 XspiCLK0/ADDR_CF1
[3] [3] [3] [3]
XspiCS1 XspiMISO1/mmcCMD2 XspiMOSI1 XspiCLK1/mmcCLK2
RA4
NC
RA5
0
R161 R162
NC/R1005 NC/R1005
30
CFG6
IIS 5.1 [ON]
[1]
[ON]
[OFF]
[2]
[ON]
[OFF]
[3]
[ON]
[OFF]
[4]
[ON]
[OFF]
[3] [3] [3] [3]
Channel 0
IIS 5.1[OFF]
CFG6 1 2 3 4
XmmcDATA1_4/mmcDATA2_0/ADDR_CF0 XmmcDATA1_5/mmcDATA2_1/ADDR_CF1 XmmcDATA1_6/mmcDATA2_2/ADDR_CF2 XmmcDATA1_7/mmcDATA2_3
B_MMC_CLK B_MMC_CMD
B
8 7 6 5
B_HSMMC_DAT4/i2sV40_BCLK [16] B_HSMMC_DAT5/i2sV40_CDCLK [16] B_HSMMC_DAT6/i2sV40_LRCLK [16] B_HSMMC_DAT7/i2sV40_DI [16]
KHS04 RA3
NC
RA8
0
R930 R931
0/R1005 0/R1005
B_SPI0_CSn [16] B_SPI0_MISO/ADDR_CF0 [16] B_SPI0_MOSI/ADDR_CF2 [16] B_SPI0_CLK/ADDR_CF1 [16]
B_SPI1_CSn/i2sV40_DO2 [16] B_SPI1_MISO/MMC2_CMD/i2sV40_DO0 [16] B_SPI1_MOSI [16] B_SPI1_CLK/MMC2_CLK/i2sV40_DO1 [16]
C
SD/HSMMC Socket (Taisol 156-1001000901))
IEEE1394/SD-54030 [3] [3] [3] [3]
P30/GND
DAT4 NC CMD NC DAT5 NC VSS NC
LED-Green (SMD 3216)
[3] XmmcCDN0/mmcCDN1
B
[3,6,16] XEINT13
LED4
Channel 1
DAT3
5 6 7 8 9 10 11 12
R156
B_MMC_DATA1 [3] XmmcCDN0/mmcCDN1 [3,6,16] XEINT12
SD/HSMMC Socket (Taisol 156-1001000901))
DAT2
4
VDD_MMCD
B_MMC_CLK
R154 330/R1005
NC NC
3
B_MMC_DATA2 B_MMC_DATA3
1 2 3
1 2
P29/GND
4
P29/GND
[3] XmmcDATA1_2 [3] XmmcDATA1_3 [3] XmmcDATA1_4/mmcDATA2_0/ADDR_CF0
NC/R1005
30
VDD_D
29
DAT2
50K/R1005 50K/R1005 10K/R1005 50K/R1005 50K/R1005
NC NC
3
D
CON7
R147 R148 R149 R150 R151
1 2
SDDATA & CLK path must be same length and route
P30/GND
CON6
R136 R137 R138 R139 R140 R141 R142 R143 R144 R145 R146
D
50K/R1005 50K/R1005 50K/R1005 10K/R1005 50K/R1005 50K/R1005 50K/R1005 50K/R1005 50K/R1005 50K/R1005 50K/R1005
VDD_MMCD
SDDATA & CLK path must be same length and route
[3] XmmcCLK1/ADDR_CF0 [3] XmmcCMD1/ADDR_CF1 [3] XmmcDATA1_0/ADDR_CF2 [3] XmmcDATA1_1
B_MMC_CLK B_MMC_CMD
[3] XmmcDATA1_2 [3] XmmcDATA1_3
B_MMC_DATA0 B_MMC_DATA1 B_MMC_DATA2 B_MMC_DATA3
B_XmmcCLK1/ADDR_CF0 [16] B_XmmcCMD1/ADDR_CF1 [16] B_XmmcDATA1_0/ADDR_CF2 [16] B_XmmcDATA1_1 [16]
B_XmmcDATA1_2 [16] B_XmmcDATA1_3 [16]
A
A
SAMSUNG ELECTRONICS CO.,LTD Title SMDK6410 CPU Board (S3C6410 Evaluation Board) Size A3 Date: 5
4
3
2
Document Number SD_MMC/SPI Wednesday, June 18, 2008
Rev 0.2 Sheet 1
13
of
16
5
4
3
2
1
VDD_D
CON10 4
Xhi_D5/txWAKE/DATA_CF5 [4]
[4] Xhi_D3/rxDATA/DATA_CF3
5
6
Xhi_D7/txDATA/DATA_CF7 [4]
[4] Xhi_D2/rxFLAG/DATA_CF2
7
8
Xhi_D6/txFLAG/DATA_CF6 [4]
[4] Xhi_D0/rxREADY/DATA_CF0
[16] [16] [16] [16]
RA6
Xhi_D1/DATA_CF1 Xhi_D3/DATA_CF3 Xhi_D2/DATA_CF2 Xhi_D0/DATA_CF0
0
9
10
11
12
13
14
15
16
Xhi_D4/txREADY/DATA_CF4
RA7
0
R164
NC/R1005 10K/R1005
[4]
Xhi_D5/DATA_CF5 Xhi_D7/DATA_CF7 Xhi_D6/DATA_CF6 Xhi_D4/DATA_CF4
AXK7L16227G
R163
R165
R166
10K/R1005
10K/R1005
[3] XTRSTn [3] XTDI [3] XTMS [3] XTCK [3] XRTCK [3] XTDO [2,3,6,16] XnRESET
[16] [16] [16] [16]
R167
VDD_D
CON11 1 3 5 7 9 11 13 15 17 19
0/R1005
R169 470/R1005
R171
MIPI Connector
1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20
6 5 4 3 2 1
2
3
2 4 6 8 10 12 14 16 18 20
D
CFG3 KHS06 7 8 9 10 11 12
D
VDD_D
1 [4] Xhi_D1/rxWAKE/DATA_CF1
[3] XOM0 [3] XOM1
HIF3F-20PA-2.54DS (Box,Male,Right Angle)
10K/R1005
[3] XOM2
JTAG
[3] XOM3 [3] XOM4
[3] XSELNAND
VDD_SMEM
VDD_SMEM
CON12
CTB31
CB83
100K/R1005
[2] Xm0CSn3
[2,11] Xm0RDY0/ALE [2,11] Xm0RDY1/CLE
[2,11] Xm0INTsm0/FWEn [2,11,12] Xm0INTsm1/FREn
R178
0/R1005
R179
NC/R1005
R180
0/R1005
R181
0/R1005
R182
NC/R1005
R183
0/R1005
R184
0/R1005
R185
NC/R1005
R186
0/R1005
R176 100K/R1005
M0CSn3 [11,12]
R177
nCS_EXT_ONE nCS_EXT_TWO nCS_EXT_TWO nCS_EXT_ONE [2,11] Xm0WEn/nIOWR_CF [2] Xm0ADV RPn_EXT
RDY_EXT_ONE
[2] Xm0SMCLK [2,10,11] Xm0DATA[15:0]
RDY_EXT_TWO INT_EXT_ONE
Xm0DATA0 Xm0DATA2 Xm0DATA4 Xm0DATA6 Xm0DATA8 Xm0DATA10 Xm0DATA12 Xm0DATA14
INT_EXT_TWO
B
100K/R1005
R172
100K/R1005
R173
100K/R1005
R174
100K/R1005
R175
100K/R1005
CFG3
+ 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
100K/R1005
R170
Changed on 06/18/2008
C
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
R168
Booting Mode
[6]
[5]
[4]
[3]
[2]
NOR/SROM
X
0
1
0
0:8bit 1:16bit
OneNAND
0
0
1
1
0
Modem
X
0
1
1
1
[1]
C
100nF 10uF/6.3V/T2012
Xm0DATA1 Xm0DATA3 Xm0DATA5 Xm0DATA7
INT_EXT_TWO RDY_EXT_TWO
Internal ROM(OneNAND)
0
1
1
1
1
Internal ROM(NAND) Xm0OEn/nIORD_CF [2,11,12] INT_EXT_ONE RDY_EXT_ONE
Internal ROM(SD/MMC)
1 X
1 1
1 1
1 1
1 1
ON :EXTCLK
OFF :XTI
Xm0DATA[15:0] [2,10,11]
Xm0DATA9 Xm0DATA11 Xm0DATA13 Xm0DATA15 B
CFG4 1 2 3 4
[2] Xm0CSn2 [2] Xm0RPn/RnB
8 7 6 5
QSH-030-01-F-D-A
M0CSn2 [11,12] RnB [11] nCS_EXT_ONE RPn_EXT
oneNAND Connector
X2
KHS04
27MHz (SMD,SX-8) 1
R947 R187
X3
XXTI [3] 4
VDD_D
EXTCLK TP84
X4
3 2 1
[3] XDBGSEL
NC/R1005
3
2
R189
5M/R1005
C28
XrtcXTO [3]
C26
3
100K/R1005
OSC2
1M/R1005
R949
1 2
XXTO [3] C27
VDD
OUT
3
1
OE
GND
2
A
0/R1005
Title
0/R1005
SMDK6410 CPU Board (S3C6410 Evaluation Board)
NC/R1005
13pF
A2-3PA-2.54DSA
Size A3
Clocks
Date: 5
25pF
XEXTCLK [3]
SAMSUNG ELECTRONICS CO.,LTD
R193 13pF
25pF R191
4
R192 15pF
C25
12MHz (SMD,SCO-103)
C29 15pF
C24 100K/R1005
R948
XrtcXTI [3] R190
J1 VDD_D XDBGSEL GND
X27MXTO [3]
R188
32.768KHz (CH-308)
VDD_D A
1M/R1005
VDD_D
NC/R1005
12MHz (SMD,SX-8)
OneNANDC(CS2)
3
NANDC(CS2)
2
ON OFF OFF ON
1
[1,2]: [3,4]: [1,2]: [3,4]:
VDD_D
NAND/ONENAND
4
X27MXTI [3]
CFG4
4
3
2
Document Number oneNAND/MIPI/JTAG/CLK Wednesday, June 18, 2008
Rev 0.2 Sheet 1
14
of
16
5
4
B_CAMDATA0
TP86 B_CAMDATA0
B_CAMPCLK
TP87 B_CAMPCLK
B_CAMDATA1
TP88 B_CAMDATA1
B_CAMVSYNC
TP89 B_CAMVSYNC
B_CAMDATA2
TP90 B_CAMDATA2
B_CAMHREF
TP91 B_CAMHREF
D
VDD_CAM_EXT
CB86
CB87
100nF
100nF
CTB32
+
10uF/6.3V/T2012
VDD_CAMIP R194
B_CAMDATA3
TP92 B_CAMDATA3
CB84
B_CAMDATA4
TP93 B_CAMDATA4
100nF
VCCA0 VCCA1
B_CAMDATA5
TP94 B_CAMDATA5
42 31
B_CAMDATA6
TP95 B_CAMDATA6
B_CAMDATA7
TP96 B_CAMDATA7
B_CAMDATA0 B_CAMDATA1 B_CAMDATA2 B_CAMDATA3 B_CAMDATA4 B_CAMDATA5 B_CAMDATA6 B_CAMDATA7
47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26
1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 L : B to A H : A to B 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8
48 25
1OE 2OE
45 39 34 28
GND0 GND1 GND2 GND3
VDD_CAM_1.5V
1 3 5 7 9 11 13 15 17 19
[3,9,16] Xi2cSDA0 [3,9,16] Xi2cSCL0 B_CAMRST VDD_CAM_1.5V B_CAMPCLK B_CAMVSYNC CB89
CTB34
CTB35
+
XciYDATA[7:0] [4]
(VDDIO 2.8V) VDD_CAM_EXT
CON13 2 4 6 8 10 12 14 16 18 20
B_CAMPCLK B_CAMHREF B_CAMVSYNC B_XirSDBW
B_CAMDATA[7:0] B_CAMCLK
B_CAMDATA7 B_CAMDATA6 B_CAMDATA5 B_CAMDATA4 B_CAMDATA3 B_CAMDATA2 B_CAMDATA1 B_CAMDATA0
AXK8L20125B_Header 100nF
100nF
10uF/6.3V/T2012
1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8
2 3 5 6 8 9 11 12
2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8
13 14 16 17 19 20 22 23
1DIR 2DIR
1 24
GND7 GND6 GND5 GND4
4 10 15 21
D
XciYDATA0 XciYDATA1 XciYDATA2 XciYDATA3 XciYDATA4 XciYDATA5 XciYDATA6 XciYDATA7 XciPCLK [4] XciHREF [4] XciVSYNC [4] XirSDBW [3,12,16]
R196 0/R1005
VDD_CAM_EXT
B_CAMHREF
+ 10uF/6.3V/T2012
C
CB85 100nF
7 18
VCCB0 VCCB1
0/R1005
B_CAMDATA[7:0]
R195
CB88
U35
10uF/6.3V/T2012
0/R1005
1
VDD_CAM_EXT
(VDDA 2.8V) VDD_CAM_EXT
CTB33
+
2
TP85 B_XirSDBW
B_XirSDBW
Camera Interface
3
R197
10K/R1005
SN74AVCA164245DGG
C
CAM IF
B_CAMCLK B_CAMRST
CB90
VDD_CAMIP
U36
VDD_CAM_EXT
100nF
1 2 3 4 5 6 7 8 9 10 11 12
VCCA DIR A1 A2 A3 A4 A5 A6 A7 A8 GND GND
R198
24 23 22 21 20 19 18 17 16 15 14 13
VCCB VCCB OEn B1 B2 B3 B4 B5 B6 B7 B8 GND
0/R1005 XciCLK [4] XciRSTn [4]
CB91 100nF
SN74AVC8T245-DGV
B
B
VDD_CAM_1.5V
VDD_CAM2.8V
VDD_D R199
47K/R1005 R200
U37
0/R1005
VDD_CAM_EXT R201 0/R1005
VIN
2
GND
3
EN
OUT
PG
L5 2.2uH (LQH32CN2R2M33)
5
[7,8] REG_EN
4
+
C33 FAN2558S18X-SOT23
CT21 CTB36 2.2uF/6.3V/T2012
A
+
4
VIN
1
RUN
SW
3
VFB
5
R1
C32
100nF
1 2 3
+
22pF
1 2 3
JP27 PVDD_EXT
A2-3PA-2.54DSA
10uF/6.3V/T2012
VDD_CAMIP
JP26
CT20 C31
R2
10uF/6.3V/T2012
VDD_CAM2.8V
(2.8V)
R202 257K,1%/R1005
LTC3406ES5 2
1
U38
C_PWR_5V
100nF
GND
C30
VDD_D VDD_CAM_EXT
Vout=0.6(1+R2/R1) R2=R1(Vout/0.6V-1)
A2-3PA-2.54DSA
CAM_EXT
CAMIP
PVDD_EXT
A
R203 70K,1%/R1005
1uF
SAMSUNG ELECTRONICS CO.,LTD Title SMDK6410 CPU Board (S3C6410 Evaluation Board) Size A3 Date: 5
4
3
2
Document Number Camera Interface Wednesday, June 18, 2008
Rev 0.2 Sheet 1
15
of
16
4
3
C_PWR_5V
2
C_PWR_5V
1
VDD_D
VDD_D
[11] B_RESET [11] B_nBE0 [11] B_CSn_0 [11] B_CSn_2 [11] B_CSn_4
B
ATA/GPS
[11] [11] [11] [11] [11] [11]
[11] B_CLE [11] B_ALE B_WEn/nIOWR_CF B_WAITn/IORDY B_FWEn B_INTata B_INPACKata B_REGata
C_PWR_5V
[3] [3] [3] [3] [3] [3] [3,6,13] [3,6]
B_ADDR17 [11] B_ADDR19 [11] B_XmmcCMD1/ADDR_CF1 B_XmmcDATA1_1 [13] B_XmmcDATA1_3 [13]
[13]
B_DATA[15:0] [11]
B_DATA1
B_DATA3 B_DATA5 B_DATA7 B_DATA9 B_DATA11 B_DATA13 B_DATA15
XEINT0/KP_ROW0 XEINT2/KP_ROW2 XEINT4/KP_ROW4 XEINT6/KP_ROW6 XEINT8/ADDR_CF0 XEINT10/ADDR_CF2 XEINT12 XEINT14
[13] B_SPI0_CLK/ADDR_CF1
[13] B_SPI0_MISO/ADDR_CF0 [13] B_SPI0_CSn [13] B_SPI0_MOSI/ADDR_CF2
[9] WHITE_LED PVCCAUX1 [9] WLED_OUT1 PVCCAUX2 PVCCAUX3 B_nBE1 [11] B_CSn_1 [11] B_CSn_3 [11] B_CSn_5 [11]
PVCCM3BT
B_RnB [11] AP_nRESET [2] B_OEn/nIORD_CF [11] Modem_nRESET [2] B_FREn [11] B_WEata [11] B_OEata [11] B_CData [11]
C_PWR_5V
TP101
PVDD_SYS
[4] XdacOUT_0
PVCCM2MTV [4] Xadc_AIN4_YM [4] Xadc_AIN6_XM VDD_D
51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100
101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149
101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149
102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150
102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150
QSS-075-01-F-D-A
MODEM/Host/Keypad Interface
51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99
Xhi_D1/DATA_CF1 [14] Xhi_D3/DATA_CF3 [14] Xhi_D5/DATA_CF5 [14] Xhi_D7/DATA_CF7 [14] Xhi_D9/DATA_CF9/KP_ROW1 [4] Xhi_D11/DATA_CF11/KP_ROW3 [4] Xhi_D13/DATA_CF13/KP_ROW5 [4] Xhi_D15/DATA_CF15/KP_ROW7 [4] Xhi_D17/DATA_CF9 [4] Xhi_A1/ADDR_CF1/KP_COL1 [4] Xhi_A3/KP_COL3/Xm0INTata [4] Xhi_A5/KP_COL5/Xm0INPACKata [4] Xhi_A7/KP_COL7/Xm0CData [4] Xhi_A9/CE_CF1 [4,6] Xhi_A11/IOWR_CF [4] XhiCSn/CE_CF0 [4] XhiCSn_sub/CF_IORD [4] XhiOEn/CF_IORDY [4]
D
PVDD_EXT
PVDD_LCD
XVD[23:0] [4]
XVD1 XVD3 XVD5 XVD7 XVD9 XVD11 XVD13 XVD15 XVD17 XVD19 XVD21 XVD23
Display
102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150
[4] XVSYNC [4] XVDEN [4] XHSYNC
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
C
XVCLK [4] XEINT1/KP_ROW1 XEINT3/KP_ROW3 XEINT5/KP_ROW5 XEINT7/KP_ROW7 XEINT9/ADDR_CF1 XEINT11 [3,6] XEINT13 [3,6,13] XEINT15 [3,6]
[3] [3] [3] [3,8] [3]
B_SPI1_CLK/MMC2_CLK/i2sV40_DO1 [13]
SPI Port 1
102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150
Display
101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149
UART1, 3 (IrDA)
101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149
[4] XVD[23:0]
B_ADDR[15:0] [11]
TP100
XVD2 XVD4 XVD6 XVD8 XVD10 XVD12 XVD14 XVD16 XVD18 XVD20 XVD22
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
B_SPI1_MISO/MMC2_CMD/i2sV40_DO0 [13] B_SPI1_CSn/i2sV40_DO2 [13] B_SPI1_MOSI [13] PMIC_MODEM_MIC_P [9] PMIC_MIC1_N [9] PMIC_MIC1_P [9] PMIC_MIC2_N [9] PMIC_MIC2_P [9] B_HSMMC_DAT4/i2sV40_BCLK [13] B_HSMMC_DAT5/i2sV40_CDCLK [13] B_HSMMC_DAT6/i2sV40_LRCLK [13] B_HSMMC_DAT7/i2sV40_DI [13] XdacOUT_1 [4]
PVDD_SS
B
I2S
B_DATA4 B_DATA6 B_DATA8 B_DATA10 B_DATA12 B_DATA14
XVD0
XPCM_DCLK1/I2S_CLK1/AC97_BITCLK0 [3,9] XPCM_EXTCLK1/I2S_CDCLK1/AC97_RSTn0 [3,9] XPCM_FSYNC1/I2S_LRCLK1/AC97_SYNC0 [3,9] XPCM_SIN1/I2S_DI1/AC97_SDI0 [3,9] XPCM_SOUT1/I2S_DO1/AC97_SDO0 [3,9] B_ADDR1 B_ADDR3 B_ADDR5 B_ADDR7 B_ADDR9 B_ADDR11 B_ADDR13 B_ADDR15
[4] XhiCSnmain/CE_CF1 [4] XhiWEn/CF_IOWR [4,8,12] XhiINTR
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
Touch Screen
B_DATA0 B_DATA2
[3,11]
Xhi_A0/ADDR_CF0/KP_COL0 Xhi_A2/ADDR_CF2/KP_COL2 Xhi_A4/KP_COL4/Xm0RSTata Xhi_A6/KP_COL6/Xm0REGata Xhi_A8/CE_CF0 Xhi_A10/IORD_CF Xhi_A12/IORDY_CF
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
External Interrupt /Keypad
Memory Port 0 (ROM I/F)
[13] B_XmmcCLK1/ADDR_CF0 [13] B_XmmcDATA1_0/ADDR_CF2 [13] B_XmmcDATA1_2 [11] B_DATA[15:0]
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100
XuRXD_1 [3] XuTXD_1 [3] XuCTSn_1/ADDR_CF0 [3] XuRTSn_1/ADDR_CF1 [3] XuRXD_3/ExdREQ/IrRXD/ADDR_CF2/Xi2cSCL1 XuTXD_3/ExdACK/IrTXD/Xi2cSDA1 [3] XirSDBW [3,12,15] Xi2cSCL0 [3,9,15] XnRESET [2,3,6,14]
[4] [4] [4] [4] [4,6] [4,6] [4]
TV
[11] B_ADDR16 [11] B_ADDR18
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100
PMIC_MONO_SPK_N [9] PMIC_MONO_SPK_P [9] PMIC_MODEM_SPK_N [9] PMIC_MODEM_SPK_P [9]
External Interrupt /Keypad
[11] B_ADDR[15:0]
51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99
[9] [9] [9] [9]
Xhi_D0/DATA_CF0 Xhi_D2/DATA_CF2 Xhi_D4/DATA_CF4 Xhi_D6/DATA_CF6 Xhi_D8/DATA_CF8/KP_ROW0 Xhi_D10/DATA_CF10/KP_ROW2 Xhi_D12/DATA_CF12/KP_ROW4 Xhi_D14/DATA_CF14/KP_ROW6 Xhi_D16/DATA_CF8
SPI Port 0
B_ADDR0 B_ADDR2 B_ADDR4 B_ADDR6 B_ADDR8 B_ADDR10 B_ADDR12 B_ADDR14
51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99
PMIC_STEREO_CH2 PMIC_STEREO_CH1 PMIC_BEAR_SPK_N PMIC_BEAR_SPK_P
[14] [14] [14] [14] [4] [4] [4] [4] [4]
Touch Screen
[3,9] XPCM_DCLK0/I2S_CLK0/AC97_BITCLK0/ADDR_CF0 [3,9] XPCM_EXTCLK0/I2S_CDCLK0/AC97_RSTn0/ADDR_CF1 [3,9] XPCM_FSYNC0/I2S_LRCLK0/AC97_SYNC0/ADDR_CF2 [3,9] XPCM_SIN0/I2S_DI0/AC97_SDI0 [3,9] XPCM_SOUT0/I2S_DO0/AC97_SDO0
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
Audio Port 1
C
Audio Port 0
[3] XnRSTOUT
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
I2C
[3] XuRXD_0 [3] XuTXD_0 [3] XuCTSn_0/ADDR_CF0 [3] XuRTSn_0/ADDR_CF1 [3] XuRXD_2/ExdREQ/IrRXD/ADDR_CF0 [3] XuTXD_2/ExdACK/IrTXD/ADDR_CF1 [3,9,15] Xi2cSDA0
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
Memory Port 0 (ROM I/F)
[3] PWM_TOUT1 [3] PWM_TOUT0 [3,8,13] XPWM_ECLK
I2C
UART0, 2
PWM
[9] PMIC_STEREO_VMID [9] PMIC_REM_IN TP97 TP98 PVDD_AUDIO
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
ATA/GPS
D
JB2 MODEM/Host/Keypad Interface
JB1
TV
5
Xadc_AIN5_YP [4] Xadc_AIN7_XP [4] VDD_D
QSS-075-01-F-D-A
PVDD_LCD
C_PWR_5V
VDD_D
10uF/6.3V/T2012 CB92 CTB37
CB93 CTB38
+ C_PWR_5V
A
PVCCAUX1
VDD_D
PVCCAUX2
PVCCAUX3
PVCCM3BT
PVCCM2MTV
PVDD_SS
PVDD_AUDIO
PVDD_EXT
+
CB96 CTB43
+
CB97 CTB44
+
CB98 CTB45
+
CB99 CTB46
+
CB100 CTB47
+
CB101 CTB48
+
CB102 CTB49
+
CB103 CTB50
+
CB104 CTB51
+
+
+
PVDD_SYS 100nF
CTB41 CB95 CTB42
CTB39 CB94 CTB40
+
CB105 CTB52
+
10uF/6.3V/T2012
100nF
A
100nF
10uF/6.3V/T2012
+
10uF/6.3V/T2012
SAMSUNG ELECTRONICS CO.,LTD 100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
Title SMDK6410 CPU Board (S3C6410 Evaluation Board)
10uF/6.3V/T2012 10uF/6.3V/T2012
10uF/6.3V/T2012
10uF/6.3V/T2012
10uF/6.3V/T2012
10uF/6.3V/T2012
10uF/6.3V/T2012
10uF/6.3V/T2012
10uF/6.3V/T2012
10uF/6.3V/T2012
10uF/6.3V/T2012
10uF/6.3V/T2012 Size A3 Date:
5
4
3
2
Document Number B2B Connector Wednesday, June 18, 2008
Rev 0.2 Sheet 1
16
of
16
5
4
3
2
1
SMDK6410 Base B'd (S3C6410 Evaluation Board) Schematics Revision D
Rev 0.0 Rev 0.1 Rev 0.2
Description
Date 2008. 02.22 2008. 04.02 2008. 04.30
Preliminary Version Second Version (Changed sheet 3 ~ 10, 12, 13, 15, 16 and 17) Third Version (Changed sheet 3, 5, 14 and 17)
D
C
B
C
Table of Contents
Part Reference
Page Function ------------------------------------------------------01 Revision History 02 B2B Connector(Base) 03 NOR/SRAM/NAND/Config 04 Audio(General0) 05 Audio(Jack)/Multi-IIC/PWM 06 Audio(WM9713_AC97) 07 Audio(WM8580_IIS5.1CH) 08 CF Socket (ATA) 09 UART/IrDA 10 Ext. Bus/ Modem I/F 11 Ethernet 10Mbps(CS8900) 12 Ethernet 100Mbp(LAN9115) 13 Keypad 14 Module Connector1_2 15 Module Connector3_4 16 Module Connector5 (LCD)/TV 17 Power
--------------------------------------------------U : Component or Regurator IC C : Capacitor CB : Capacitor Bypass CT : Capacitor Tantal CTB : Capacitor Tantal Bypass J : Jumper JB : CPU or Base connector JP : Jumper Power R : Resistor RA : Resistor Array RP : Resistor Power VR : Variable Resistor L : Inductor FB : Ferrite Bead OSC : Oscillator X : X-tal (Crystal) Q : Transistor or FET D : Diode ZD : Zener Diode LED : LED Diode SW : SWitch Tact/Push CON : CONnector CFG : ConFiGure switch (DIP/Slide) TP : Test Point (SMD) TPH : Test Point Hole (Through Hole) MTH: Mount Through Hole M (MOD) : MODule Interface connector
A
B
A
SAMSUNG ELECTRONICS CO.,LTD Title SMDK6410 Base Board (S3C6410 Evaluation Board) Size A3 Date: 5
4
3
2
Document Number Revision History Wednesday, April 30, 2008
Rev 0.2 Sheet 1
1
of
17
2
MODEM/Host/Keypad Interface
VDD3.3V
Memory Port 0 (ROM I/F)
B_DATA4 B_DATA6 B_DATA8 B_DATA10 B_DATA12 B_DATA14 [8] B_RESET [3,10] B_nBE0 [3] B_CSn_0 [3] B_CSn_2 [3] B_CSn_4
B
ATA
[3] B_CLE [3] B_ALE [3,8,10..12] B_WEn/nIOWR_CF [8,10,11] B_WAITn/IORDY [3] B_FWEn [8] B_INTata [8] B_INPACKata [8] B_REGata
B_PWR_5V
B_ADDR17 B_ADDR19
[16] XVD[23:0]
[16] XVSYNC [16] XVDEN [16] XHSYNC B_ADDR[19:0] [3,8,10..12]
B_XmmcCMD1/ADDR_CF1 [13] B_XmmcDATA1_1 [13] B_XmmcDATA1_3 [13] TP11 B_DATA[15:0] [3,8,10..12] B_DATA1
B_DATA3 B_DATA5 B_DATA7 B_DATA9 B_DATA11 B_DATA13 B_DATA15
[13] [13,15] [10,13,15,16] [9,13,15,16] [8,10,14] [11,12,14,17] [17] [16,17]
[14,16] B_SPI0_CLK/ADDR_CF1
[14..16] B_SPI0_MISO/ADDR_CF0 [14,16] B_SPI0_CSn [3,14..16] B_SPI0_MOSI/ADDR_CF2
PVCCAUX1 [16] WHITE_LED [16] WLED_OUT1 PVCCAUX2 (Now, Not Used) PVCCAUX3 (Now, Not Used) PVDD_SYS TP16 (Now, Not Used) PVCCM3BT
B_nBE1 [3,10,11] B_CSn_1 [3] B_CSn_3 [3] B_CSn_5 [3] B_RnB [3] AP_nRESET [10] B_OEn/nIORD_CF [3,8,10..12] Modem_nRESET [10] B_FREn [3] B_WEata [8] B_OEata [8] B_CData [8]
XEINT0/KP_ROW0 XEINT2/KP_ROW2 XEINT4/KP_ROW4 XEINT6/KP_ROW6 XEINT8/ADDR_CF0 XEINT10/ADDR_CF2 XEINT12 XEINT14
[16] XdacOUT_0 PVCCM2MTV [16] Xadc_AIN4_YM [16] Xadc_AIN6_XM VDD3.3V
(Now, Not Used)
B_PWR_5V
PVDD_SYS
PVDD_LCD
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99
51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100
101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149
101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149
102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150
102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150
QTS-075-03-F-D-A
Xhi_D1/DATA_CF1 [8,10] Xhi_D3/DATA_CF3 [8,10,14] Xhi_D5/DATA_CF5 [8,10,14] Xhi_D7/DATA_CF7 [8,10,14] Xhi_D9/DATA_CF9/KP_ROW1 [8,10,13] Xhi_D11/DATA_CF11/KP_ROW3 [8,10,13] Xhi_D13/DATA_CF13/KP_ROW5 [8,10,13] Xhi_D15/DATA_CF15/KP_ROW7 [8,10,13] Xhi_D17/DATA_CF9 [10] Xhi_A1/ADDR_CF1/KP_COL1 [8,10,13] Xhi_A3/KP_COL3/Xm0INTata [8,10,13] Xhi_A5/KP_COL5/Xm0INPACKata [8,10,13,14] Xhi_A7/KP_COL7/Xm0CData [8,10,13,14] Xhi_A9/CE_CF1 [8,10,14] Xhi_A11/IOWR_CF [8,10,15]
D
XhiCSn/CE_CF0 [8,10] XhiCSn_sub/CF_IORD [8,10,15] XhiOEn/CF_IORDY [8,10,15]
PVDD_EXT (Now, Not Used) PVDD_LCD
XVD[23:0] [16]
XVD1 XVD3 XVD5 XVD7 XVD9 XVD11 XVD13 XVD15 XVD17 XVD19 XVD21 XVD23
Display
B_ADDR1 B_ADDR3 B_ADDR5 B_ADDR7 B_ADDR9 B_ADDR11 B_ADDR13 B_ADDR15
XVD2 XVD4 XVD6 XVD8 XVD10 XVD12 XVD14 XVD16 XVD18 XVD20 XVD22
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
C
XVCLK [16] XEINT1/KP_ROW1 XEINT3/KP_ROW3 XEINT5/KP_ROW5 XEINT7/KP_ROW7 XEINT9/ADDR_CF1 XEINT11 [17] XEINT13 [14,16,17] XEINT15 [14,16,17]
External Interrupt /Keypad
102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150
B_DATA2
E_XPCM_DCLK1/I2S_CLK1/AC97_BITCLK0 [4] E_XPCM_EXTCLK1/I2S_CDCLK1/AC97_RSTn0 [4] E_XPCM_FSYNC1/I2S_LRCLK1/AC97_SYNC0 [4] E_XPCM_SIN1/I2S_DI1/AC97_SDI0 [4] E_XPCM_SOUT1/I2S_DO1/AC97_SDO0 [4]
Display
102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150
[13] B_XmmcCLK1/ADDR_CF0 [13] B_XmmcDATA1_0/ADDR_CF2 [13] B_XmmcDATA1_2 [3,8,10..12] B_DATA[15:0] B_DATA0
XVD0
External Interrupt /Keypad
101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149
B_ADDR16 B_ADDR18
[3,8,10..12] B_ADDR[19:0]
Xhi_A0/ADDR_CF0/KP_COL0 Xhi_A2/ADDR_CF2/KP_COL2 Xhi_A4/KP_COL4/Xm0RSTata Xhi_A6/KP_COL6/Xm0REGata Xhi_A8/CE_CF0 Xhi_A10/IORD_CF Xhi_A12/IORDY_CF
[8,10] XhiCSnmain/CE_CF1 [8,10] XhiWEn/CF_IOWR [10,16] XhiINTR
SPI Port 0
C
[5,8..10]
Xhi_D0/DATA_CF0 Xhi_D2/DATA_CF2 Xhi_D4/DATA_CF4 Xhi_D6/DATA_CF6 Xhi_D8/DATA_CF8/KP_ROW0 Xhi_D10/DATA_CF10/KP_ROW2 Xhi_D12/DATA_CF12/KP_ROW4 Xhi_D14/DATA_CF14/KP_ROW6 Xhi_D16/DATA_CF8
TV
101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149
B_ADDR0 B_ADDR2 B_ADDR4 B_ADDR6 B_ADDR8 B_ADDR10 B_ADDR12 B_ADDR14
XuRXD_1 [9,15] XuTXD_1 [9,15] XuCTSn_1/ADDR_CF0 [9,15] XuRTSn_1/ADDR_CF1 [9,15] XuRXD_3/ExdREQ/IrRXD/ADDR_CF2/Xi2cSCL1 XuTXD_3/ExdACK/IrTXD/Xi2cSDA1 [5,9,10] XirSDBW [9] Xi2cSCL0 [5,7,14,15] XnRESET [3]
[8,10,13] [8,10,13] [8,10,13] [8,10,13,14] [8,10] [8,10,15] [8,10]
Touch Screen
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100
[4] E_XPCM_DCLK0/I2S_CLK0/AC97_BITCLK0/ADDR_CF0 [4] E_XPCM_EXTCLK0/I2S_CDCLK0/AC97_RSTn0/ADDR_CF1 [4] E_XPCM_FSYNC0/I2S_LRCLK0/AC97_SYNC0/ADDR_CF2 [4] E_XPCM_SIN0/I2S_DI0/AC97_SDI0 [4] E_XPCM_SOUT0/I2S_DO0/AC97_SDO0
TP7 TP8 TP9 TP10
Audio Port 1
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100
[10..16] XnRSTOUT
PMIC_MONO_SPK_N PMIC_MONO_SPK_P PMIC_MODEM_SPK_N PMIC_MODEM_SPK_P
UART1, 3 (IrDA)
51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99
[9,10,14] XuRXD_0 [9,10,14] XuTXD_0 [9,14] XuCTSn_0/ADDR_CF0 [9,14] XuRTSn_0/ADDR_CF1 [8..10,14] XuRXD_2/ExdREQ/IrRXD/ADDR_CF0 [8..10,14] XuTXD_2/ExdACK/IrTXD/ADDR_CF1 [5,7,14,15] Xi2cSDA0
PMIC_STEREO_CH2 [5] PMIC_STEREO_CH1 [5] TP4 TP6
[8,10] [8,10] [8,10] [8,10,14] [8,10,13] [8,10,13] [8,10,13] [8,10,13] [10]
I2C
51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99
[5,16] PWM_TOUT1 [5,16] PWM_TOUT0 [5,16] XPWM_ECLK
PMIC_BEAR_SPK_N PMIC_BEAR_SPK_P
Memory Port 0 (ROM I/F)
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
ATA
PWM UART0, 2 I2C
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
TP3 TP5
PVDD_AUDIO
Audio Port 0
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
PMIC_STEREO_VMID PMIC_REM_IN
TP1 TP2 D
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
VDD3.3V
JB2
[13] [10,13,15] [10,13,16] [9,13,15,16] [14,17]
B_SPI1_CLK/MMC2_CLK/i2sV40_DO1 [7,14,15]
B_SPI1_MISO/MMC2_CMD/i2sV40_DO0 [7,14,15] B_SPI1_CSn/i2sV40_DO2 [7,14,15] B_SPI1_MOSI [14,15] PMIC_MODEM_MIC_P
TP12 PMIC_MIC1_N [5,6] TP13 TP14 TP15 B_HSMMC_DAT4/i2sV40_BCLK [7,8,13,15] B_HSMMC_DAT5/i2sV40_CDCLK [7,8,13,15] B_HSMMC_DAT6/i2sV40_LRCLK [7,8,15] B_HSMMC_DAT7/i2sV40_DI [7,15]
PMIC_MIC1_P PMIC_MIC2_N PMIC_MIC2_P
I2S
JB1
MODEM/Host/Keypad Interface
B_PWR_5V
1
SPI Port 1
3
B
XdacOUT_1 [16] PVDD_SS
Touch Screen
4
B_PWR_5V
TV
5
Xadc_AIN5_YP [16] Xadc_AIN7_XP [16] VDD3.3V
QTS-075-03-F-D-A CTB1
CTB2
CB1
CB2
+
+
10uF,6.3V/T2012 100nF/C1608
B_PWR_5V
VDD3.3V
10uF,6.3V/T2012 100nF/C1608 CTB5
B_PWR_5V
A
PVCCAUX1
VDD3.3V
(Now, Not Used)
(Now, Not Used)
PVCCAUX2
PVCCAUX3
(Now, Not Used)
PVCCM3BT
PVCCM2MTV
PVDD_SS
PVDD_AUDIO
CB3
CTB3
+
PVDD_EXT
CB4 +
+ CTB4 10uF,16V/T3216
10uF,6.3V/T2012 100nF/C1608 CTB8 CTB6
CB5 +
CB6 10uF,16V/T3216
CTB9 CB7
+
+ CTB7
10uF,6.3V/T2012
CTB10 CB8
CTB11 CB9
+
+
10uF,6.3V/T2012
10uF,6.3V/T2012
CTB12 CB10
+ 10uF,6.3V/T2012
CTB13 CB11
+ 10uF,6.3V/T2012
CTB14 CB12
+ 10uF,6.3V/T2012
CTB15 CB13
+ 10uF,6.3V/T2012
10uF,16V/T3216
100nF/C1608
CTB16 CB14
+
+
10uF,6.3V/T2012
10uF,6.3V/T2012
SAMSUNG ELECTRONICS CO.,LTD Title SMDK6410 Base Board (S3C6410 Evaluation Board)
10uF,16V/T3216
100nF/C1608
100nF/C1608
100nF/C1608
100nF/C1608
100nF/C1608
100nF/C1608
100nF/C1608
100nF/C1608
100nF/C1608
100nF/C1608 Size A3 Date:
5
4
3
2
Document Number B2B Connector(Base) Wednesday, April 30, 2008
Rev 0.2 Sheet 1
2
of
17
A
5
4
3
2
1
CFGB1:nCS0 SROM Selector
AMD Flash Memory(SOCKET) SRAM B_ADDR[19:0] [2,8,10..12]
B_ADDR1 B_ADDR2 B_ADDR3 B_ADDR4 B_ADDR5 B_ADDR6 B_ADDR7 B_ADDR8 B_ADDR9 B_ADDR10 B_ADDR11 B_ADDR12 B_ADDR13 B_ADDR14 B_ADDR15 B_ADDR16 B_ADDR17 B_ADDR18 B_ADDR19 R7 0/R1608
25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 10
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
R8 0/R1608
27 46
VSS0 VSS1
B_ADDR[19:0] [2,8,10..12]
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1
29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45
SRAM
[1]
NOR(AMD)
CFGB1 1 2 3 4
[2] B_CSn_0
nCE nOE nWE nRY/BY nRESET nBYTE VDD0
26 28 11 15 12 47 37
nCS_AMD B_OEn/nIORD_CF [2,8,10..12] B_WEn/nIOWR_CF [2,8,10..12] VDD3.3V XnRESET [2]
B_ADDR1 B_ADDR2 B_ADDR3 B_ADDR4 B_ADDR5 B_ADDR6 B_ADDR7 B_ADDR8 B_ADDR9 B_ADDR10 B_ADDR11 B_ADDR12 B_ADDR13 B_ADDR14 B_ADDR15 B_ADDR16 B_ADDR17 B_ADDR18
VDD3.3V
CB15
CTB17
+
CB16
+
5 4 3 2 1 44 43 42 27 26 25 24 23 22 21 20 19 18
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
11 33
VCC VCC
12 34
VSS VSS
B_DATA0 B_DATA1 B_DATA2 B_DATA3 B_DATA4 B_DATA5 B_DATA6 B_DATA7 B_DATA8 B_DATA9 B_DATA10 B_DATA11 B_DATA12 B_DATA13 B_DATA14 B_DATA15
[4]
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16
7 8 9 10 13 14 15 16 29 30 31 32 35 36 37 38
WE LB UB OE
17 39 40 41
B_WEn/nIOWR_CF [2,8,10..12] B_nBE0 [2,10] B_nBE1 [2,10,11] B_OEn/nIORD_CF [2,8,10..12]
CS
6
nCS_SRAM
CFGB2
External
[3]
Ethernet
[2]
SRAM
[1]
NOR(AMD)
1 2 3 4
[2] B_CSn_1
CFGB3:nCS2 SROM Selector CFGB4:nCS3 [4] External [3]
Ethernet
[2]
XD card
[1]
NAND
1 2 3 4
[2] B_CSn_2
8 7 6 5
K6X4016T3F_1
8 7 6 5
nCS_NAND nCS_XD nCS_ETH [12] nCS_EXT [10]
C
KHS04
1 2 3 4
[2] B_CSn_4
CFGB5:nCS4 SROM Selector CFGB6:nCS5 [4] Ethernet
NAND Flash memory (SOCKET )
NAND U3
VDD3.3V
R15 NC/R1608 [2] B_RnB [2] B_FREn nCS_NAND nCS_NAND2
nCS_NAND3 nCS_NAND4 [2] B_CLE [2] B_ALE [2] B_FWEn [2,14..16] B_SPI0_MOSI/ADDR_CF2 R28 NC/R1608
VDD3.3V
R11 10K/R1608
R457 0/R1608
CFG7 GPC2
R450 10K/R1608
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
NC0 NC1 NC2 NC3 NC4 NC5 R/nB nRE nCE NC6 NC7 VCC0 VSS0 NC8 NC9 CLE ALE nWE nWP NC10 NC11 NC12 NC13 NC14
VDD3.3V [2,8,10..12] B_DATA[15:0]
NC29/ VSS2 NC28/ IO15 NC27/ IO7 NC26/ IO14 IO7/ IO6 IO6/ IO13 IO5 IO4/ IO12 NC25/ IO4 NC24 NC23 VCC1 VSS/ NC22 NC21 NC20 NC19/ IO11 IO3 IO2/ IO10 IO1/ IO2 IO0/ IO9 NC18/ IO1 NC17/ IO8 NC16/ IO0 NC15/ VSS1
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
R35 NC/R1608 Socket S-TSO-SM-048-A (With K9F2G08UOA-P)
3
B1
B2
6
2
C1
C2
5
1
A1
A2
4
R12 R13 R16
R19
B_DATA15 0/R1608 B_DATA7 0/R1608 B_DATA14 0/R1608 IO7/IO6 IO6/IO13 B_DATA5 IO4/IO12 B_DATA4 0/R1608
IO2/IO10 R25
0/R1608
R29 R31 R32
IO2/IO10 IO1/IO2 IO0/IO9 0/R1608 0/R1608 0/R1608
B_DATA11 B_DATA3 IO1/IO2 B_DATA1 B_DATA8 B_DATA0
[2] B_CSn_4 [2] B_CSn_5
NC/R1608
R38
NC/R1608
R39
NC/R1608
IO0/IO9
R36 0/R1608
NC/R1608 B_DATA6
R17
0/R1608
R18
NC/R1608 B_DATA13
R20
0/R1608
R21
NC/R1608 B_DATA12
R22
0/R1608
R24
NC/R1608 B_DATA10
SRAM
[2]
NOR(AMD)
[1]
CF card
B_DATA4
NC/R1608 B_DATA2
R30
0/R1608
R33
NC/R1608 B_DATA9
R34
0/R1608
TP17
RnB
TP18
nFRE
[2] B_ALE
TP19
ALE
[2] B_CLE
TP20
CLE
[2] B_FWEn
TP21
nFWE
CFGB6 1 2 3 4
[2] B_CSn_5
VDD3.3V 100K/R1608
R10
8 7 6 5
nCS_CF1 [8] nCS_AMD nCS_SRAM nCS_ETH [12]
KHS04
XD PICTURE CARD
B
VDD3.3V
[2,8,10..12] B_DATA[15:0]
B_DATA2
0/R1608
R27
[2] B_RnB
nCS_CF0 [8] nCS_AMD nCS_SRAM nCS_ETH [12]
KHS04
B_DATA6
R26
[2] B_FREn
8 7 6 5
B_DATA7
R23 4.7K/R1608 B_DATA7 B_DATA6 B_DATA5 B_DATA4 B_DATA3 B_DATA2 B_DATA1 B_DATA0
B_DATA1
B_DATA0 [2] B_FWEn [2] B_ALE [2] B_CLE nCS_XD [2] B_FREn [2] B_RnB
16-bit: R11,14,17,21,24,29 8-bit: R13,16,19,23,26,30
CAS220A1
R37
IO6/IO13
R14
[3]
VDD3.3V 100K/R1608
R9
CON1 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 19
VCC D7 D6 D5 D4 D3 D2 D1 D0 GND WP WE ALE CLE CE RE R/B GND GND
VDD3.3V
CB17
CB18 100nF/C1608
100nF/C1608
VDD3.3V
CTB19
nCS_XD
IO7/IO6
IO4/IO12
CB19
CB20
+ nCS_NAND2 nCS_NAND3 nCS_NAND4
A
xD_CARD Socket
SAMSUNG ELECTRONICS CO.,LTD Title
100nF/C1608
SMDK6410 Base Board (S3C6410 Evaluation Board) 100nF/C1608 10uF,6.3V/T2012
Size A3 Date:
5
nCS_NAND nCS_XD nCS_ETH [12] nCS_EXT [10]
CFGB4 1 2 3 4
[2] B_CSn_3
CFGB5
A
VDD3.3V 100K/R1608 100K/R1608 100K/R1608 100K/R1608
R3 R4 R5 R6
KHS04
NOR
Add&Changed on 04/30/2008
nCS_AMD nCS_SRAM nCS_ETH [12] nCS_EXT [10]
KHS04
B
D
8 7 6 5
CFGB3
100nF/C1608 10uF,6.3V/T2012
nCS_AMD nCS_SRAM nCS_EXT [10]
CFGB2:nCS1 SROM Selector
100nF/C1608
Socket S-TSO-SM-048-A (with AM29LV800BB,1MB) OR AM29LV160BB 10uF,6.3V/T2012
8 7 6 5 KHS04
[2,8,10..12] B_DATA[15:0]
U2
B_DATA0 B_DATA1 B_DATA2 B_DATA3 B_DATA4 B_DATA5 B_DATA6 B_DATA7 B_DATA8 B_DATA9 B_DATA10 B_DATA11 B_DATA12 B_DATA13 B_DATA14 B_DATA15
CTB18
C
External
[2]
[2,8,10..12] B_DATA[15:0]
U1 D
[3]
VDD3.3V 100K/R1608 100K/R1608
R1 R2
4
3
2
Document Number NOR/SRAM/NAND/Config Wednesday, April 30, 2008
Rev 0.2 Sheet 1
3
of
17
5
4
3
2
1
VDD_ext C1
100nF/C1608
U4 AVDD_ext
CFG1 1 2 3 4
D
8 7 6 5 KHS04
Speaker_nWM8753 /WM9713 [5] Mic_nWM8753/WM9713 [5] LineIn_nWM8753 /WM9713 [5] R41 100K/R1608
R40 100K/R1608
[2] E_XPCM_DCLK0/I2S_CLK0/AC97_BITCLK0/ADDR_CF0 [2] E_XPCM_EXTCLK0/I2S_CDCLK0/AC97_RSTn0/ADDR_CF1 [2] E_XPCM_FSYNC0/I2S_LRCLK0/AC97_SYNC0/ADDR_CF2 [2] E_XPCM_SIN0/I2S_DI0/AC97_SDI0 [2] E_XPCM_SOUT0/I2S_DO0/AC97_SDO0
R43 100K/R1608 R42
Audio Port 0
[2] : Mic
1B1 2B1 3B1 4B1 5B1
2 6 10 16 20
AC97_BITCLK [6] AC97_RSTn [6] AC97_SYNC [6] AC97_SDI [6] AC97_SDO [6]
4 8 14 18 22
1A2 2A2 3A2 4A2 5A2
1B2 2B2 3B2 4B2 5B2
5 9 15 19 23
XPCM_DCLK/I2S_CLK [6,7] XPCM_EXTCLK/I2S_CDCLK [6,7] XPCM_FSYNC/I2S_LRCLK [6,7] XPCM_SIN/I2S_DI [6,7] XPCM_SOUT/I2S_DO [6,7]
13 1
BX nBE
GND
12
Off: WM8580 (IIS) On: WM9713 (AC97)/PMIC
[4] : Reserved
C
SN74CBTLV3383DGVRE4
R49 R50 R51 R52 R53
0/R1608 0/R1608 0/R1608 0/R1608 0/R1608
R54 R55 R56 R57 R58
NC/R1608 NC/R1608 NC/R1608 NC/R1608 NC/R1608
M4_Port0_I2SSCLK/AC_BITCLK [15] M4_Port0_I2SCDCLK/AC_RSTn [15] M4_Port0_I2SLRCLK/AC_SYNC [15] M4_Port0_I2SSDI/AC_SDI [15] M4_Port0_I2SDO/AC97_SDO [15] M2_Port0_I2SSCLK/AC_BITCLK [14] M2_Port0_I2SCDCLK/AC_RSTn [14] M2_Port0_I2SLRCLK/AC_SYNC [14] M2_Port0_I2SSDI/AC_SDI [14] M2_Port0_I2SDO/AC97_SDO [14]
CFG2 1 2 3 4
C
VDD_ext
8 7 6 5
KHS04
D
Selector
[3] : LineIn
VDD_ext
AC97/IIS_PCM nAudio0_En
24
1A1 2A1 3A1 4A1 5A1
R44 R45 R46 R47 R48
CFG1:Audio Connector [1] : Speaker
0/R1608 0/R1608 0/R1608 0/R1608 NC/R1608
100K/R1608
VCC 3 7 11 17 21
AC97/IIS_PCM nAudio0_En nAudio1_En
R60 100K/R1608 R59 100K/R1608
C2
100nF/C1608
U5
R62 100K/R1608 R61
[2] E_XPCM_DCLK1/I2S_CLK1/AC97_BITCLK0 [2] E_XPCM_EXTCLK1/I2S_CDCLK1/AC97_RSTn0 [2] E_XPCM_FSYNC1/I2S_LRCLK1/AC97_SYNC0 [2] E_XPCM_SIN1/I2S_DI1/AC97_SDI0 [2] E_XPCM_SOUT1/I2S_DO1/AC97_SDO0
100K/R1608
VCC
24
3 7 11 17 21
1A1 2A1 3A1 4A1 5A1
1B1 2B1 3B1 4B1 5B1
2 6 10 16 20
XPCM_DCLK/I2S_CLK [6,7] XPCM_EXTCLK/I2S_CDCLK [6,7] XPCM_FSYNC/I2S_LRCLK [6,7] XPCM_SIN/I2S_DI [6,7] XPCM_SOUT/I2S_DO [6,7]
4 8 14 18 22
1A2 2A2 3A2 4A2 5A2
1B2 2B2 3B2 4B2 5B2
5 9 15 19 23
AC97_BITCLK [6] AC97_RSTn [6] AC97_SYNC [6] AC97_SDI [6] AC97_SDO [6]
13 1
BX nBE
GND
12
Off
Port 0 :AC97 Port 1: IIS/PCM
[2]
[3]
[4]
Audio Port 1 0/R1608 0/R1608 0/R1608 0/R1608 0/R1608
[1]
CFG2
Port 0 : Port 1 : Internal Internal
AC97/IIS_PCM nAudio1_En
B
B
SN74CBTLV3383DGVRE4 R63 R64 R65 R66 R67
Port 0 : Port 0 : Port 1 : IIS/PCM External External Reserved Port 1 : AC97
On
R68 R69 R70 R71 R72
NC/R1608 NC/R1608 NC/R1608 NC/R1608 NC/R1608
R73 R74 R75 R76 R77
0/R1608 0/R1608 0/R1608 0/R1608 0/R1608
M4_Port1_I2SSCLK/AC_BITCLK [15] M4_Port1_I2SCDCLK/AC_RSTn [15] M4_Port1_I2SLRCLK/AC_SYNC [15] M4_Port1_I2SSDI/AC_SDI [15] M4_Port1_I2SDO/AC97_SDO [15] M3_Port1_PCM_DCLK [15] M3_Port1_PCM_EXTCLK [15] M3_Port1_FSYNC [15] M3_Port1_PCM_SIN [15] M3_Port1_PCM_SOUT [15]
CON2
A
[2] E_XPCM_DCLK0/I2S_CLK0/AC97_BITCLK0/ADDR_CF0 [2] E_XPCM_EXTCLK0/I2S_CDCLK0/AC97_RSTn0/ADDR_CF1 [2] E_XPCM_FSYNC0/I2S_LRCLK0/AC97_SYNC0/ADDR_CF2 [2] E_XPCM_SIN0/I2S_DI0/AC97_SDI0 [2] E_XPCM_SOUT0/I2S_DO0/AC97_SDO0
1 2 3 4 5 6
A
7 8 9 10 11 12
E_XPCM_DCLK1/I2S_CLK1/AC97_BITCLK0 [2] E_XPCM_EXTCLK1/I2S_CDCLK1/AC97_RSTn0 [2] E_XPCM_FSYNC1/I2S_LRCLK1/AC97_SYNC0 [2] E_XPCM_SIN1/I2S_DI1/AC97_SDI0 [2] E_XPCM_SOUT1/I2S_DO1/AC97_SDO0 [2]
SAMSUNG ELECTRONICS CO.,LTD Title SMDK6410 Base Board (S3C6410 Evaluation Board)
A1-12PA-2.54DSA (HDR12-2.54-MALE) Size A3 Date: 5
4
3
2
Document Number Audio(General0) Wednesday, April 30, 2008
Rev 0.2 Sheet 1
4
of
17
5
VDD_ext
4
3
2
AVDD_ext
VDD3.3V
0 : NC ON 1 : NO ON
JP1 2
1
CTB20 10uF,6.3V/T2012 AVDD_ext
1
R78
AVDD_ext CTB21 10uF,6.3V/T2012
A2-2PA-2.54DSA
+
100/R1608
CB21
AVDD_ext
+
NC1
[7] WM8580_LINEIN_R
8
NC2
3
3
COM2
9
2
Line In Left
NO1
10
COM1
1 5
IN2
7
8
NC2
2
NO1
1.5K/R1608
10
NO2
+ CTB25
PJ-327-2
C3 6
220pF/C1608 10uF,6.3V/T2012
LineIn_nWM875 3/WM9713 [4]
NC1
[2,6] PMIC_MIC1_N [2,6] WM9713_MIC R81
MAX4764ETB
4
JACK2 VCC
1
COM1
3
3
COM2
9
2
IN1
5
GND
IN2
7
Mic In
Gnd
GND
IN1
D
100nF/C1608
U7
[7] WM8580_MIC
R80 1.5K/R1608
Line In
Line In Right
NO2
6
CB22 CTB22 47uF,6.3V/T3528
Gnd
[6] WM9713_LINE_R
2
1
R
[6] WM9713_LINE_L
BLM18PG121SN1
+
JACK1 VCC
L
FB2
4
R
CTB24 10uF,6.3V/T2012
10uF,6.3V/T2012
[7] WM8580_LINEIN_L
L
+ CTB23
U6
