Order No. TG-990802
Supplement Technical Guide Colour Television EURO 4 / EURO 4H and EURO 4D Chassis Circuit Explanations
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CONTENTS Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Chapter 1.
Common Circuits
1.
Geometry Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.
Audio Signal Processing (Euro 4 and Euro 4H only) . . . . . . . . . . . . . . . . . 5
3.
Audio Acoustic FeedBack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.
AF Audio Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 2.
Euro 4 Supplement
1.
Control Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.
Dynamic Automatic Focus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 3.
Euro 4H Supplement
1.
Control and Teletext Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.
F-Board Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.
Colour Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.
AV2 Video Out Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.
Vertical Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Chapter 4.
Euro 4D Supplement
1.
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.
Digtal Video Broadcasting Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.
Microprocessor and Teletext Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.
Memory IC (EAROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.
Video Display Processor (VDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.
Dynamic Auto Focus (DAF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.
Audio Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.
Headphone Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.
Audio and Video Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
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Introduction We at Panasonic realise that the service engineer needs to understand the circuitry inside the TV and for this need, we have produced this Supplemental Technical Guide.
This supplemental technical guide should be used in-conjunction with the EURO 4 Technical Guide and the relevant Service Manuals. Only those differences which have arisen with the introduction of new models are covered in this Supplemental Technical Guide, all other information is as presented in the EURO 4 Technical Guide (TZS8EL001).
This Supplemental Technical Guide contains updated information for the following: :
EURO 4 chassis.
:
EURO 4H chassis with new simple 100Hz processing.
:
EURO 4D IDTV chassis with integrated Digital Video Broadcasting (DVB) terrestial decoder.
As this supplemental technical guide covers three variants of the EURO 4 chassis, this technical guide has been split into chapters as presented in the contents.
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Chapter 1.
1
Common Circuits
Geometry Adjustment
Large screen CRT’s require an additional circuit which is used for picture geometry adjustment. This additional circuit is used to cancel the effects of the earths magnetic field.
Pin 3 is fed to the inverting input of internal op-amp1, while the input via pin 6 is fed to the non-inverting input of op-amp2. The result of increasing this d.c. current to the inverting input of op-amp1 is to reduce its output, while the output of op-amp2 is amplified increasing its output. This results in the picture rotating in an anti-clockwise direction.
This circuit is provided by IC1901 [IC1900 Euro 4D] (located on the M-Board TNP8EM021 or TNP8EM020) which contains two op-amps. These op-amps being configured as push-pulls devices.
Likewise, when the d.c. current is decreased the output from op-amp1 is amplified increasing its output, while the output of op-amp2 is decreased. This results in the picture rotating clockwise.
IC1901 [IC1900 Euro 4D] is fed a d.c. current which can be adjusted by the user via the OSD display. Here the user can adjust the picture geometry in 54 steps (+26 / -27). By increasing the OSD value the d.c. current to IC1901 [IC1900 Euro 4D] is also increased, under the control of microprocessor IC1101 pin 77, which is used to control the current fed to IC1901 [IC1900 Euro 4D] pins 3 and 6.
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A cancellation coil on the AK1 series is also controlled by IC1901, which is used to cancel any artifacts which could corrupt the purity of the CRT. The negative feedback loop for op-amp1 is via R1905 while the negative feedback for op-amp2 is via R1908.
AK1 Series Only Cancellation
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Chapter 2.
1
Common Circuits
Audio Signal Processing and 25 of IC2101 are now fed via the Acoustic Feedback (AFB) stage discussed in chapter 1 section 3. These changes are highlighted below:
As with all EURO 4 models, audio processing is provided by the MSP3410 IC2101. The MSP3410 is designed as a Multi-standard Sound Processor used in the processing of analogue and digital audio signals. A full description of its operation can be found in the Euro 4 Technical Guide, section 20.
: The right audio signal output from pin 24 and the left output from pin 25 of the MSP3410 IC2101 are fed via transistors Q2102 and Q2103 to connector E10 pins 1 and 2. The right and left audio signals are then passed to the Z-Board via connector Z4 pins 1 and 2, here the audio signals are processed by the Acoustic Feedback (AFB) stage discussed in chapter 1 section 3.
Although the internal processing of the MSP3410 IC2101 has not changed, the output processing path has, as shown in the diagram below. The left and right audio signals output from pins 24
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Chapter 3.
1
Common Circuits
Acoustic Feedback (AN6554)
The Euro 4 models which have an additional circuit named Acoustic Feedback (AFB), is located on the Z-Board and is used to overcome variations in the frequency response of the audio signal. These variations appear as peaks and troughs caused by factors such as cabinet, speaker cone construction, and ambient conditions. To overcome these
variations in frequency response, a microphone is positioned within the speaker enclosure and is used to monitor the acoustic conditions. This signal information being fed back to the AFB circuit (Z-Board) where frequency shaping occurs, thus providing a flat frequency response required for optimum sound production.
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3.1. Acoustic Feedback Processing The audio signals, output from the Multi-standard Sound Processor IC2101 pins 24 and 25 (located on the E-Board) are fed via transistors Q2102 and Q2103 via connectors E10 / Z4 pin 1 and 2 to the Acoustic Feedback (AFB) circuit, made up of IC2201 and IC2221, located on the Z-Board. Here the processing previously mentioned is performed before the audio signals are output from the AFB circuit and fedback to the E-Board via connectors Z4 and E10 pin 5 and 6, and to the input of the audio amplifier IC251.
From this RC network, the left audio speaker signal is input via pin 10 of IC2221. Here the feedback microphone signal input at pin 9 and the left speaker audio signal input at pin 10 are combined. This results in a flat frequency response of the audio signal being output from pin 8 of IC2221, providing a crisper, clearer sound for the user. This audio output from pin 8 of IC2221 is then fed to pin 5 of connector Z4, where the audio signal is fed back to the E-Board via connector E10. Once the left speaker audio signal is on the E-Board, the signal is fed to the audio output IC IC251.
A supply voltage of 8V [12V on Euro 4D] is applied to the VCC inputs of IC2221 and IC2201. This 8V [12V on Euro 4D] supply is also used to bias the op-amps of both ICs, the biasing of these op-amps being set to 1/2 Vcc by the op-amps at pins 12, 13 and 14 of both IC2221 and IC2201. To perform the processing already mentioned, two AN6554 devices are used. The AN6554 is a quadruple op-amp device used to perform AFB, with IC2201 processing the right channel audio signal and IC2221 processing the left channel audio signal.
Likewise the right microphone signal input via connector Z2 pin 1, is fed to IC2201 pin 2 via C2201 and R2201. The signal is buffered and output from pin 1 of IC2201, where the signal is split into two paths. The first sees the microphone signal being fed via the high-pass filter, consisting of capacitors C2211, C2212 and resistor R2204. The signal is then input to pin 5 where the signal is buffered and output via pin 7 and resistor R2207. Here the signal is added to the signal from the second path fed via resistors R2215 and R2205. After this signal conditioning of the right microphone signal, the added signals are then fed to pin 9 of IC2201. This negative feedback of the microphone signal is applied to the right speaker audio signal, which is fed from the E-Board to the Z-Board via connector Z4 pin 2. From connector Z4 pin 2, the right speaker audio signal is fed via de-coupling capacitor C2206, before being fed via the bass boost circuit, made up of capacitors C2207, C2208 and resistors R2213, R2210, R2211 and R2212.
At the same time the left microphone signal input via connector Z5 pin 2, is fed to IC2221 pin 2 via C2221 and R2221. The signal is buffered and output from pin 1 of IC2221. Here the signal is split into two paths. The first sees the microphone signal being fed via a high-pass filter, consisting of capacitors C2231, C2232 and resistor R2224. The signal is then input via pin 5 to the emitter follower configured op-amp where the signal is buffered and output via pin 7 and resistor R2227. Here the signal is added to the signal from the second path fed via resistors R2235 and R2225. After this signal conditioning of the left microphone signal, which is required to ensure a stabilised negative feedback, the added signals are then fed to pin 9 of IC2221. Here this negative feedback of the microphone signal is applied to the left speaker audio signal, which is fed from the E-Board to the Z-Board via connector Z4 pin 1. From connector Z4 pin 1, the left speaker audio signal is fed via de-coupling capacitor C2226, before being fed via a bass boost circuit in the form of an RC network, made up of the following components: capacitors C2227, C2228 and resistors R2233, R2230, R2231 and R2232.
From this RC network, the right audio speaker signal is input via pin 10 of IC2201. Here the feedback microphone signal input at pin 9 and the right speaker audio signal input at pin 10 are combined. The flat frequency response of the audio signal is output from pin 8 of IC2201. This audio output from pin 8 of IC2201 is then fed to pin 6 of connector Z4, where the audio signal is fed back to the E-Board via connector E10. Once the right speaker audio signal is on the E-Board, the signal is fed to the audio output IC IC251.
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3.1.1. Microphone ON/OFF Control
to the Z-Board via connectors M7 and Z3 pin 1. Once on the Z-Board the control line is fed to the base of two muting transistors Q2201 and Q2202. Transistor Q2201 being used to mute the right microphone audio signal and Q2202 muting the left.
This control is used for models which do not have a seperate headphone output path fed from the MSP IC2101, this results in the headphone terminal being in series with the loudspeakers. This configuration means that when headphones are connected the loudspeakers are disconnected. This control line is used to mute the microphone input signal to IC2201, IC2221 when the headphones are used, which as just mentioned disconnects the loudspeakers. If the microphone input signal was not muted when the headphones were connected, the microphones would feedback external sounds from the surrounding area, which would then be reproduced in the headphones, mixing with the user selected audio signal.
Where the headphone terminal is not in use the control line is LOW biasing the muting transistors Q2201, Q2202 OFF, allowing the microphone signal to be input to IC2201 and IC2221, where the processing discussed in the previous section takes place. When headphones are connected the control line fed to the muting transistors Q2201, Q2202 goes HIGH. This high level fed via resistor R2246, results in the muting transistors being biased ON, pulling the microphone input signals to IC2201, IC2221 to ground, preventing the microphone audio signal being passed to the headphones.
The microphone ON/OFF control is fed from the headphone terminal (located on the M-Board) and fed
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Chapter 4.
1
Common Circuits
AF Audio Output
Both amplitude controlled audio signals output from pins 24 and 25 of IC2101 of the MSP are fed to the base of transistors Q2102 and Q2103. These transistors being used for impedance matching in order that the interference on the audio lines between the MSP IC2101 and the subsequent audio stages is kept at a minimum.
The usual negative feedback occurs from pin 11 to pin 1 and from pin 7 to pin 6 of the I.C. via the R/C network R252, C254 and R258 and C259. The diodes at pins 2 and 5 D254 and D253 provide protection for the output I.C. against any voltage spikes by clamping the input pins. The output I.C. is fed with a voltage of +29V to pin 10 of IC251.
The audio signals fed via transistors Q2102, Q2103 are then fed to connector E10 pins 1 and 2. Here the audio signals are then fed to the Z-Board via connector Z4 pins 1 and 2 where Acoustic Feedback (AFB) processing takes place, as described in chapter 1 section 3. After AFB processing the audio signals are then fed via connectors Z4 / E10 pins 5 and 6.
4.1. AF Audio Mute The AF audio mute circuit located at the inputs of the audio output IC IC251 consists of two transistors Q251 and Q252 which is controlled by transistor Q2101. Transistor Q2101 being used to prevent POP during switch ON and OFF times. At switch ON and OFF times the audio signals are muted to prevent POP. The mute control is generated by transistor Q2101 (located on the E-Board), its operation being discussed in section 10.1 of the EURO 4 Technical Guide.
The audio signals once on the E-Board are then fed to the audio output stage via C266, R261 and C257 for the right hand signal and C263, R256, C253 for the left. These capacitors may be charged up very quickly as all control processes (volume, balance) together with the base band switch over are processed in the MSP IC2101.
During the ON and OFF periods the mute control signal is fed to the base of both transistors Q251 and Q252. The mute control line during the ON / OFF periods is of a HIGH level which causes both transistors Q251 / Q252 into conduction, muting the left and right audio signals by pulling them to ground.
Both audio signals are fed to pins 2 and 5 of the output I.C. IC251. From here they are amplified and output via pins 7 and 11. From here they are fed via the headphone terminal to connectors E6 and E7 to the internal speakers.
Audio Left Out Audio Right Out
Audio Right In
Audio Left In Switch ON Mute
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Chapter
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1.
Control and Teletext Processing
1.1.
Control Processing
EURO 4 Supplement
supply falls to approximately 4.8V the reset IC IC1105 inputs a reset pulse via pin 54 of the microprocessor IC1101.
The following section only highlights changes in control processing which have occurred with the introduction of new models into the EURO 4 line up, and should be used in-conjunction with the EURO 4 technical guide.
: Pin 71 - VProt This input is used to detect a fault in the deflection circuit. This is achieved by using the vertical synchronisation signal which is fed to the microprocessor IC1101 pin 47, via transistor Q1108. This signal is also fed via diode D453 where capacitor C455 is charged. The charge held by capacitor C455 results in a HIGH level being applied to the base of transistor Q451, which ensures that the transistor is switched OFF. When transistor Q451 is switched OFF a HIGH level is applied to pin 71 of the microprocessor IC1101, fed via resistor R457. This HIGH level ensures that the safety input of the microprocessor IC1101 is in-operative.
The Microprocessor IC1101 used on the EURO 4 chassis is the SDA5450 which performs the same processing tasks as under taken by the microprocessor used on the first generation EURO 4. This includes not only control processing but teletext processing too. Listed below is those changes: 1.1.1. Input Control : Pin 54 - Reset In This input terminal is used as a power OFF reset by the microprocessor IC1101 when the TV is switched into standby. Without this power OFF reset the microprocessor IC1101 has no way of knowing the operational condition of the TV. When the TV is switched OFF the operational data from the digital processing ICs is lost. This means that at switch ON this data has to be reloaded. To be able to do this the microprocessor IC1101, has to be reset so that at switch ON from standby the operational data is reload into the digital processing ICs. This is achieved with reset IC IC1105, which monitors the 5V supply line via pin 2. When the 5V
Where an error occurs resulting in there being no vertical synchronisation signal being fedback to transistor Q451, capacitor C455 discharges via R458 resulting in transistor Q451 conducting. This results in pin 71 of the microprocessor IC1101 being pulled LOW and the TV switching into standby after a short delay. : Pin 74 - RC The users commands for control of the TV receiver are applied via the remote control. These commands from the remote control transmitter are applied via the remote control receiver to pin 74 of IC1101, this command data being in serial format.
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Chapter
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EURO 4 Supplement LOW by Q1101 which is conducting at this point due to the 5V standby supply fed to the base of Q1101 via R1112. Once the supply voltages have become established pin 53 of the microprocessor IC1101 pulls the base of Q1101 LOW resulting in it switching OFF. A HIGH level is then fed via R1111 to the digital ICs initiating their start-up.
1.1.2. Output Control : Pin 45 - 4:3 RGB The 4:3 RGB control output from the microprocessor is used to support the display of an RGB picture on wide screen TV’s. This is achieved by mechanical means as opposed software by transistor Q580 and relay RL580. The 4:3 RGB control line being used to control transistor Q580 responsible for controlling the horizontal aspect ratio. Where the aspect ratio of the picture is reduced to a 4:3 display the operating voltage to the DAF circuit located on the W-Board has to be reduced too, ensuring that the DAF correction signal is also reduced to match the active picture scan ensuring optimum picture conditions as described in chapter 2 section 2.
: Pin 79 - Chroma Switch (M-Board Only) The chroma switch control output from pin 79 of the microprocessor IC1101 is used to control the switching transistors Q3202, Q3204 located on the M-Board. This control line being used to select between the chroma signals input from the S-VHS inputs of AV3 and AV2. : Pin 81 - LED The standby LED is controlled via pin 81 of the microprocessor IC1101, which when In standby mode causes the standby LED to light up. Pin 81 is also used to flash the standby LED when the Infra-red remote control receiver receives a signal from the remote control.
: Pin 53 - Reset Out To ensure correct operation of the digital ICs, they must be started at a specific time in order to permit signal processing. This is achieved by the reset control line output from pin 53 of the microprocessor IC1101. During switch ON the digital ICs are held
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Chapter 2.
2
EURO 4 Supplement
Dynamic Automatic Focus (D.A.F.)
2.1. Introduction
connector E4 to the P-Board via connector P4. Once on the P-Board the signal splits into two paths.
Euro 4 wide screen models (PK1 and PK2) have an additional circuit provided, named Dynamic Automatic Focus (D.A.F.), this circuit is used to overcome the problems of poor focus at the outer edges of the picture which is normally associated with large screen CRT’s. By using this D.A.F. circuit, focus of the picture at the outer edges of the CRT are as sharp as the centre portions of the picture. To provide this feature an additional circuit located on the P-Board (TNP8EP016) is used (as shown on page 14). This circuit containing IC3901 is discussed in the following sections.
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The first path feeds the vertical pulse to the vertical deflection coil which is fed via connector P3.
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The second path feeds the vertical signal via the zener diode D3921 and transistor Q3917 where the signal is amplified and fed to IC3901 pin 15.
The horizontal pulse output from the horizontal output transistor Q551 is split into four paths. :
The first path feeds the horizontal pulse directly to pin 10 of the flyback transformer T551
:
The second path feeds the horizontal pulse directly to the horizontal deflection coil via connector E4 onto the P-Board via connector P4 to the horizontal deflection coil via connector P3.
To carry out D.A.F. processing a horizontal and vertical pulse are fed to IC3901.
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The third path feds a horizontal flyback pulse to the E-Board and to the video processing stage.
The vertical pulse is output from the vertical output IC IC451 pin 2 (LA7845) or pin 3 (LA7876), and fed to
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The fourth path finally feds the horizontal pulse to IC3901 pin 13 via amplifier transistor Q3901.
2.2. D.A.F. Processing
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P-Board DAF Circuit
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2.3. AN5422K (IC3901) The horizontal and vertical pulses as mentioned earlier are fed to IC3901 pins 13 and 15. Here a vertical and a horizontal drive pulse are produced and output via pins 3 and 21.
horizontal drive signal applied to the gate terminal of Q3905. At switch on Q3911 is biased into conduction by the rising 12V supply line which is fed via R3974 to the base of Q3911. With Q3911 biased on, the horizontal drive signal is grounded via the collector/emitter junction.
The horizontal pulse input via pin 13 is fed via a noise cancellation circuit and sync. separator stage whose reference is set via pin 11 by R3987/R3983 and C3939. The horizontal sync. pulse is then output via pin 10 and input via pin 9 of IC3901 to the AFC stage.
Q3911 remains biased on until the zener diode (D3915) break-over voltage is reached at this point capacitor C3938 begins to charge. Once C3938 is fully charged Q3912 switches on, removing the base bias from Q3911. Q3911 switches OFF and diode D3917 becomes reversed biased due to the HIGH level being fed via R3974. The horizontal drive signal is now fed to the FET transistor Q3905, this soft start allowing time for the supplies to the DAF stage to become established.
At the AFC stage the horizontal sync. pulse is compared with the horizontal flyback pulse input via pin 8. Here the phase is set by adjusting R3938. The horizontal pulse is then output via pin 7 and input via pin 6 to the horizontal oscillator stage (the adjustment for which can be set by R3922) before being fed via the horizontal driver stage and output via pin 3. After the horizontal drive signal is output from pin 3 at approximately 2.2Vpp the signal is fed via the complementary Darlington pair connected transistors Q3902, Q3904. The signal is then fed via the FET transistor Q3905 to T3901 pin 1 at approximately 250Vpp.
The vertical pulse which is input via pin 15 is fed via the vertical trigger stage before being passed onto the following vertical oscillator. The vertical oscillator is set via pin 16, while the timing of the oscillator is set via pin 18. From the oscillator stage the vertical pulse is fed to the vertical drive stage, the amplitude of the vertical pulse being set by R3927 / R3918 connected to pin 19.
The horizontal drive signal output from pin 3 IC3901 is also fed to transistors Q3911 and Q3912 which provides a soft start at switch by grounding the
The vertical pulse is then output via pin 21 synchronised by the vertical flyback pulse input via pin 22. This vertical signal is then fed to the base Q3903.
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Transistor Q3903 is then used to generate a parabola signal of approximately 5Vpp. This parabola waveform is then fed to the cascade connected transistors Q3907, Q3906. Here the signal is amplified to approximately 250Vpp before being fed to pin 4 of transformer T3901.
Here the signal is added to the focus voltage of T551, the focus voltage VF2 with the D.A.F. waveform signal which is then supplied to the focus terminal on the CRT. By this method the focus voltage for the central and outer edges of the scan undergo alteration. This results in the focus voltage for the outer edges being reduced compared with that of the central area of the screen, thus increasing the focusing distance of the beam and enhancing focus at the outer edges.
The D.A.F. transformer T3901 then combines both the horizontal sync pulse mentioned earlier with the vertical parabola waveform. This combined signal is then output via the HV terminal to the D.A.F. input terminal of the FBT T551 located on the E-Board.
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EURO 4 Supplement
2.3.1. RGB 4:3 Mode
Q580 and pin 45 of the microprocessor IC1101, which pulls the base of Q580 LOW. This results in the transistor switching OFF and the relay contact opening. When the contact of relay RL580 is open, the path the horizontal signal follows changes. This sees the horizontal signal being fed from the horizontal scan coil back to connector P3 pin 1 (as mentioned earlier) and fed via capacitor C586, the relay contact and coil L585. The relay contact short circuiting L580, R580 and C580. The horizontal signal is again finally fed via coils L581, L584 and L582 back to the E-Board and the FBT.
On those models which use the VDP IC601 located on the E-Board, an additional circuit is required. This additional circuit is used to support the display of RGB in 4:3 mode. Where a normal composite or S-VHS signal is processed and displayed on screen, horizontal compression and expansion takes place in the horizontal scaler stage within the VDP. However the RGB signal which is also fed to and processed by the VDP is inserted after the VDP’s horizontal scaler stage, meaning that no horizontal compression can take place. To over come this problem, located on the P-Board (page 14) is, a relay RL580.
During these periods of 4:3 display the 150V supply voltage to the DAF circuit is also reduced. This is achieved by the circuit consisting of transistor Q3922, Q3923 and opto-isolator D3922.
Where a normal wide screen display is processed the the horizontal drive signal is fed from the line output transistor Q551, via connector E4 to the P-Board and connector P4. Here the horizontal drive signal is output to the horizontal scan coil connected to connector P3 pin 4 and fedback to the P-Board via connector P3 pin 1. The horizontal signal is then fed via an L/C/R circuit made up of coil L580, resistor R580 and capacitor C580, from here the signal is fed via the relay contact of RL580, controlled by transistor Q580 and pin 45 of the microprocessor IC1101.
When a normal wide screen display is processed transistor Q3922 is biased into conduction via a pull-up resistor R1180 (located on the E-board) mentioned earlier, this HIGH level being fed via connectors E9, P9 pin 3. When Q3922 is biased into conduction its collector goes LOW removing any bias to the diode junction of the opto-isolator D3922. With D3922 OFF transistor Q3923 is also switched OFF. The supply voltage of 150V to the DAF circuit is thus fed via resistor R3901.
In normal wide screen display transistor Q580 is biased into conduction, via a pull-up resistor R1180 (located on the E-Board). This results in current flow being fed via R589 (connected to the 15V supply line), the relay winding and the collector-emitter junction of transistor Q580. This current flow via the relay winding of RL580 results in the switch closing, short circuiting coil L585 and resistors R584 and R585. The horizontal signal is then finally fed via coils L581, L584 and L582 back to the E-Board and the FlyBack Transformer (FBT) T551.
When an RGB 4:3 display is being processed the base of transistor Q3922 is pulled LOW by pin 45 of the microprocessor IC1101. With transistor Q3922 switched OFF the opto-isolator D3922 is biased into conduction by a HIGH level fed via resistor R3902 fed from the 15V supply line. This results in transistor Q3923 also being biased into conduction by a HIGH level fed via the collector-emitter junction of D3922. With transistor Q3923 now conducting this series regulator configured transistor reduces the supply to the DAF circuit to approximately 90V. By reducing the supply voltage to the DAF circuit the DAF signal is also reduced, ensuring optimum picture conditions as described in chapter 2 section 2.
However when an RGB signal is input and displayed in 4:3 format the relay contact of RL580 is opened. This is achieved again under the control of transistor
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Chapter
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1.
Control and Teletext Processing
1.1.
Control Processing
EURO 4H Supplement
2.
The following section covers the control processing stage of the new 100Hz Euro 4 chassis which has been introduced into the EURO 4 line up. The Microprocessor IC1101 used on the EURO 4 chassis is the SDA5450 which performs the same processing tasks as under taken by the microprocessor used on the first generation EURO 4. This includes not only control processing but teletext processing too.
The internal TV signal selection is performed by the VPC IC1501 (located on the F-Board) which is controlled by the microprocessor via I2C Bus 1. By placing an AV turn on voltage at pin 8 of the 21 pin scart sockets, the relevant scart socket will be automatically selected. This turn on voltage fed from AV1 and AV2 pin 8 is fed to IC1101 pins 58 (AV1) and 59 (AV2) of the microprocessor.
Listed below is those changes: 1.1.1. Input Control
Pin 8 of AV1 and AV2 scart sockets are also used to allow IC1101 of the microprocessor to perform automatic picture ratio selection between 4:3 and 16:9 formats during AV operation. However, a pre-requirement for this would be for example, the provision of a video recorder able to process both picture formats. It has been established that during play-back recorders with a picture format of 4:3 supply an AV turn on voltage of 12V, and those with an aspect ratio of 16:9 provide a turn on voltage of 6V. These switching voltages fed from pin 8 of the 21 pin scart sockets are fed to the microprocessor pins 58 (AV1) and 59 (AV2) via the potential divider resistors R1131, R1128, and final R1127 to pin 59 for AV2 selection. AV1 selection is fed via resistors R1130, R1129 and R1126 to pin 58 of the microprocessor IC1101.
: Pin 54 - Reset In This input terminal is used as a power OFF reset by the microprocessor IC1101 when the TV is switched into standby. Without this power OFF reset the microprocessor IC1101 has no way of knowing the operational condition of the TV. When the TV is switched OFF the operational data from the digital processing ICs is lost, this means that at switch ON this data has to be reloaded. To be able to do this the microprocessor IC1101, has to be reset so that at switch ON from standby the operational data is reload into the digital processing ICs. This is achieved with reset IC IC1105, which monitors the 5V supply line via pin 2. When the 5V supply falls to approximately 4.8V the reset IC IC1105 inputs a reset pulse via pin 54 of the microprocessor IC1101.
The table shown below shows the required voltages for aspect ratio selection.
: Pin 58 - Slow1 / Pin 59 - Slow2 This circuit is designed so that it is possible to switch over to AV operation from all programme locations to the desired AV interface. The AV inputs being: 1.
AV2 21 pin scart socket also allows composite video input providing slow switching control via pin 8. AV2 also allows the input of an S-VHS signal as does AV3 (wide screen models only).
)XQFWLRQ
9ROWDJH 9
AV1 21 pin scart socket allows composite video and RGB signal input. Slow switching being provide via pin 8 for composite video input.
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: Pin 71 - VProt This input is used to detect a fault in the deflection circuit. This is achieved by using the vertical synchronisation signal which is fed to the microprocessor IC1101 pin 47, via transistor Q1108. This signal is also fed via diode D453 where capacitor C455 is charged. The charge held by capacitor C455 results in a HIGH level being applied to the base of transistor Q451, which ensures that the transistor is switched OFF. When transistor Q451 is switched OFF a HIGH level is applied to pin 71 of the microprocessor IC1101, fed via resistor R457. This HIGH level ensures that the saftey input of the microprocessor IC1101 is in-operative.
output amplifiers in this I.C. to a greater or lesser extent, thereby limiting the beam current. Where the control limit is exceeded, and the amplifiers have been completely reversed (which may lead to an error in the RGB final outputs or there voltage supply), defects in the CRT may result if no protective measures are taken. In order to avoid this, zener diode D511 is incorporated into the circuit. During normal operation the zener diode D511 is non-conducting and Pin 75 of the microprocessor IC1101 is held High via resistor R1149. In this state the protection circuit does not operate. Where an error described arises and the beam current continues to rise then the zener diode D511 conducts due to the negative voltage fed back from T551 (Flyback transformer), which causes diode D609 to conduct pulling the anode of the zener diode D511 lower than its cathode. As its anode is pulled lower, its cathode becomes more positive. Once the zener diodes breakover voltage is reached pin 75 of microprocessor IC1101 is pulled LOW.
Where an error occurs resulting in there being no vertical synchronistaion signal being fedback to transistor Q451, capacitor C455 discharges via R458 resulting in transistor Q451 conducting. This results in pin 71 of the microprocessor IC1101 being pulled LOW and the TV switching into standby after a short delay. : Pin 74 - RC The users commands for control of the TV receiver are applied via the remote control. These commands from the remote control transmitter are applied via the remote control receiver to pin 74 of IC1101, this command data being in serial format.
Where upon, after a short delay the microprocessor IC1101 switches the TV into standby.
: Pin 75 - Prot1 The microprocessor IC1101 pin 75 which is normally held High via R1149 provides a protection input which is used to switch the TV into standby mode. The protection input has two hard wired protection circuits, these being:
1.
12V supply monitored via D863
2.
9V supply monitored via D864 (wide screen only)
3.
8V supply monitored via D865
4.
5V supply monitored via D866
:
:
Voltage supply lines protection
The Voltage supply lines are monitored for short circuit faults,the supply lines monitored are:
If a fault occurs resulting in one of the aforementioned supplies failing then the safety diode connected to that supply will conduct. This will result in the base of Q851 (which is switched OFF during no fault conditions) going low with respect to its emitter. In this condition Q851 would conduct biasing ON Q856, this would cause pin 75 of the microprocessor IC1101 to go LOW and the TV would shut down into standby.
ABL protection
During normal operation the beam current is measured, with the result being input via the sense input of the DDP IC1504 pin 17, the beam current limitation being carried out via software control. The results of this being used to back off the RGB
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EURO 4H Supplement not changed, the ICs controlled by the I2C bus have, these being:
1.1.2. Output Control : Pin 53 - Reset Out To ensure correct operation of the digital ICs, they must be started at a specific time in order to permit signal processing. This is achieved by the reset control line output from pin 53 of the microprocessor IC1101. During switch ON the digital ICs are held LOW by Q1101 which is conducting at this point due to the 5V standby supply fed to the base of Q1101 via R1112. Once the supply voltages have become established pin 53 of the microprocessor IC1101 pulls the base of Q1101 LOW resulting in it switching OFF. A HIGH level is then fed via R1111 to the digital ICs initiating their start-up.
The following are connected to I2C- bus 1: On the F-Board the VPC IC1501, CIP IC1502, SDA9401 IC1503, DDP IC1504 are responsble for the video and deflection processing for 100Hz models. The multi standard sound processor (MSP) IC2101. The tuner and I.F. stage The 21 pin AV1 socket pins 10 and 12 are fed the I2C-bus1 control line via the transistors Q3006 and Q3007. During service mode, therefore, the T.V. may be programmed with the aid of a remote control.
: Pin 79 - Chroma Switch (M-Board Only) The chroma switch control output from pin 79 of the microprocessor IC1101 is used to control the switching transistors Q3202, Q3204 located on the M-Board. This control line being used to select between the chroma signals input from the S-VHS inputs of AV3 and AV2.
For those models with Dolby Pro Logic, the Dolby Pro Logic processing IC DPL3520 IC2401 is controlled directly by the microprocessor via I2C-bus1. The following are connected to I2C- bus 2 : The EAROM IC1102 is the only IC connected to I2Cbus 2, which contains system data, programme locations and specific tuning values, normal levels etc.
: Pin 81 - LED The standby LED is controlled via pin 81 of the microprocessor IC1101. In standby mode pin 81 is set to HIGH level which causes Q1052 (Q1062 M-Board) to switch ON causing the standby LED to light up. Pin 81 is also used to flash the standby LED when the Infra-red remote control receiver receives a signal from the remote control.
1.2.
General Teletext processing as discussed in the EURO 4 Technical Guide has not changed, however on the EURO 4H with the deletion of the VDP and the addition of the F-Board the output path has changed.
1.1.3. I2C Bus :
Teletext Processing
This sees the RGB signal being output from the microprocessor IC1101 via pins 37 (R), 38 (G) and 39 (B) accompanied by a blanking pulse output via pin 40. These signals are then fed to the VPC IC1501 (located on the F-Board) via connectors E70 to F1, where the RGB signals are processed as discussed in chapter 3 section 2.2.
Pin48,49-SCL1,SDA1 / Pin 50, 51-SCL2, SDA2
The I2C bus is generated by the microprocessor, with data line SDA1 being output via pin 49 and SDA2 output via pin 51, while the required clock lines SCL1 and SCL2 are output from pins 48 and 50 consecutively. While the operation of the I2C bus has
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F-Board Processing
On EURO 4H models the VDP processor IC601 located on the E-Board has been replaced by an F-Board. The F-Board contains 4 video processing ICs, used used to perform a number of functions. :
50/60Hz to 100/120Hz up conversion for flicker free picture processing and display
:
Automatic letter box detection for wide screen transmissions
: 2.1. :
chrominance before the signals are processed by the internal comb filter and colour decoder. :
:
Processor
Processor IC1502
SDA9401 (IC1503)
The SDA9401 on the F-Board provides up-conversion, vertical zooming, PNR and Automatic Letter Box Detection (ABLD).
I.C. Overview Video
Interface
This CIP IC is used to convert the analogue RGB and fast blanking signals to digital and to perform signal selection.
Picture zooming and compression.
Comb Filter (VPC3215)
Component (CIP3250)
:
IC1501
Display and Deflection Processor (DDP3310) IC1504
The DDP is used to provide horizontal scaling, deflection processing and RGB processing as well as converting digital YUV to analogue RGB for display.
This device converts analogue luminance and chrominance signals to digital luminance and
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Comb Filter Video Processor VPC3215C
The VPC3215C is a high quality, single chip video front end device providing the following features:
:
Pin 61 (Vin2) is the input for a composite video signal input via AV1.
:
Digital video processing
:
:
High performance adaptive comb filter
Pin 62 (Vin1) is the composite video signal which is fed from the tuner stage.
:
Multi-standard colour decoder
:
:
Composite video and S-VHS inputs
:
I2C bus
Pin 63 (Cin) allows the input of a chrominance signal which is input via the scart terminal of AV2 pin 15 or the 4 pin terminal of AV3 when an S-VHS signal is input.
:
20.25MHz crystal
These video / luminance and chrominance signals are then fed to the internal analogue frontend which is the first processing stage of the VPC.
2.2.1. Video Signal Processing To perform video signal processing a number of video signals are fed from the E-Board to the F-Board via connector F1 and to the VPC3215C IC1501, where 5 analogue inputs are available for the following video signals. :
Pin 58 (Vin4) is fed a composite video signal from the RCA terminals of AV3 or the luminance signal of an S-VHS signal input via the 4 pin S-VHS terminal again of AV3.
:
Pin 60 (Vin3) allows the input of a composite video signal fed from the scart terminal AV2 pin 20, or in the case of an S-VHS signal input via AV2 the luminance signal.
In this first processing stage the signals are fed to an internal muxtiplexer were the signal or signals are selected for further processing, before being clamped and converted to digital by the A/D converters at a clock rate of 20.25Mhz. The digital video / luminance signal and chrominance signals are then output from the A/D converter as 8 bits of digital information, and fed to the Adaptive comb filter also incorporated in the VPC IC1501. The 20.25Mhz crystal X1501 which is connected to the VPC IC1501 at pins 5 and 6 is used to provide all the necessary clock frequencies required by the VPC IC1501.
CIN VIN1 VIN2 VIN3 VIN4 VOUT
Analogue Frontend
Adaptive Comb filter
AGC 2*8bit ADC
Colour Decoder PAL NTSC SECAM
Horizontal Scaler Output Formatter Panorama Mode
Clock
VPC3215C 20.25MHz Clock Gen. DCO
YUV
2 I C
Sync. Processing
H/V
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2.2.2. Adaptive Comb Filter
is intended for S-VHS wide bandwidth chrominance. If the adaptive comb filter of the VPC3215C IC1501 is used for luminance chrominance separation, the colour decoder uses the S-VHS processing mode. The output of the colour decoder is YCrCb in a 4:2:2 format.
The digital CVBS signal fed from the previous front-end stage is fed to the 4H adaptive comb filter stage which is used to produce high-quality luminance/chrominance separation for PAL or NTSC signals. The comb filter improves the luminance resolution by allowing the full 5MHz bandwidth to be processed even during colour transmissions. Without the use of a comb filter, the luminance resolution is limited to about 3.8MHz.
2.3.
Scaler Stage
The luminance and chrominance signals output from the colour decoder are fed to the following scaler and Skew filter stages.
Where an S-VHS signal or SECAM signal are input then the comb filter is switched off. In this case the signals are fed via the delay lines directly to the colour decoder stage. This also applies where the comb filter is switched off via software control.
2.3.1. Skew Filter
In the colour decoder stage standard luminance and chrominance separation and multi-standard colour demodulation is carried out. The colour demodulator uses an asynchronous clock, thus allowing unified architecture for all colour standards.
The skew filter is used to ensure that the signal being processed is at the same timing as the system clock. As there is no way for the VPC IC1501 to know whether the signal that it is processing is a standard signal or a non-standard signal, e.g. VCR input, the system clock is free running. The skew filter which is controlled by an internal Horizontal Phase Lock Loop1 (PLL1), produces a phase shift which ensures that the system clock and source signal are at the same timing.
The colour decoder also provides some special modes such as wide band chrominance format which
The luminance and chrominance signals are then fed to the Horizontal scaler.
2.2.3. Colour Decoder
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2.3.2. Horizontal Scaler
The VPC3215 IC1501 supports this feature using a letterbox detector. The detector is used to detect black video lines by measuring the signal amplitude during active video. For every field the number of black lines are measured, compared to the previous measurement and the result is stored in the I2C register BLKLIN. To adjust the picture amplitude the external controller reads this register, calculates the vertical scaling co-efficients (vertical sawtooth parameters, horizontal scaling etc.) and transfers the new settings to the VPC IC1501.
The horizontal scaler which is fed the 4:2:2 YCrCb signal from the previously discussed stage is used to convert the YCrCb signals from 20.25MHz to a Line Locked output Clock (LLC) of 13.5MHz, under the control of the internal fast processor. This conversion of the output clock frequency to 13.5MHz allows the support of the 100Hz system. This up-conversion taking place in IC1503 discussed in chapter 3 section 2.5. After the above conversion process has taken place the YCrCb signals are then fed to the following Black Line Detector stage.
The letterbox signals containing logos on the left and right side of the black areas are processed as black lines, while subtitles inserted in the black areas are processed as non-black lines. Therefore the subtitles are visible on the screen. Dark video scenes with a low contrast level compared to the letterbox area are indicated by a BLKPIC bit.
2.3.3. Black-Line Detector When a letterbox format signal is processed black areas at the top and bottom of the picture are visible. To over come this the picture is either zoomed or shifted.
Scaler Stage
Luma From Colour Decoder
Skew Filter
Horizontal Scaler
Chroma
BlackLine Detector
Luma To Display Processor Chroma
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2.3.4. Output Formatter
frequency is programmed by an internal Fast Processor (FP).
The final processing stage of the VPC for the luminance and chrominance signals is the formatter stage here the signals are output from the VPC via pins 20-25 / 28-29 for luma and 38-43 / 46-47 for chroma in 4:2:2 format at 20.25MHz, synchronised by the horizontal and vertical sync. signals output from pins 12 and 14. Accompanying these vertical and horizontal synchronisation signals is the active video out (AVO) signal fed via pin 17 of the VPC IC1501, which is fed to IC1502 where it is used to signal the active video signal data output from IC1501.
2.3.6. Control In addition to those signals mentioned above the VPC also provides the following clock frequencies. :
LLC2 pin 18 - provides a 27Mhz clock which is produced by the internal rate multiplier used to synthesize the clock frequency of 27MHz used as the system clock for the support of the 100Hz system.
:
LLC1 pin 19 - provides a 13.5Mhz clock which is used as the system clock for support of the 50Hz system.
2.3.5. Synchronisation Processing Synchronisation is provided by the Sync. Processing stage, the sync. information extracted from the video/luma signal being distributed internally to the rest of the video processing system. Most of the processing that runs at the horizontal
Control of the VPC is performed microprocessor IC1101 via I2C bus 2.
26
:
Serial data line SDA pin 55.
:
Serial clock line SCL pin 56.
by
the
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CIP3250A (IC1502)
The CIP IC IC1502 contains the entire circuitry required to interface analogue YUV and RGB signals to a digital YUV signal. The fast blanking signal is used to control internal switching between the digitised luminance and chrominance signals and external RGB signals.
and 36-43 (chroma). The first stage these signals are fed is the format conversion stage used to convert the input signal format of 4:2:2 to 4:4:4 format for internal processing. From this stage, this signal is also fed to the mixer stage.
The external RGB and fast blanking signal fed from the 21 pin scart socket, (AV1 located on the E-Board), is fed to the F-Board via connector F1 to the input of the CIP IC IC1502. Here the RGB signal is input via pins 63 (B), 65 (G) and 67 (R), with the fast blanking pulse being input via pin 61. These signals are then fed to an internal A/D converter, digitising the input signals. The digitised RGB signals are then fed to a matrix stage which converts the digital RGB signals to digital YUV. These digitised YUV signals then undergo signal correction for brightness, contrast, saturation and hue as well as being converted to 4:4:4 signal format before being fed to a mixer stage.
The mixer stage is used to select between the digital YUV signal fed from the VPC IC1501 and the digitised YUV signal produced from the RGB signal input to the CIP, IC1502 (discussed earlier), this mixer stage being controlled by the fast blanking pulse input via pin 61. The selected YUV signal is then fed via the LPF to the output format conversion stage. Here the signal format of 4:4:4 used for internal processing is converted to 4:2:2 format. The resultant digital luminance signal is then output via pins 10-17, while the digital chrominance signal is output via pins 20-27. Both these signals are then fed to IC1503 (SDA9401) for up-conversion.
The digitised luminance and chrominance signals fed from IC1501 are input to IC1502 via pins 44-51 (luma)
To aid in the processing of the signals just discussed the following signals are also reguired.
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2.4.1. Pin Information
:
:
This is the serial data input which is part of the I2C bus 1 control line.
AVO - pin 29
Input from the VPC IC1501 is the AVO signal which is used to synchronise the active video signal. :
:
CLK - pin 54
This input provides a 13.5MHz clock which provides synchronisation and timing of the chrominance and luminance signals in IC1502.
HS - pin 30
Horizontal synchronisation signal input from the VPC IC1501 which is used for synchronisation of internal processing. :
SDA pin 32
:
RSTN - pin 55
The reset input which is an active LOW input, is used to ensure correct operation after a power on. This is acheived by keeping the CIP IC in a stable condition during this period.
SCL - pin 31
This is the serial clock input which is part of the I2C bus 1 control line.
YUV 4:2:2 36-51
CIP3250 Format Conversion 4:4:4
67
R G B FBL
65
ADC
63
Matrix (on/off)
CT BR SAT
Soft Mixer
Adjustable LPF
Format Conversion 10-17 20-27
4:4:4
61
2
CLK
YUV 4:2:2
54
I C Interface
Clock Buffer
28
31 32
2
I C Bus
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SDA9401 (IC1503)
The SDA9400 and SDA9401 are model dependent, they are both used as a 100Hz high end solution for digital TV, which offer the features listed below. However the SDA9400 uses frame based processing, as opposed to field based processing performed by SDA9401. The SDA9400 used on wide screen models produces a sharper picture in the horizontal direction than the SDA9401, which is used on 4:3 models, where horizontal zooming is not as critical.
:
Digital vertical zooming
:
Digital vertical panning
:
Digital colour transient improvement
:
Digital luminance peaking
:
Motion adaptive temporal and spatial noise reduction
:
Still picture
:
Large area flicker reduction
:
100 / 120 Hz interlaced scan
:
Line flicker reduction
:
16:9 compatible
Hin 23 Vin 22
ISC Input Sync. Controller
Syncen 29
MC Memory Controller
61 60
OSC Output Sync. Controller
Vout Hout
62
Href
SDA9400 LDR Low Data Rate Processing 43-50 IFC Input Format Conversion
Yin UVin
ED eDRAM
Vertical Horizontal Decimation
Data Buffer
Noise Reduction and Measurement
Interfaces
Motion Detector
31-34 37-40
I2 C Bus Interface
Vertical Interpolation
OFC Output Format Conversion
20
YOUT UVOUT
10-17
CLK Out PLL1 Clock Doubling LM Line Memory 54
SCL
1,3-7 63, 64
26
LM Line Memory
SDA
Scan Rate Conversion
Movie Mode and Phase Detection
Reset 30
21
HDR High Data Rate Processing
CLK1
29
PLL2 Clock Doubling
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2.5.1. Operation
with the luminance signal being output from pins 1, 3-7, 63 and 64, while the chrominance signals are output via pins 10-17. Here both the luminance and chrominance signals are fed to IC1504, the final processing IC on the F-Board.
The selected digitised luminance and chrominance signals output from IC1502 via pins 10-17 (luma) and pins 20-27 (chroma) are fed to the input of IC1503. Here the luminance signal is input via pins 43-50 and the chrominance input via pins 31-34 and 37-40. These signals input to IC1503 being synchronised by the vertical synchronisation pulse input pin 22, horizontal synchronisation pulse input pin 23 and the 13.5MHz system clock signal input via pin 29. This system clock of 13.5MHz also provides the memory controller with a write clock, which is required when writing the luminance and chrominance data into the internal memory.
To achieve the processing carried out by IC1503 the following signals are also required. 2.5.2. Input Signals :
SCL - pin 20
This is the serial clock input which is part of the I2C bus 1 control line. :
SDA - pin 21
These luminance and chrominance signals are then processed by the Low Data Rate (LDR) processing stage for:
This is the serial data input which is part of the I2C bus 1 control line.
:
Noise reduction
:
:
Vertical compression
:
Horizontal compression
:
Motion detection
:
Movie mode detection
Reset - pin 30
The reset input which is an active LOW input, is used to ensure correct operation after a power on. This is achieved by keeping IC1503 in a stable condition during this period. 2.5.3. Output Signals
After undergoing this processing the luminance and chrominance signals are then up-converted for 100 / 120Hz display by the High Data Rate (HDR) processing stage. This up-conversion being achieved by reading out the luminance and chrominance data from the internal memory at twice the rate that the data was written into memory. To achieve this a 27MHz read clock is required by the memory controller, this 27MHz system clock signal for the 100 / 120Hz system being input via pin 54, is then used to read data out of the memory at the increased rate thus performing up-conversion. In addition to this up-conversion the internal memory and HDR stage also allow the display of a still picture.
:
CLKout - pin 26
This output provides the 27MHz clock signal which is fed to IC1504 and used as the system clock to support the processing of the up-converted luminance and chrominance signals. :
Hout - pin 60
Pin 60 of IC1503 is used to provide a horizontal synchronisation signal used for further processing of the up-converted luminance and chrominace signals. :
Vout - pin 61
Output from pin 61 of IC1503 is a vertical synchronisation signal used for further processing of the up-converted luminance and chrominace signals.
These now up-converted luminance and chrominance signals are then output from IC1503,
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DDP3310B (IC1504) RGB Processing
The DDP3310 IC1504 is a single chip digital video deflection processor, designed for high quality back-end applications in 100Hz TV sets with 4:3 or 16:9 picture tubes.The IC contains the entire digital video and deflection processing stages which are as follows :
:
Programmable RGB matrix
:
Additional analogue RGB / fast blank inputs
:
Picture frame generator
Deflection Video Processing
:
High performance H/V deflection
:
Separate ADC for tube measurements
:
EHT compensation
Horizontal scaling
:
Panorama Vision
:
Dynamic peaking
:
Soft Limiter (gamma correction)
:
I2C Bus Interface
:
Colour transient improvement
:
Single 5V power supply
YC rCb 4:2:2
Miscellaneous
Contrast Peaking Brightness Soft Limiter Y Horizontal C Scaler
Clock Gen.
Analogue RGB switch Tube Control 3 x DAC (10 bit)
Digital RGB Matrix
53
67 68 SDA SCL
Scan velocity modulation output
:
43-50 54-61
27MHz Clock
:
External RGB Clamping Brightness Contrast
DTI Cr, Cb
Interpolator 4:4:4
Scan velocity modulation Picture Frame Generator
2
I C Measurement ADC
DDP3310
24, 25, 26 RGB Out 31, 32, 33 RGB In 30 FB In 23 SVM
8 Deflection Prcessing Stage
security unit
H Drive 19-20 V. Out 21 E/W Out
17
63 64 2H/2V
Sense
31
9 HFlyb.
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Display Processing Transient Improvement (DCTI). The DCTI stage is used to sharpen the chrominance rise time, which is achieved by applying a correction signal that is calculated by differentiating the colour difference signals. The amount of correction is limited automatically. The CrCb signals are then input to the matrix circuit where the luminance signal is added to the CrCb signals to produce a digital RGB signal.
The luminance and chrominance signals input to the DDP IC1504 are fed via pins 54-61 (luma) and pins 43-50 (chroma), synchronised by the horizontal and vertical synchronisation signals input via pins 63 and 64 respectivley. Here the 4:2:2 YCrCb signals on wide screen models are fed via the horizontal scaler. The horizontal scaler synchronised by the 27MHz clock signal input via pin 53 is responsible for the display of the active picture in a number of formats, these being: :
Just mode
:
4:3 mode
2.7.3. Tube Control Stage After the RGB signals are output from the matrix circuit, the signals are input to 3 multipliers which are used to digitally adjust the white drive. The digital RGB signals are then output as 10 bits of information. The same multipliers are also used to implement a software beam current control. The digitised RGB signals, along with the display and clock control data are then synchronised by the Horizontal flyback pulse input via pin 9 of the DDP, before the digitised RGB signals are fed to the Analogue Backend which is the final processing stage of the DDP.
Like the scaler stage of the VPC IC1501 discussed in chapter 3 section 2.2., the DDP scaler stage also contains a programmable decimation filter, a 1-line delay FIFO memory and a programmable interpolation filter. The controlling of the scaler being performed by the internal Fast Processor. After the Horizontal scaler the luminance and chrominance processing then splits into two paths.
Also included in the display processor stage of the DDP IC1504 is the picture frame generator, which is used when the picture does not fill the total area of the screen (height or width to small). In this case the area around the picture is surrounded with black bars, generated by the frame generator.
2.7.1. Luminance Processing The luminance signal passes via a number of control stages such as the contrast control stage and dynamic peaking circuit used to enhance the luminance signal. The luminance signal is then fed via a brightness adjustment and soft limiter circuit. The soft limiter circuit being used to prevent the CRT from being driven to hard due to high contrast and brightness levels, which in turn causes the beam current to increase resulting in the CRT overheating producing colouration. Once the signal has been output from the soft limiter the luma signal is fed to the matrix circuit for production of the RGB signal.
2.7.4. Scan Velocity Modulation The video RGB which is fed to the three multipliers is also fed to the Scan Velocity Modulator (SVM) circuit, here the RGB input signal is converted to a luminance (Y) signal which is carried out by a simple matrix. The analogue output signal is generated by an 8bit D/A converter where the SVM signal is output via pin 23 of the DDP IC1504. Here the SVM signal is fed via a transistor array which amplifies and buffers the signal. This operation being performed by transistors Q1504, Q1503 and Q1502 The SVM signal is then fed to the E-Board via connector F1 pin 9 where the signal is fed directly to the CRT drive stage located on the Y-Board.
2.7.2. Chrominance Processing In the chrominance processing path the CrCb signals are converted from 4:2:2 to 4:4:4 sampling rate. by the interpolator stage before undergoing Digital Colour
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RGB Switching Stage
The digital RGB signal fed from the Tube Control stage, is input to the RGB Switching Stage. Here the digital RGB signal is converted to analogue RGB, before being output from the DDP IC1504.
inserted into the main RGB signal path under the control of the fast blanking pulse. The control of white drive, brightness and contrast adjustments being carried out on the RGB signals, using the internal Fast processor (FP).
The digital RGB signal is converted to analogue using 3 digital to analogue converters (DAC), with 10 bit resolution, here an analogue brightness value is added to the RGB signal. The brightness value having an adjustment range of 40% of the full RGB range.
In the final stages, before the selected analogue RGB signal is output, cutoff and blanking values are added. Cut off is provided by three 9-bit D/A converters, with a cut off adjustment range of 60% of the full scale RGB range.
The backend also allows the insertion of external analogue RGB signals, which in this case is fed from the microprocessor, providing text and OSD information. The text/OSD information is input to the DDP IC1504 via pins 31 (R), 32 (G) and 33 (B) with the fast blanking pulse input via pin 30.
The RGB signals are then finally output via pins 24 (R), 25 (G), 26 (B), where all three signals are fed via a transistor array which amplifies and buffers the RGB signals. This operation for the Blue signal being performed by transistors Q1507, Q1506 and Q1505, for the Red Q1510, Q1509 and Q1508, while for the Green Q1513, Q1512 and Q1511 are used. The RGB signal is then fed to the E-Board via connector F1 pins 6 (G), 7 (B) and 8 (R) where they are then fed directly to the CRT drive stage located on the Y-Board.
The RGB signal is initially fed to a clamping circuit, where the signal is independently adjusted for brightness and contrast. The RGB signal is then
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CRT Measurement and Control
EHDP FXUUHQW $ 6HQVH 5 ' 0$'& 5 56: 5 56:
7XEH 0HDVXUHPHQW &XWRII :KLWH GULYH 3LFWXUH 0HDVXUHPHQW %HDP &XUUHQW
7XEH 0HDVXUHPHQW The DDP is also equipped with an A/D converter which is used to perform Tube and Picture measurement, this information being fed from the Y-Board via 3 transistors. These transistors depending upon the Y-Board being used.
During cut-off measurement the input range of the measuring A/D converter is set by resistor R603 (located on the E-Board). However as the white drive measurement contains alarger current range, resistor R1538 is also switched into the measurement A/D converter input along with R603 thus keeping the measured value in the range of the A/D converter.
For the Y-Board TNP8EY017 please refer to the EURO 4 Technical Guide (TZS8EL001).
This information then passes via the I2C bus to the microprocessor IC1101 which evaluates this data and compares the data set in the memory (during alignment adjustment) to continuously match the measured data.
The information fed from the Y-Board (TNP8EY018) is fed via transistors Q351, Q361 and Q371 to the sense input pin 17 of the DDP IC1504. The reference voltage for the measurement A/D converter being input via pin 29 also of the DDP IC1504.
These correction values again pass via the I2C bus to the fast processor in the DDP IC1504. Here the RGB output stages are corrected according to the values supplied, thus compensating for CRT and component aging.
2.9.1. Tube Measurement Tube measurement is carried out during vertical flyback, during this period two sets of measurements are gated back to the DDP IC1504 pin 17. The two sets of measurements taken during tube measurement being cut-off for the RGB systems and white drive for either of the R, G or B which are carried out sequentially.
2.9.2. Picture Measurement To ensure that the Picture Measurement is kept within the range of the A/D converter resistor R603 is used along with R1539.
The input range of the A/D converter is set between 0 - 1.5V which has to be switched to ensure that its input range is not exceeded. The input range of the A/D converter is dependant upon the measurement being taken and is controlled by pins 15 and 16 of the DDP IC1504.
This Picture Measurement which is fedback to the DDP IC1504 pin 17 sense input is used to perform Beam Current safety (discussed on page 30 of the Euro 4 Technical Guide under the heading ABL protection) which is software controlled.
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2.9.3. Deflection Processing
2.9.5. Control In addition to these signals mentioned above, the DDP also requires the following:
The deflection processing stage of the DDP IC1504 is used to generate the signals for the horizontal and vertical drive. Here the horizontal and vertical timings are synchronised by the incoming synchronisation signals, from which the east / west and vertical output signals are produced. The resultant east / west signal is then output from pin 21, while the vertical output is fed from pins 19 and 20 of IC1504. The horizontal drive pulse output from pin 8 of IC1504 is monitored by a security unit which with the aid of the external 5MHz crystal X1502 connected between pins 65 and 66 produces a reference clock signal which controls the Horizontial drive on and off time. During the power on stage and before the horizontal drive signal can be estabilished the security unit also generates a free running Horizontal drive signal divided down from the 5MHz reference clock. The horizontal drive signal output via pin 8 of IC1504 is then fed to connector F1 pin 16 where the drive signal is then fed to the E-Board and the horizontal output stage.
:
Reset In pin 39 is used during the switch ON period, to hold the DDP in a stable condition until the supply voltages have become established.
:
LLC2 pin 53 provides a 27MHz clock signal which is used as the system clock for support of the 100Hz system.
:
LLC1 pin 62 provides a 13.5MHz clock signal which is used as the system clock by the control processing stage.
:
SDA serial data line pin 67
:
SCL serial clock line pin 68
2.10. F-Board Supply Voltages To allow the IC’s on the F-Board to perform the processing that has just been discribed a number of supply voltages are required, these are: :
A 12V supply fed via connector F1 pin 18 and used to supply the perphial circuits.
:
The 5V supply fed to the F-Board via connector F1 pin 20 is used to supply periphal circuits of the F-Board, as well as the processing ICs.
:
In addition to the 5V supply required by the processing ICs of the F-Board, a 3.3V supply is also required by IC1502 and IC1503. This 3.3V supply is fed from the E-Board and IC855 which is fed a 5V supply input via pin 1. Output from pin 3 of IC855 is a stabilised 3.3V supply which is fed to connector E70 pin 19 on the E-Board and to connector F1 of the F-Board.
2.9.4. Protection Circuitry As well as all the functions just mentioned picture tube and drive stage protection is also provided. This is achieved through the following measures. 1.
Vertical protection safety input pin 11: This vertical protection input is used to prevent the picture tube from damage in the event of a malfunction of the vertical deflection stage. If the peak-to-peak sawtooth signal is to small the RGB output signals are blanked.
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COLOUR OUTPUT STAGE between connector Y5 pins 1 and 3), which is controlled directly via the collector terminals of transistors Q908, Q909 via resistor R929 which is coupled in parallel to the deflection winding.
The Y-Board (TNP8EY018), contains not only the colour output stage, but also scan velocity modulation stage. The RGB signals fed to the colour output stage are fed from the DDP IC1504 pins 24 (R out), 25 (G out), 26 (B out), here the RGB signals is fed from the F-Board via connector F1 pins 6, 7 and 8 to the E-Board via connector E70. On the E-Board the RGB signals is fed directly to connector E8 pins 3, 4 and 5 to the Y-Board via connector Y2. The RGB signals at this point being approximately 5Vpp.
3.2. CRT AMPLIFIER STAGE 3.2.1. Outline In order to avoid damage caused by long cathode lines and there by trim the frequency response, the RGB output stages have once again been mounted on the CRT board. Each colour channel has an IC with a signal bandwidth of > 10MHz guaranteeing high resolution even with rapid signal transitions in both directions. The circuits for the three colour channels being identical. The use of ICs means that the number of components in the output stages can be reduced to a minimum.
The velocity modulated (VM) signal which is a combined RGB signal, is output from the DDP IC1504 via pin 23 and is fed to the E-Board via connectors F1, E70 pin 9 and then directly to the Y-Board via connectors E8, Y2 pin 7.
3.1. Velocity Modulation circuit
The RGB signals mentioned earlier are fed via connector Y2 pins 3, 4, and 5 where the signals are fed to pin 3 of IC351, IC361, IC371 and then the inverting input of an operational amplifier via an R/C combination. The non-inverting input and thus the operating point is determined via pin 1. The negative feedback to determine the amplification factor is provided by the resistance between pin 9 and pin 3. The signals are output at approxromately 160Vpp maximum via pins 7 and 8 to drive the CRT cathodes. The actual drive signal being output from pin 8 and a correcting signal input via pin 7 is used in order to allow automatic dark current regulation.
The SVM signal which is fed via connector Y2 is fed to the base of transistor Q905, where with capacitor C906 and resistor R914 signal shaping occurs. The signal is then fed from here to two mirror image push pull output stages which are used to supply the required current to the velocity modulation coils. Transistors Q906 and Q907 are connected as impedance converters which control the output stage at low impedance without distortion. Transistors Q908 and Q909 then output the signal at approximately 35Vpp to the SVM coil, (connected
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Tube and Picture Measurement
3.4. BEAM CURRENT LIMITATION
Tube and Picture measurements are carried out by gating relevant information back via transistors Q351, Q361 and Q371 to the sense input, pin 17 of the DDP IC1504. These Tube and Picture measurements being discussed in detail in chapter 3 section 2.9. of the DDP. However below is a brief overview of Tube and Picture measurements.
The measurement of the beam current as mentioned in the previous section is fed via the Sense input of the DDP IC1504 pin 17, the result of the measurement being compared to the value stored in memory. The result of which is used to reduce the drive of the brightness A/D converters and if necessary the contrast A/D converters. However if the beam current fails to be reduced the the beam current safety circuit is used to switch off the T.V. This is achieved by the flyback transformer which works with virtual earthing, this basically means that as the beam current increases the base of the flyback transformer T551 becomes negative. If the beam current reaches the maximum control range of the FBT the zener diode D511 conducts, this causes pin 75 of the microprocessor IC1101 to go LOW resulting in the TV being switched in to standby (refer to page 20 of the microprocessor stage).
3.3.1. Tube Measurement The Tube measurements (cut-off control) as described in chapter 3 section 2.9. is basically a scan regulating circuit, which electronically regulates for dynamic tolerances and the effects of aging, of the C.R.T. etc. It also offers the following advantages: :
Automatic black level and white level tracking.
:
Prevention of colour falsification during the picture tube heating up time.
This eliminates the setting regulators which were once common, and the need for compensation.
3.5. ABL Stabilisation
During field flyback the leakage current from the CRT system is measured at ultra black before the cathode currents for the three systems (RGB) are measured. These measured values are then gated back via the previously mentioned transistors Q351, Q361 and Q371 to the DDP IC1504 pin 17.
This circuit which consists of Q552 and R564 (located on the E-Board) is used to keep the beam current at a constant level avoiding degradation in Focus and at the same time reducing blooming effects normally associated with increases in beam current. This circuit is arranged so that as the beam current increases transistor Q552 switches OFF, this means that resistor R564 is no longer in parallel with R562 / R563 thus reducing the above mentioned artifacts.
In addition to the above control, to also stabilise the cut-off control against voltage variations due to load, IC381 is used. If the 12V supply line were to vary due to load then the operating point of IC351, IC361, IC371 which is set via pin 1 would also vary altering the cut-off. The 12V supply is monitored via the R terminal of IC381, which is responsible for the conduction of the internal zener diode between the K and A terminals. If the voltage at the R terminal rises conduction of the zener diode increases maintaining a constant supply to pin 1 of the three output ICs. Likewise if the voltage at the R terminal of IC381 reduces then the conduction of the internal zener diode is reduced accordingly.
3.6.
Switch-off Spot Suppression
The switch-off after-glow flecks which would occur if the CRT charge could not be reduced quickly enough are suppressed by transistor Q3352. At switch-on and during operation Q3352 has no effect, since the base and emitter of Q3352 are at the same potential and so is non-conducting. At switch-off Q3352 is switched ON by a rapidly falling supply line. Diode D3351 becomes reversed biased due to the charge held in electrolytic capacitor C3351, this causes Q3352 to become conductive and so C3351 discharges via the emitter/collector junction of Q3352. This discharging capacitor C3351 causes diodes D3352 / D3353 / D3354 to conduct, forcing the colour output amplifiers of IC351 / IC361 / IC371 into saturation, discharging the CRT quickly preventing after-glow.
3.3.2. Picture Measurement During Picture Measurement, which is carried out during active picture scan, measurement of the active picture current is carried out, this data is then input via the sense terminal pin 17 of the DDP IC1504, where this information is used to provide software controlled beam current regulation.
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Y-Board Schematic
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AV2 Video Out Switching This newly combined video signal is then fed to the E-Board via connector E15 and is fed to pin 8 of IC601. The video signal is then output from pin 6 and fed to the video output, pin 19 of AV2. Likewise video out fed from the VPC pin 64 to the E-Board via connector E70 pin 25 is fed to connector E15 pin 6 where the video signal is input onto the M-Board. Here signal selection takes place as described in the EURO 4 Technical Guide section 18 of the M-Board processing stage. The video out signal is then fedback from the M-Board to the E-Board via connector E15 pin 8. This video signal is then input to pin 8 of IC601 and output via pin 6, where the video signal is fed to the video output, pin 19 AV2.
AV2 video out switching on EURO 4 is performed on the H-Board by IC3401. However with the introduction of the F-Board, used on 100Hz EURO 4 models, AV2 video switching is now performed by switching IC IC601 located on the E-Board, but which performs the same operation as IC3401 on the H-Board. This switching being used to feed video out to the AV2 scart socket. The signals fed to the switching IC IC601 are: : RF Video This signal is the video fed from the tuner to the AV video switching IC, IC601 pin 3. The RF video signal is then output via pin 6 of IC601 where the signal is then fed directly to the AV2 scart socket. : AV2 V-Out The signal selected for AV2 video out (V-Out) is input via pin 8 of IC601. Here the video signal is switched and output via pin 6 of IC601 and fed to AV2 video out of the 21 pin scart socket.
4.1.
Control
Control of this switching IC is performed by the MSP3410 IC2101 pin 4, although the switching control commands are fed from the microprocessor IC IC1101 via the I2C bus to the MSP3410 IC2101.
Those models however which have an additional S-VHS input is fed via AV3 located on the M-Board. Also performed on the M-Board is the combining of the luminance and chrominance signals to produce a video signal (which is described in the EURO 4 Technical Guide section 18 of the M-Processing Stage).
This switching control fed from the MSP3410 IC2101 pin 4 is fed to transistor Q601 where the signal is amplified and applied to the switching IC IC601 pin 5.
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Vertical Output Stage
5.1.
LA7876N
EURO 4H Supplement
During vertical sweep, the bootstrap capacitors C456 and C463 are charged up to almost supply voltage via D454 and D458. The output of the pump-up generators at pins 8, 9 and 10 of IC451 are at this moment ground potential.
On EURO 4H models the vertical output IC used is the LA7876 which is fed a drive pulse output from the DDP IC1504 pins 19 and 20 to the vertical output stage IC451 pins 5 and 6.
As a result of the DC displacement at the negative pole of capacitor C456, C463 (rising to the supply voltage), build up of the supply voltage for the output stage at pin 3 rises to almost 3 times the supply voltage. At the same time, D454, D458 are reverse biased and thus prevents discharge of C456, C463 into the supply line.
This vertical output IC IC451 consists of an operational amplifier to which the vertical drive pulse in the form of a sawtooth is passed, the results of which are output via pin 3. The gain of the internal op-amp. is controlled by the negative feedback pulse which is fed via R454 connected between pin 3 and pin 6. IC451 also contains two pump-up circuits which are used to provide a switching voltage for the vertical flyback period. This is required as the energy requirement of the vertical output stage is highest during flyback, as the electron beam has to be passed rapidly from the bottom right hand corner of the screen to the top left corner of the screen.
5.1.1. Vertical Protection The output pin, pin 3 of IC451 which is directly connected to the deflection coil is monitored by the protection input of the DDP IC1504. Here a vertical flyback pulse is fed to pin 11 of the DDP IC1504, which is used to signal a fault (as described in chapter 3 section 2.9.4. ). When a fault is detected the RGB signals are blanked preventing any damage of the CRT.
This brief additional energy requirement is met by increasing the supply voltage available to the output stage by 3 times the supply.
Vertical Drive
+14V
-14V
Vertical Flyback Pulse
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POWER SUPPLY
The supply voltages on the EURO 4D chassis are provided by two power supply circuits. The first of which being the main power supply located on the E-Board which uses the integrated circuit STR-F6654. The supply voltages produced by this main power supply being used to power normal TV operations as on the first generation EURO 4 chassis. The second power supply circuit (discussed in chapter 4 Section 2.) located on the W-Board uses the integrated circuit STR-F6653, this power supply being used to power the DVB decoder located on the V-Board.
At the standby transformer T802 the A.C. supply splits into three paths: : The first path sees the A.C. supply being fed to the normally open contact of the standby relay RL801. : The second path has the A.C. supply being fed via the windings P1/P2 of the standby transformer T802. : The Third path has the A.C. supply being fed to the degaussing circuit and the positive temperature co-efficient (PTC) resistor R802.
In-conjunction with the main power supply located on the E-Board just mentioned, a standby power supply is also used, however this standby power supply normally located on the E-Board is now situated on the W-Board. The benefits of using a standby power supply results in a reduction in power consumption when in standby mode.
1.1. Standby Power Supply Circuit The standby transformer T802 has the A.C. supply as just mentioned being fed via the primary winding P2/P1. From the output of the secondary windings S2/S1 of the standby transformer, a 7V supply is fed via resistor R860, where the supply takes two paths. 2. The first path that the standby supply follows is via capacitor C869 and rectifying diode D868, this supply is then smoothed by capacitor C870. This rectified and smoothed supply is then again split into two paths.
The mains A.C. voltage input via connector M10 of the M-Board is fed to the W-Board via the main TV ON/OFF switch S802 to connector M11. The A.C. voltage is then fed from the M-Board and connector M11 to the W-Board and connector W1, where the A.C. supply is fed to the standby transformer T802,.
+12V
5V Standby
From Pin 52 IC1101
From Q857 & D875 +B Protection
To RL4801 From W1
To W2
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The first path sees the supply voltage being fed via resistor R861 to the standby relay RL801 and the relay winding to the collector of transistor Q853. Transistor Q853 which is controlled by Q854, is responsible for switching the TV into and out of standby mode under the control of the microprocessor IC, IC1101 pin 52. When Q853 is switched ON current flows through the winding of the relay and collector / emitter junction of Q853. This current flow causes the relay contact to close feeding the mains supply to connector W2. The mains A.C. supply is then fed from connector W2 to the E-Board via E1 from where the A.C. supply is fed to the bridge rectifier D801 and the switched mode power supply IC IC801. A 12V supply is also fed from the main power supply via R863 and D871, this supply being used to reduce the load on the standby transformer when the TV is in normal operation.
3.
The second path the supply takes is via resistor R862 to the base of transistor Q852. This supply being regulated by the zener diode D873 which is used as a base bias.
The second path from the standby transformer T802, that the supply voltage follows is via the rectifying diode D867 and smoothing capacitor C871. Here the supply is applied to the collector of Q852. From the emitter of Q852 a 5V standby supply is fed to the Microprocessor IC1101, the EPROM IC1102, the EAROM IC1103 and AV Link circuit consisting of transistors Q1104 Q1107. This supply allows these circuits to operate during standby which is required to process the switch ON command from the remote control or local keys, allowing the TV to be switched out of standby, or to also process AV Link commands.
The 5V standby supply is also fed to connector W4 where the standby supply is then fed to the V-Board via connector V15 and to the ON Digital decoder stage.
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1.2. Flyback Converter Power Supply The STR-F6654 is a hybrid IC with built-in MOS-FET and control IC as well as a separate oscillation circuit.
1.2.1.
It features a small SIP (Single In-line Package) with isolated body (no bush and micra isolator required) and requires only a small number of external components.
The mains A.C. voltage which flows via the standby relay, is then fed via connector W2 to the connector E1 located on the E-Board as mentioned earlier. Once the A.C. supply is input onto the E-Board, the supply is fed via the bridge rectifier D801 and transformer T801 primary windings P1/P2 to pin 3 of IC801 and the drain terminal of the internal MOS-FET transistor.
Quasi-resonant operation is used to improve the switching efficiency, which with altered operation in standby mode allows the supply to fulfil both power-on and standby roles. The IC features pulse-by-pulse overcurrent protection, over-voltage protection (with latch) and thermal protection functions.
General
As there is no gate control voltage at this time the operating voltage is not subjected to any load.
To W2
+B
To pin 2 IC850
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1.3. Start Up Circuitry The start-up circuit, consisting of resistors R805 and R814, is used to start and stop operations of the control IC IC801, this is achieved by detecting the voltage that appears at the Vcc terminal, pin 4.
Once IC801 begins to operate the supply voltage at pin 4 is supplied via the rectifying diode D803 and smoothing capacitor C816 which is fed from the drive winding of the switching transformer T801.
At start-up, capacitor C816 is charged via the start-up circuit resistors R805, R814 which applies 16V to pin 4 of IC801. The voltage applied to pin 4 of IC801 is then fed to the internal start circuit, over-voltage monitor and latch circuit which are used to control the oscillator and drive stage. When pin 4 reaches approximately 16V, IC801 begins to operate and drive the internal MOS-FET transistor into conduction resulting in current flow via the primary winding of T801, pin 3 (drain terminal) and pin 2 (source terminal) of IC801.
This supply voltage which is fed from the drive winding B2 of T801 is initially unable to provide the supply voltage demanded and so the voltage at pin 4 decreases. The charge held by C816 however slows this decreasing voltage at pin 4 long enough to prevent the shut down voltage of 10V being reached, thus allowing the drive winding voltage at B2 to become established.
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1.4. Operation
1.5. Regulation
When the internal MOS-FET transistor of IC801 conducts the current flows via the primary winding P1 / P2 of T801 and IC801 pin 3 (Drain) and pin 2 (source) causing a voltage drop across R810, R811 to develop. This voltage drop across R810, R811 is then fed back to pin 1 of IC801 via a noise filter made up of R809, C815.
The power supply ON time is controlled by controlling the feedback supply to pin 1 of IC801. This is achieved by the use of the photocoupler D805. The photocoupler current varies in response to the level at pin 2 of the comparator IC IC850. IC850 is used to monitor the B+ supply by comparing the B+ secondary voltage with an internally established reference voltage within IC850.
This feedback voltage at pin 1 (approx. 2.5V) is then fed to an internal comparator that is used to detect when the voltage at pin 1 exceeds the internally generated 0.73V reference signal. When this condition is detected the internal MOS-FET transistor is switched OFF. At the same time once IC801 begins to operate Vcc pin 4 is supplied from the drive winding B2/B1 as mentioned previously.
The figure below shows how the ON time changes against the current fed via D805 to pin 1 of IC801. 0.900 0.800 0.700
This voltage developed in the drive winding is also fed via an RC Network consisting of D804, R815, C819 and D806 (located between the drive winding of T801 and pin 1 of IC801) which is used to delay the switch ON of the internal MOS-FET transistor, allowing zero current switching. This reduces switching losses that occur as a result of operating with high switching frequencies.
Q L S
0.600
P E I ,
0.400
0.500
$
0.300 0.200 0.100 0 0
When the internal MOS-FET transistor of IC801 is switched OFF, as described earlier, the current flow via the primary winding P2, P1 stops. This results in the collapse of the magnetic field of T801 and the energy stored in the primary winding is transferred to the secondary windings. During this period the voltage at pin 1 of IC801 begins to fall at a rate determined by C819. When the internal comparator of IC801 detects that the voltage at pin 1 is below the internally generated 0.73V reference signal the MOS-FET is switched ON and the cycle is repeated.
10
20
30
40
50
7LPH XVHF
If either the A.C. mains input voltage to SMPS gets higher, or the load current on the secondary gets smaller, pin 2 of IC850 sinks more current causing the opto-islator to conduct more. This causes the current flowing via the photocoupler D805 to pin 1 of IC801 to increase, resulting in the ON time of the internal MOS-FET transistor of IC801 to become shorter. This in turn causes the secondary B+ level to return to its nominal value.
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1.6. Protection Circuitry 1.6.1.
Thermal Shut-down
In this condition the Vcc input (pin 4) voltage decreases until the the Vcc input reaches the shut-down voltage of 10V. At this point pin 4 begins to rise again but when it reaches the start up level (16V) the latch circuit continues to stop the drive. When the latch is ON, Vcc pin 4 voltage increases and decreases within the 10V to 16V range, as shown in figure 1 and is prevented from rising normally.
This circuit triggers the latch circuit when the body of the IC exceeds 140C 1.6.2.
Overvoltage Protection
The Overvoltage protection (OVP) is used to trigger the latch circuit (mentioned later) when the Vcc voltage at pin 4 exceeds 22V. Although the OVP circuit basically functions as protection of the Vcc terminal, it also prevents over voltage at the secondary output, since the Vcc terminal is supplied from the drive winding of transformer T801, whose voltage is proportional to its output voltage from the secondary windings. 1.6.3.
Cancellation of the latch is achieved by switching OFF the TV and disconnecting the AC input to the circuit. 1.6.5.
150V Line Protection
Overcurrent In-conjunction with the above mentioned protection circuits, the 150V line is separately monitored for over voltage protection (OVP) and over current protection (OCP). The OVP is monitored by zener diode D875, which when its breakover voltage is exceeded causes transistor Q855 to conduct. When Q855 conducts its collector is pulled LOW, this LOW level is then fed via connector E15 pin 2 to the W-Board via connector W7. On the W-Board this resultant LOW level is then fed to the base of Q853 which is pulled LOW, resulting in Q853 being switched OFF. When transistor Q853 is no longer conducting then no current flow takes place via the standby relay (RL801) winding and the collector/emitter junction of transistor Q853. The result of no current flow via the standby relay (RL801) winding causes the normally open relay contact of the standby relay RL801 to open, stopping the supply of the mains voltage to the main power supply circuit located on E-Board causing the TV to switch into standby. Likewise where an over current situation occurs then an increased voltage drop across current limiting resistor R877 develops. This increased voltage drop biases on Q857 which feeds a HIGH level via the emitter/collector junction of Q857 to the base of Q855. When transistor Q855 conducts again Q853 becomes non-conducting resulting in the TV being switched into standby mode.
The Overcurrent protection (OCP) is performed pulse-by-pulse by detecting the peak of the drain current of the MOS-FET in every pulse and which is used to reverse the internal oscillator output of IC801. The MOS-FET drain current is detected by inputting the voltage drop developed across R810, R811 into pin 1 of IC801 via the noise filter circuit R809, C815. When this input voltage exceeds the internally generated reference signal of 0.73V the drive output is pulled LOW, resulting in the internal MOS-FET of IC801 switching OFF and the power supply stopping. 1.6.4.
Latch
The latch circuit is used to keep the output from the oscillator low stopping the power supply operating when the overvoltage (OVP) and thermal shut-down (TSD) circuits are in operation. Vin
16V (TYP) 10V (TYP)
figure 1
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1.7. Secondary side On the secondary side the transformer supplies the following voltages : 1.
B+ voltage used to supply the line output stage
2.
12V and 5V to supply an operating voltage to the TV digital processing ICs.
3.
29V to supply the audio output stage
1.7.1.
Voltage Stabilisation
The stabilisation of the previously mentioned secondary supplies is performed as follows: :
Although the secondary voltages are relatively stable with short term load variations being compensated for by IC801, it is still necessary to stabilise the following voltages: 5V, 8V and 12V.
A 15V supply which is fed from the transformer T801 is fed to pin 1 of IC851 which is used to produce a stabilized 12V supply. This 12V supply is also fed to IC853 pin 1 which produces a stabilised 8V supply output via pin 2. and which is used to supply the MSP IC2101.
The 5V supply is produced by feeding 7V to the collector of series regulating transistor Q850 which at its emitter, outputs a 5V supply. The zener diode D857 in the base of Q850 is used to maintain the base of Q850 at a constant potential.
The voltages which do not require further stabilisation are : B+ voltages for the line output stage , 29V supply for the A.F. output stage
To Pin 75 IC1101
+15V
To Q855 +B Protection
+V To Pin 1 IC801
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DVB Power Supply
2.1. General On the EURO 4D chassis, we see the introduction of an integrated DVB (Digital Video Broadcasting) decoder used for the processing of digital terrestrial signals. To perform this processing an additional power supply located on the W-Board is used.
by the integrated circuit STR-F6653, IC4801. The A.C. mains supply voltage input via connector M10 of the M-Board is fed via the main TV ON/OFF switch S802 to connector M11. The A.C. voltage is then fed from the M-Board and connector M11 to the W-Board and connector W1, where the A.C. supply is fed to the standby supply circuit, discussed in chapter 4 Section 1.1., and the DVB power supply relay RL4801.
The supply voltages for the DVB decoder are provided
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The DVB power supply relay RL4801 is controlled by the DVB microcontroller and transistors Q4852, Q4851. Transistor Q4851 is fed a supply voltage of approximately 7V from the junction of resistors R861, R862 and diode D868 of the standby power supply. This 7V supply is then fed via resistor R4863 and the relay winding of the DVB relay RL4801 to the collector of Q4851.
normally open relay contact to close. When the relay contact closes the mains A.C. supply is fed to the bridge rectifier D4802. Here the A.C. supply is fully rectified before being smoothed by capacitor C4809. This supply voltage of approximately 350V is then split into two paths.
When the DVB decoder is in operation a Low level is applied to the base of transistor Q4852 fed from the DVB microcontroller via connector W4 pin 3. This LOW level switches OFF Q4852 resulting in a HIGH level being fed via resistor R4855 to the base of Q4851. This HIGH level which is now applied to the base of transistor Q4851 is biased into conduction, resulting in current flow taking place via the DVB relay RL4801 and the collector / emitter junction of transistor Q4851, this current flow causing the
50
1.
The first path feeds the supply voltage via the primary windings P2 / P1 of transformer T4801 to pin 3 of IC4801 and the drain terminal of the internal FET transistor. Which at present has no gate control voltage preventing the operating voltage from being subjected to any load.
2.
The second path the supply voltage takes from the bridge rectifier D4802 is via the start-up circuit made up of resistors R4802 / R4803, the operation of which is discussed in the following section.
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2.2. Start Up Operation The start-up circuit, which consists of resistors R4802 and R4803, is used to start and stop operations of the power supply IC IC4801. This is achieved by detecting the voltage that appears at the Vcc terminal, pin 4.
This supply voltage which is fed from the drive winding V1 of T4801 is initially unable to provide the supply voltage demanded and so the voltage at pin 4 decreases. The charge held by C4810 however, slows this decreasing voltage at pin 4 long enough to prevent the shut down voltage of 10V being reached, thus allowing the drive winding voltage at V1 to become established.
At start-up, capacitor C4810 is charged via the start-up circuit resistors R4802, R4803 which applies approximately 16V to pin 4 of IC4801. The voltage applied to pin 4 of IC4801 is then fed to the internal start circuit, over-voltage monitor and latch circuit which are used to control the oscillator and drive stage. When pin 4 reaches approximately 16V, IC4801 begins to operate and drive the internal FET transistor into conduction resulting in current flow via the primary winding of T4801, pin 3 (drain terminal) and pin 2 (source terminal) of IC4801.
Also located at pin 4 is a zener diode D4801 which is used as an over-voltage device to protect the input pin 4 of IC4801. The zener diode D4801 which operates as a CROW BAR device will conduct If an over-voltage situation occurs and the zener diodes break-over voltage is exceeded, this will create a short circuit resulting in the over-current protection circuit discussed in chapter 4 section 2.5.3. becoming active, the end result being the shut down of the power supply.
Once IC4801 begins to operate the supply voltage at pin 4 is supplied via the rectifying diode D4808 and smoothing capacitor C4810 which is fed from the drive winding of the switching transformer T4801.
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2.3. Operation
2.4. Regulation The power supply ON time is controlled by controlling the feedback supply to pin 1 of IC4801. This is achieved by the use of the photocoupler D4811 whose conduction is varied in response to the load which is monitored by IC4855.
When the internal FET transistor of IC4801 conducts the current flows via the primary winding P2 / P1 of T4801 and IC4801 pin 3 (Drain) and pin 2 (source) causing a voltage drop across R4805, R4807 to develop, the voltage as this point being monitored by the CROW BAR configured zener diode D4805, used in case of an over voltage condition. This voltage drop across R4805, R4807 is then fed back to pin 1 of IC4801 via a noise filter made up of R4808, C4807.
To monitor the load, the regulator (R) terminal of IC4855 is connected to the 3.3V supply via the voltage divider resistors R4858 / R4859. If any variations are detected by IC4855 via the R terminal, the cathode (K) terminal will increase the flow of current via the diode junction of the photo-coupler D4811 and the cathode (K) and anode (A) junctions of IC4855. This in turn controls the flow of current via the collector / emitter junction of the photo-coupler D4811 and pin 1 of IC4801, controlling the power supply ON time.
This feedback voltage at pin 1 (approx. 2.5V) is then fed to an internal comparator that is used to detect when the voltage at pin 1 exceeds the internally generated (0.73V) reference signal. When this condition is detected the internal FET transistor is switched OFF. At the same time once IC4801 begins to operate Vcc pin 4 is supplied from the drive winding V1/V2 as mentioned previously.
The figure below shows how the ON time changes against the current fed via D805 to pin 1 of IC4801. 0.900 0.800 0.700
This voltage developed in the drive winding is also fed via an RC Network consisting of D4809, R4810, C4806 and D4807 (located between the drive winding of T801 and pin 1 of IC4801) which is used to delay the switch ON of the internal FET transistor, allowing zero current switching. This reduces switching losses that occur as a result of operating with high switching frequencies.
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0.400
0.500
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0.300 0.200 0.100 0 0
When the internal FET transistor of IC4801 is switched OFF, as described earlier, the current flow via the primary winding P1, P2 stops. This results in the collapse of the magnetic field of T4801 and the energy stored in the primary winding is transferred to the secondary windings. During this period the voltage at pin 1 of IC4801 begins to fall at a rate determined by C4806. When the internal comparator of IC4801 detects that the voltage at pin 1 is below the internally generated (0.73V) reference signal the FET transistor is once again switched ON and the cycle is repeated.
10
20
30
40
50
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If either the A.C. mains input voltage to the SMPS gets higher, or the load current on the secondary gets smaller, the K and A junction of IC4855 sinks more current causing the opto-islator to conduct more. This causes the current flowing via the photocoupler D4811 to pin 1 of IC4801 to increase, resulting in the ON time of the internal FET transistor of IC4801 to become shorter. This in turn causes the secondary 3.3V level to return to its nominal value.
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2.5. Protection Circuitry 2.5.1.
Thermal Shut-down
2.5.4.
This circuit triggers the latch circuit when the body of the IC exceeds 140C 2.5.2.
The latch circuit is used to keep the output from the oscillator low stopping the power supply operating when the over voltage (OVP) and thermal shut-down (TSD) circuits are in operation.
Overvoltage Protection
The Overvoltage protection (OVP) is used to trigger the latch circuit (mentioned later) when the Vcc voltage at pin 4 exceeds approximately 22V. Although the OVP circuit basically functions to protect of the Vcc terminal, it also prevents over voltage at the secondary output, since the Vcc terminal is supplied from the drive winding of transformer T801, whose voltage is proportional to its output voltage from the secondary windings. 2.5.3.
Latch
Vin
16V (TYP) 10V (TYP)
Overcurrent
The Overcurrent protection (OCP) is performed pulse-by-pulse by detecting the peak drain current of the FET in every pulse and which is used to reverse the internal oscillator output of IC4801.
figure 1 In this condition the Vcc input (pin 4) voltage decreases until the the Vcc input reaches the shut-down voltage of 10V. At this point pin 4 begins to rise again but when it reaches the start up level (16V) the latch circuit continues to stop the drive. When the latch is ON, Vcc pin 4 voltage increases and decreases within the 10V to 16V range, as shown in figure 1 and is prevented from rising normally.
The FET drain current is detected by inputting the voltage drop developed across R4805, R4807 into pin 1 of IC4801 via the noise filter circuit R4806, C4807. When this input voltage exceeds the internally generated reference signal (0.73V) the drive output is pulled LOW, resulting in the internal FET transistor of IC4801 switching OFF and the power supply stopping.
Cancellation of the latch is achieved by switching OFF the TV and disconnecting the AC input to the circuit.
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2.6. Secondary side 3.
On the secondary side of transformer T4801 the voltages supplied are as follows: 1. 12V, 5V and 3.3V are used to supply operating voltages to the DVB digital processing ICs. 2.
32V to supply the digital tuner
Although the secondary voltages are relatively stable with short term load variations being compensated for by IC4801, it is still necessary to stabilise the following voltages: both 5V supplies, 9V and 12V.
5V supply used by the conditional access module
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2.7. Voltage Stabilisation 2.7.1.
The regulator input being connected to the 5V supply via a voltage divider consisting of resistors R4871 / R4872. If any load variations are detected by IC4853, the cathode (K) terminal output will increase or decrease the base bias of transistor Q4856. The base bias being fed from the 12V line via R4866. By adjusting this base bias of Q4856 by a greater or lesser degree the 5V supply is stabilised.
12V Supply
A 14V supply which is fed from the transformer T4801 is fed to pin 1 of IC4851 which is used to produce a stabilized 12V supply output from pin 3. This stabilised 12V supply is then fed to the V-Board containing the DVB digital processing IC’s via connectors W3 pin 6 to V9. 2.7.2.
9V Supply
At start-up to ensure that the 3.3V supply rises before the 5V supply transistor Q4858 is used. As the supplies being to rise at switch ON transistor Q4858 is biased into conduction by the rising 12V supply line which is fed via resistor R4866. At this point the capacitor C4873 is charging keeping the base of Q4858 at a lower potential then its emitter, this ensures that Q4858 conducts removing the base bias of transistor Q4856 thus preventing the 5V supply from being output. However once capacitor C4873 has charged the base potential rises biasing OFF Q4858, this in turn allows transistor Q4856 to be biased into conduction and supplying a stabilised 5V supply. This delay in the output of the 5V supply is long enough to allow the 3.3V supply to become established.
The stabilised 12V supply produced by IC4851 and fed to the V-Board just mention is also used to produce a 9V supply. The 9V supply is produced by feeding the 12V (fed to V-Board as just mention) back out from the V-Board via connector V6 pin 5 to the H-Board and connector H6 pin 5. Here on the H-Board the 12V supply is used to supply the Video and Audio switching ICs IC3401 and IC3151, the 12V supply is also fed to connector H11 pin 2 where the 12V supply is fed to the E-Board via connector E28 pin 2. Once on the E-Board this 12V supply is then fed to IC3801 pin 1 which produces a stabilised 9V supply output via pin 3 of IC3801. This 9V supply is then is used by the tuner / IF stage. 2.7.3.
5V Supply
A supply of approximately 6V is output from transformer T4801 and fed to the collector of transistor Q4856. Transistor Q4856, which is connected as a series regulator. inconjunction with IC4853 produces a regulated 5V supply.
2.7.4.
5V CA (Conditional Access) Supply
This 5V CA (Conditional Access) supply is produced by feeding a 6V supply from transformer T4801 to IC4852 pin 5. Output from pin 3 of IC4852 is a stabilised 5V supply which is fed to connector W3 pins 11 and 12, from here the supply is then fed to the V-Board and the conditional access module.
The 5V supply fed from the emitter junction of Q4856 is monitored by IC4853, via the regulator (R) terminal.
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2.8. Secondary Supply Protection On the secondary side of the power supply a number of protection circuits are used which are discussed below. 2.8.1.
Q4855 conducting pin 2 of IC4852 is then pulled LOW switching OFF IC4852. Cancellation of the latch circuit operation is achieved by switching OFF the TV disconnecting the A.C. input to the power supply circuit.
3.3V Protection
In the case of the 3.3V supply failing, IC4854 which (houses a latch circuit) is monitoring the supply via pin 2, would sink current via pin 1 of IC4854. This would result in the capacitor C4873 discharging very rapidly, causing transistor Q4858 to switch ON. When transistor Q4858 conducts the base bias from transistor Q4856 is removed, stopping the output of the 5V supply. 2.8.2.
2.8.3.
12V Protection
Likewise the 12V supply line is also monitored, in this case for over voltage conditions by transistor Q4859. Transistor Q4859 is connected to the 12V supply line via the potential divider resistors R4882 / R4883, while the base of transistor Q4859 is connected to the 5V supply line via resistor R4879.
5V (Conditional Access) CA Protection
In normal operation the resistor configurations of the emitter and base junctions ensures that the transistor Q4859 is switched OFF. However if an over voltage condition arises and the 12V supply rises by approximately 1V the emitter of Q4859 would become more positive with respect to its base, this would result in the transistor Q4859 being biased into conduction. To prevent any voltage spikes or ripples causing the transistor Q4859 to conduct, capacitor C4874 is used.
The 5V supply output from pin 3 of IC4852 is fed via resistor R4873 used to monitor the current flow to the Conditional Access (CA) module. Resistor R4873 develops a voltage drop that is fedback to IC4852 pin 4. and used to regulate the 5V output supply. However if the current flow reaches to high a level, the voltage drop developed across R4873 would cause transistor Q4857 to conduct. When transistor Q4857 conducts a HIGH level is fed to the latch circuit made up of transistors Q4854 / Q4855. The HIGH level fed to the base of Q4854, biases the transistor into conduction. Now with transistor Q4854 conducting, the base of transistor Q4855 is pulled LOW, this resulting in Q4855 also conducting. With transistor
When transistor Q4859 is switched ON then a HIGH level is fed to the base of transistor Q4860. This HIGH level would thus result in transistor Q4860 being biased into conduction, pulling the base bias of transistor Q4856 LOW, switching off the 5V supply.
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MICROPROCESSOR AND TELETEXT PROCESSING
The microprocessor SDA5450 IC1101 used on EURO 4D chassis, performs the same processing as that of EURO 4 which is control and teletext processing. Although as just mentioned the processing performed by the microprocessor IC1101 on the EURO 4D
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chassis is the same as EURO 4 , some pin differences do occur, these differences being highlighted in the following sections. The First area looked at being control processing stage of the microprocessor.
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3.1. Microprocessor Stage 3.1.1. :
Input Control
conduct resulting in transistor Q1118 being biased into conduction, feeding a HIGH level to pin 8 of the microprocessor IC1101.
Pins 3/4 - XIN / XOUT
The internal oscillator of the CPU is synchronised with an external 6MHz quartz crystal X1101 which is connected to pins 3 and 4. The Clock frequencies for the I2C bus system are also obtained from this frequency by internal dividing. :
The ALE control line pin 8 is held HIGH until the supply voltages have become established, at which time pin 1 of IC1104 goes HIGH. This HIGH level results in the diode D1112 becoming reversed biased, switching OFF transistor Q1118 and removing the HIGH level from pin 8 enabling the address lines.
Pin 5 - Reset
:
During power On/Off operation, or during a fall in voltage to the microprocessor IC1101, incorrect operation may occur. To prevent this incorrect operation the microprocessor IC1101 has a reset signal input via pin 5. This reset signal is provided by the reset IC IC1104 pin 1, which keeps the microprocessor IC1101 in a stable condition until the voltage level has risen and become stabilised. This reset IC IC1104 which is fed a 5V standby supply is input via pin 2. At switch on this supply is less than 4.8V which results in the reset IC IC1104 pulling pin 5 of the microprocessor IC1101 LOW, providing a stable condition until the supply voltage becomes greater than 4.8V. At this point the reset line goes High and the microprocessor IC1101 begins to operate. :
Pin 46 - HS
This input is used by the microprocessor for synchronisation of the CVBS signal used for teletext processing and display :
Pin 47 - VS
This input is used by the microprocessor for synchronisation of the CVBS signal used for teletext processing and display. :
Pin 54 - Reset In
This input terminal is used as a power OFF reset by the microprocessor IC1101 as the TV is switched into standby. Without this power OFF reset the microprocessor IC1101 has no way of knowing the operational condition of the TV. When the TV is switched OFF the operational data from the VDP IC601 and MSP IC2101 is lost, this means that at switch ON the data has to be reloaded back into the VDP IC601 and MSP IC2101. To be able to do this the microprocessor IC1101, has to be reset so that at switch ON from standby the required operational data is reload back into the VDP IC601 and MSP IC2101. This is achieved with reset IC IC1105 which monitors the 5V supply line via pin 2. When the 5V supply falls to approximately 4.8V the reset IC IC1105 inputs a reset pulse via pin 54 of the microprocessor IC1101.
Pin 8 - ALE
This Address Latch Enable (ALE) control line which is connected to the transistor Q1118, and whose conduction is controlled by the reset IC IC1104 pin 1, is used to hold the address lines in a stable condition during switch ON periods. The reset IC IC1104 which as mentioned under Pin 5 - Reset, is fed a 5V standby supply input via pin 2. At switch ON this supply is less than 4.8V which results in the reset IC IC1104 pulling the reset line LOW, this LOW level thus causes the diode D1112 to
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Pin 58 - Slow1 / Pin 59 Slow2
via resistors R1130, R1129 and R1126 to pin 58 of the microprocessor IC1101.
The circuit is designed so that it is possible to switch over to either AV1 or AV2 channels from all programme locations, allowing automatic processing of a composite video signal input from an external source via the 21 pin scart terminals, by using the Slow switch control line of AV1 and AV2.
The table shown below shows the required voltages for aspect ratio selection. )XQFWLRQ
9ROWDJH 9
Internal TV switching is performed by the video switching IC IC3401 (located on the H-Board) and is controlled by the microprocessor via I2C Bus 4. By placing an AV turn on voltage at pin 8 of the 21 pin scart sockets, the relevant AV input will be automatically selected.
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Pin 60 - Keyscan
The local control commands fed from the local keys are fed to the microprocessor IC1101 as serial data, this data being input via pin 60. When no commands are fed from the local keys pin 60 is held at 5V by pull-up resistor R1256 (located on the H-Board) which is connected to the 5V standby supply. This means that this High level is also maintained during standby condition. Operating commands fed from the local keys results in varying voltages being applied to pin 60 which inturn initiates the varies controls. Operating commands issued from the local and remote control are treated with equal status,
These turn on voltages fed from AV1 and AV2 pin 8 are fed from the H-Board to the E-Board. This sees the slow switch signal from AV1 being fed via connectors H11 and E28 pin 18. Likewise for AV2 the slow switch signal is also fed from the H-Board to the E-Board via connectors H12 and E29 pins 10. Once both the slow switching signals are input onto the E-Board, they are then fed to IC1101 and pins 58 (AV1) and 59 (AV2) of the microprocessor. Pin 8 of AV1 and AV2 scart sockets are also used to allow the microprocessor IC1101 to perform automatic picture ratio selection between 4:3 and 16:9 formats during AV operation. However, a pre-requirement for this would be for example, the provision of a video recorder able to process both picture formats. It has been established that during play-back recorders with a picture format of 4:3, supply a slow switch control voltage of 12V, and those with an aspect ratio of 16:9 supply a slow switch control voltage of 6V. These switching voltages which are fed to the microprocessor pins 58 (AV1) and 59 (AV2) as mentioned previously are fed via the potential divider resistors R1131, R1128, and final R1127 to pin 59 for AV2 selection. AV1 selection is fed
:
Pin 61 - AFC
During search mode the microprocessor IC1101 detects the AFC voltage input via pin 61, which is fed from the tuner/I.F. stage. When the AFC voltage reaches mid level between the highest and lowest points of its swing, the microprocessor stops the search operation and holds the data. :
Pin 63 - 65 - FLT1-3
FLT3 pin 63 is used for the phase shifting of the VPS or teletext data. FLT2 pin 64 PLL filter for VPS slicing. FLT1 pin 65 PLL filter is used by the teletext slicer.
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Pin 67 - IRef
1.
During normal operation the beam current is measured, with the result being input via the sense input of VDP IC601, pin 28. The beam current limitation is carried out via software control with the results of this being used to back off the RGB output amplifiers in this I.C. to a greater or lesser extent, thereby limiting the beam current.
This is a reference current for internal PLL. :
Pin 68 - CVBS In
This composite video signal which is input via pin 68 is used for teletext processing which is carried out within the microprocessor IC1101. :
Where the control limit is exceeded, although the amplifiers have been completely reversed (which may lead to an error in the RGB final outputs or there voltage supply), defects in the CRT may result if no protective measures are taken.
Pin 71 - VProt
This input is used to detect a fault in the deflection circuit. This is achieved by using the vertical synchronisation signal which is fed to the microprocessor IC1101 pin 47, via transistor Q1108. This signal is also fed via diode D453 where capacitor C455 is charged. The charge held by capacitor C455 results in a HIGH level being applied to the base of transistor Q451, which ensures that the transistor is switched OFF. When transistor Q451 is switched OFF a HIGH level is applied to pin 71 of the microprocessor IC1101, fed via resistor R457. This HIGH level ensures that the safety input of the microprocessor IC1101 is in-operative.
In order to avoid this, zener diode D511 is incorporated into the circuit. During normal operation the zener diode D511 is non-conducting and Pin 75 of the microprocessor IC1101 is held High via resistor R1149. In this state the protection circuit does not operate. Where an error described arises and the beam current continues to rise then the zener diode D511 conducts due to the negative voltage fed back from T551 (Flyback transformer), which causes diode D609 to conduct pulling the anode of the zener diode D511 lower than its cathode. As its anode is pulled lower, its cathode becomes more positive. Once the zener diodes breakover voltage is reached pin 75 of the microprocessor IC1101 is pulled LOW.
Where an error occurs resulting in there being no vertical synchronisation signal being fedback to transistor Q451, capacitor C455 discharges via R458 resulting in transistor Q451 conducting. This results in pin 71 of the microprocessor IC1101 being pulled LOW and the TV switching into standby after a short delay. :
Where upon, after a short delay the microprocessor IC1101 switches the TV into standby. 2.
Pin 74 - RC
Voltage supply lines protection
The Voltage supply lines monitored for short circuit faults, are: : 12V supply monitored via D863
The user commands for control of the TV receiver are applied via the remote control. These commands from the remote control transmitter are applied via RPM-637CBRL IC1061 the remote control receiver and Q1051 to pin 74 of IC1101, this command data being in serial format. :
ABL protection
:
8V supply monitored via D865
:
5V supply monitored via D866
If a fault occurs resulting in one of the aforementioned supplies failing then the safety diode connected to that supply will conduct. This will result in the base of Q851 (which is switched OFF during no fault conditions) going low with respect to its emitter. In this condition Q851 would conduct biasing ON Q856, this would cause pin 75 of the microprocessor IC1101 to go LOW and the TV would shut down into standby.
Pin 75 - Prot1
The microprocessor IC1101 pin 75 which is normally held High via R1149 provides a protection input which is used to switch the TV into standby mode. The protection input has two hard wired protection circuits, these being:
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Common Circuits
Output Control OSD information on screen. The RGB signals being output from the following terminals: Blue - pin 39, Green - pin 38, Red - pin 37
Pin 6 - WR
This is the Write Enable line used to signal the UART IC IC1107 when information is going to be written to this device. :
:
Pin 7 - RD
The blanking pulse output from the microprocessor IC1101 pin 40 is used to provide the required switching control for the teletext and OSD displays.
The Read Enable line is used to signal the UART IC IC1107 when information is going to read from this device. :
:
Pins 9, 10, 12 - 22, 24 - 27, 29 - A17 - A0
:
Pin 23 - PSEN
Pins 28, 30 - 36 - D7 - D0
The Data lines D7-D0 allow 8 bit data to be transferred between the EPROM IC1102 and microprocessor. These same data lines are also used to transfer data between the microprocessor and UART IC. :
Pin 53 - Reset Out
To ensure correct operation of the digital TV ICs (VDP, MSP), they must be started at a specific time in order to permit signal processing. This is achieved by the reset control line output from pin 53 of the microprocessor IC1101. During switch ON the digital ICs are held LOW by Q1101 which is conducting at this point due to the 5V standby supply fed to the base of Q1101 via R1112. Once the supply voltages have become established pin 53 of the microprocessor IC1101 pulls the base of Q1101 LOW resulting in it switching OFF, a HIGH level is then fed via R1111 to the digital ICs initiating their start-up.
The Programme Store Enable output is used by IC1102 as the EPROM enable control line. :
Pin 52 - ON/OFF
This output is responsible for switching the TV into and out of standby mode. When an ON command is received, the ON/OFF output fed from pin 52 is set to a LOW level which is fed to the base of switching transistor Q854 (located on the W-Board). The output from pin 52 of the microprocessor IC1101 only switches High when an OFF command is received.
These address lines are used to address two devices. The first device being the EPROM IC1102, where not only is the device addressed, but also the memory location for storing or reading data from the selected memory device. The second device connected to the address lines is the UART IC IC1107, here this device is addressed via address lines A0-A2 while A15 is used as the chip enable line for this device. :
Pin 40 - Blanking
Pins 37 - 39 - R,G,B Output
The RGB signals output from the microprocessor IC1101 are used to display the required teletext and
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Pin 55 - Service
LOW level results in Q1013 switching ON and the DVB LED is illuminated.
PLEASE NOTE: Even though this following option is still available when in Service Mode, the EAROM of the EURO 4D Chassis is 32k bits and the Memory Pack is only 16k bits. This means that the memory pack is unable to store all the EAROM data.
:
The SERVICE output control line only goes high when the TV is switched into Service Mode. The service control line is used to allow a memory programmer to be connected via AV1, allowing data to be transferred between TV and memory programmer or vice versa. The programmer basically consists of an EAROM which when connected to the AV1 socket, can talk directly with the microprocessor IC1101 via the I2C bus 1. Since pins 10 and 12 of the 21 pin AV1 socket are available only during service mode, I2C bus 1 must be set to high impedance during all other operating modes. This is achieved by disconnecting the I2C bus 1 from the 21 pin socket by means of two transistors Q3006 and Q3007. Transistors Q3006 and Q3007 are controlled via pin 55 of the microprocessor IC1101, which when the Programmer function is called up in Service Mode, the transistors are switched ON with a High level allowing the transfer of programming data from the microprocessor IC1101 to programmer or from the programmer to microprocessor IC1101. As mentioned earlier the transistors are switched OFF with a Low level, thus switching pins 10 and 12 of AV1 socket to high impedance.
:
:
Pin 73 - In
This control line output from pin 73 of the microprocessor IC1101 is used as an interrupt control line between the UART IC IC1107 located on the T-Board the microprocessor IC1101 on the E-Board. Pin 77 - G.M.C.
Output from pin 77 of the microprocessor IC1101 is Geo-Magnetic Correction control, this is used for large screen CRTs which is required to cancel the effects of the earth’s magnetic field. :
Pin 79 - 4:3 RGB
The 4:3 RGB control output from the microprocessor is used to support the display of an RGB picture on wide screen TVs. This is achieved by mechanical means as oppose software by transistor Q590 and relay RL590. The 4:3 RGB control line being used to control transistor Q590 responsible for controlling the horizontal aspect ratio. Where the aspect ratio of the picture is reduced to a 4:3 display the operating voltage to the DAF circuit located on the W-Board has to be reduced too, ensuring that the DAF correction signal is also reduced to match the active picture scan ensuring optimum picture conditions as described in chapter 4 section 6. :
Pin 81 - LED
The standby LED is incorporated into a dual LED device D1012 (located on the H-Board) which has two LED’s. One LED is used to display TV standby, while the second is used to signal operation of the DVB Decoder. Control of the standby LED is via pin 81 of the microprocessor IC1101, which when in standby mode is set to a LOW level causing Q1011 on the M-Board to switch ON, resulting in the standby LED to switch ON. Pin 81 is also used to flash the standby LED when the Infra-red remote control receiver receives a signal from the remote control.
Pin 69 - LED IRD
The LED device D1012 located on the M-Board incorporates two LEDS. One LED is used to display TV standby, while the second is used to signal operation of the DVB Decoder. Control of the DVB LED is via pin 69 of the microprocessor IC1101, which when in operation feeds a LOW level to Q1013 on the M-Board. This
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Chapter 3.1.3. :
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EURO 4D Supplement quality). Here the TV/video at first time of connecting send information regarding each others features and operation capabilities, such as the signal standards they can processes and whether they are able to process and display 16:9 format as an example.
Q-Link
AV_Link
The AV_Link control line is used to transfer information and user functions between the TV and VCR via pin 10 of the 21 pin scart terminals using a 21 pin socket lead which conforms to the EUROCONNECTOR standard.
3.1.4. :
The transfer of data fed from the TV to the VCR is output from pin 72 of the microprocessor IC1101 via the AV_Link_OUT control line, this data with its dc level biases transistor Q1106. into conduction, feeding the data to pin 10 of AV2 via the AV Link control line.
The following are connected to I2C- bus 1: The video and deflection processor (VDP) IC601, for processing of the composite video signal and deflection processing. The multi standard sound processor (MSP) IC2101, for processing of the sound signals. The tuner and I.F. stage where signal selection and processing is performed.
The type of data and function control information fed via the AV_Link is as follows: 1. TV Auto Power ON: TV automatically turns ON when the VCR starts play-back.
The 21 pin AV1 socket pins 10 and 12 is fed the I2C-bus1 control line via the transistors Q3006 and Q3007. During service mode, therefore, the T.V. may be programmed with the aid of an external memory pack.
VCR Auto Standby: VCR will automatically switch to standby when the TV is turned OFF, unless the VCR is in recording mode.
3.
TV On screen Display of VCR status.
4.
Down load of Country selection.
PLEASE NOTE: Even though the above option is still available when in Service Mode, the EAROM of the EURO 4D Chassis is 32k bits and the Memory Pack is only 16k bits. This means that the memory pack is unable to store all the EAROM data.
These above features will only work with a Panasonic TV / video combination who are both Q-Link (Project 50+) compliant. The features below will work with different brands of TV and video combinations, again as long as both TV and video are Project 50 compliant. 1.
Tuner preset data down load (TV->VCR)
2.
What You See Is What You Record (Direct TV)
Pin48,49-SCL1,SDA1 Pin 50, 51-SCL2, SDA2 Pin 44, 45 - SCL4, SDA4
The I2C - bus systems are generated by the microprocessor, with data line SDA1 being output via pin 49, SDA2 output via pin 51 and SDA4 output via pin 44, while the required clock lines SCL1, SCL2 and SCL4 are output from pins 48, 50 and 44 consecutively.
Likewise data transferred from the VCR to the TV is again fed via pin 10 of the 21 pin scart terminal (AV2). Here data input from the VCR is fed via the AV Link control line to transistor Q1107, which is configured to function as a diode. When the data input to the TV which has a dc level of approximately 5V is applied to the collector of Q1107, transistor Q1107 conducts feeding the input AV Link data via transistors Q1105, Q1104. At the output of transistor Q1104 the AV Link data is then fed to the T-Board and the UART IC where this AV Link data is acted upon.
2.
I2C Bus
The following are connected to I2C- bus 2 : The EAROM IC1102 is the only IC connected to I2Cbus 2, which contains system data, programme locations and specific tuning values, normal levels etc. Connected to I2C- bus 4: The Video switching IC IC3401 and the audio switching IC IC3151, both ICs being located on the H-Board.
In addition to these features the TV/Video also include in their protocol Automatic signal matching (signal
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3.2. Teletext Processing Stage Programme Signal (VPS). The VPS feature is not used.
General As already briefly mentioned earlier the microprocessor performs teletext processing as well as Control processing. To perform teletext processing the following elements are required: : Teletext (TTX), Video Programme Signal (VPS) slicer used to extract the relevant information from the video signal.
: Display Timing which is used to ensure that the text information is locked to the same timing as the raster scan. : Character ROM which provides the required characters for display of text information on screen
: Acquisition stage allowing simultaneous reception of both the Teletext (TTX) and Video
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EURO 4D Supplement
Teletext Operation
the data is stored in the display RAM until the TTX data is required.
To enable teletext processing by the microprocessor IC1101 a CVBS signal is input via pin 68. Here the signal is fed to the Teletext (TTX) slicer stage, where the horizontal and vertical sync. information and TTX data are extracted from the CVBS signal. To do this the slicer has an analogue circuit for sync. filtering and data slicing as well as an analogue PLL used for system clock generation. A third PLL is used to shift the system clock for data sampling of the TTX signal.
When the TTX data is requested the information is read out of the Display RAM via the interface and fed to the Display Generator. The display generator then selects the pixel information from the character ROM and translates it into RGB values. The character generator itself includes a character and control decoder, a RAM interface, RGB and Blanking signal generators. To allow the character generator to carry out processing of the TTX signal, generation of a pixel clock is required. This generation of the pixel clock is created internally by the display timing stage which is fed a horizontal and vertical sync signal input via pins 46 and 47.
Output from the slicer stage the sliced bit stream is fed to the Acquisition stage where this bit stream is converted into a byte stream and a framing code check to identify the TTX signal takes place. After framing code detection a status word is generated which is used to identify the type of data received and the signal quality of the TV channel.
The TTX data which has now been converted to RGB values are then output from pins 37 (R), 38 (G), 39 (B) with the blanking signal being output via pin 40. These signals are then fed to the VDP IC601.
The text data is then fed via the dual port interface to the buffer, where under the control of the internal CPU
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MEMORY I.C. (EAROM)
Together with the system data for the digital IC’s, customer data is also stored in the EAROM IC1103.
The memory location address is then transmitted by the master I.C. (in this case the microprocessor). This address also consists of an 8 bit word whose reception is again confirmed by an acknowledgement bit. If this is the case, the 8 data bits are then transmitted to or from the memory I.C. and their reception is confirmed by the relevant I.C. The transmission described above is carried out by the SDA line and synchronised with the clock in the SCL line.
The stored data includes programme location data such as channel, receiving range, standard, as well as customer adjustment values for brightness, volume and contrast. The EAROM IC1103 has a memory capacity of 32768 bits organised into 4096 words, each of 8 bits. The carrier storage time is equal to a minimum of ten years whereby the read out operations are unlimited. The read in and read out of data is controlled by the microprocessor IC1101 and carried out via I2C- bus2. For this purpose the microprocessor IC1101 generates an 8 bit address word preceded by a start bit. The 8 bit word is composed of a 7 bit word for the address and 1 bit which contains the command for reading out.
After the transmission of the final acknowledgement bit, the memory process is initiated on the command ’read in’. During the storage process, the memory inputs SDA and SCL of EAROM IC1103 are latched in order to eliminate any external influence on the memory during this period.
The address word is checked for compatibility with the address contained in the IC and acknowledged by an acknowledgement bit.
After the switch on process, the system data is read out from the memory via the I2C BUS 2 by the microprocessor.
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Video Display Processor - VDP3120
Although the internal processing of VDP3120, IC601 has not changed, a full explanation of which can be found in the EURO 4 Technical Guide section 17, the input and output processing paths have, these changes being discussed in the following section.
the chrominance signals are output from pin 13 of IC3401 and fed to the VDP, IC601 pin 60. : Pin 61 - Vin1 (RFV) This input, which is fed from the video switching IC IC3401 pin 14, is fed either a video signal from the tuner or the luminance signal from the DVB decoder
A detailed explanation of the Video Switching Circuit can be found in chapter 4 Section 9.
: Pin 62 - Vin2 (AV1V)
: Pin 59 - Video Out
This input is still fed the video signal fed from the 21 pin scart terminal AV1 pin 20 directly to pin 62.
This output feeds either a video or the luminance component of a S-VHS signal to the microprocessor IC1101, as previously, it also feeds this video or luminance signal to the video switching IC IC3401 pin 1.
: Pin 63 - Vin3 (AV2V) This input is still fed the video signal or the luminance signal from the 21 pin scart terminal directly to pin 63 of the VDP.
: Pin 60 - Cin
: Pin 64 - Vin4 (AV3V)
The chrominance signal inputs fed from the various sources are firstly fed to the video switching IC IC3401, discussed in chapter 4 section 9.2., from here
This input is still fed the video signal from the RCA terminal or the luminance signal from the 4-pin S-VHS terminal of AV3 directly to pin 64 of the VDP. Colour Bus
VRT
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2H Adaptive Comb filter
AGC 2*8bit ADC
Colour Decoder PAL NTSC SECAM
Horizontal Scaler
Display Processor
Panorama Mode
RGB Matrix CLUT Scan Veloc.
XREF
RGB/FB IN1 Analogue Backend 3*10bit DAC Tube Control RGB switch
VDP3120B 2 I C
RGB Out
SVM
20.25MHz Clock Gen. DCO
RGB/FB IN2
Sync. & Deflection
H/V/EW
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Measurement ADC
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Dynamic Automatic Focus (D.A.F.)
6.1. Introduction Euro 4D wide screen models have an additional circuit provided, named Dynamic Automatic Focus (D.A.F.), this circuit is used to overcome the problems of poor focus at the outer edges of the picture which is normally associated with large screen CRT’s. By using this D.A.F. circuit, focus of the picture at the outer edges of the CRT are as sharp as the centre portions of the picture. To provide this feature an additional circuit located on the W-Board is used (as shown on page 69). This circuit containing IC3901 is discussed in the following sections.
:
The first path feeds the vertical pulse to the vertical deflection coil which is fed via connector E4.
:
The second path feeds the vertical signal via the zener diode D3931 and transistor Q3921 where the signal is amplified and fed to connector E66 pin 5, here the vertical signal is passed to the W-Board via connector W6. Once on the W-Board the vertical signal is fed to IC3901 pin 15.
The horizontal pulse output from the horizontal output transistor Q551 is split into four paths. :
The first path feeds the horizontal pulse directly to pin 10 of the flyback transformer T551
:
The second path feeds the horizontal pulse directly to the horizontal deflection coil via connector E4.
:
The third path feds a horizontal flyback pulse to the video processing stage of the VDP IC601.
:
The fourth path feds the horizontal pulse to connector E66 pin 4, where the horizontal pulse is fed to the W-Board, and finally IC3901 pin 13 via amplifier transistor Q3901.
6.2. D.A.F. Processing To carry out D.A.F. processing a horizontal and vertical pulse are fed to IC3901. The vertical pulse is output from the vertical output IC IC451 pin 2 (LA7845) where the signal then splits into two paths.
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6.3. AN5422K (IC3901) The horizontal and vertical pulses as mentioned earlier are fed to IC3901 pins 13 and 15. Here a vertical and a horizontal drive pulse are produced and output via pins 3 and 21.
is fed to the vertical drive stage, the amplitude of the vertical pulse being set by R3927 / R3918 connected to pin 19. The vertical pulse is then output via pin 21 synchronised by the vertical flyback pulse input via pin 22. This vertical signal is then fed to the base Q3903.
The horizontal pulse input via pin 13 is fed via a noise cancellation circuit and sync. separator stage whose reference is set via pin 11 by R3987/R3983 and C3939. The horizontal sync. pulse is then output via pin 10 and input via pin 9 of IC3901 to the AFC stage.
Transistor Q3903 is then used to generate a parabola signal of approximately 5Vpp. This parabola waveform is then fed to the cascade connected transistors Q3907, Q3906. Here the signal is amplified to approximately 250Vpp before being fed to pin 4 of transformer T3901.
At the AFC stage the horizontal sync. pulse is compared with the horizontal flyback pulse input via pin 8. Here the phase is set by adjusting R3938. The horizontal pulse is then output via pin 7 and input via pin 6 to the horizontal oscillator stage (the adjustment for which can be set by R3922) before being fed via the horizontal driver stage and output via pin 3.
The D.A.F. transformer T3901 then combines both the horizontal sync pulse mentioned earlier with the vertical parabola waveform. This combined signal is then output via the HV terminal to the D.A.F. input terminal of the FBT T551 located on the E-Board. Here the signal is added to the focus voltage of T551, the focus voltage VF2 with the D.A.F. waveform signal which is then supplied to the focus terminal on the CRT.
After the horizontal drive signal is output from pin 3 at approximately 2.2Vpp the signal is fed via the complementary Darlington pair connected transistors Q3902, Q3904. The signal is then fed via the FET transistor Q3905 to T3901 pin 1 at approximately 250Vpp.
By this method the focus voltage for the central and outer edges of the scan undergo alteration. This results in the focus voltage for the outer edges being reduced compared with that of the central area of the screen, thus increasing the focusing distance of the beam and enhancing focus at the outer edges.
The vertical pulse which is input via pin 15 is fed via the vertical trigger stage before being passed onto the following vertical oscillator. The vertical oscillator is set via pin 16, while the timing of the oscillator is set via pin 18. From the oscillator stage the vertical pulse
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6.3.1. RGB 4:3 Mode On those models which use the VDP IC601 located on the E-Board, an additional circuit is required. This additional circuit is used to support the display of RGB in 4:3 mode.
compression and expansion takes place in the horizontal scaler stage within the VDP. However the RGB signal which is also fed to and processed by the VDP is inserted after the VDP’s horizontal scaler stage, meaning that no horizontal compression can take place. To over come this problem located on the E-Board is a relay RL590.
Where a normal composite or S-VHS signal is processed and displayed on screen, horizontal
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Where a normal wide screen display is processed the the horizontal drive signal is fed from the line output transistor Q551, to connector E4. Here the horizontal drive signal is output to the horizontal scan coil connected to connector E4 pin 4 and fedback via connector E4 pin 1. The horizontal signal is then fed via an L/C/R circuit made up of coil L590, resistor R590 and capacitor C590, from here the signal is fed via the relay contact of RL590, controlled by transistor Q590 and pin 79 of the microprocessor IC1101.
short circuiting L590, R590 and C590. The horizontal signal is again finally fed via coils L595, L591 and L594 back to the FBT. During these periods of 4:3 display the 147V supply voltage to the DAF circuit is also reduced. This is achieved by the circuit (located on the W-Board) consisting of transistor Q3922, Q3923 and opto-isolator D3922. When a normal wide screen display is processed transistor Q3922 is biased into conduction via a pull-up resistor R1141 (located on the E-board) mentioned earlier, this HIGH level being fed via connectors E66, W6 pin 6. When Q3922 is biased into conduction its collector goes LOW removing any bias to the diode junction of the opto-isolator D3922. With D3922 OFF transistor Q3923 is also switched OFF. The supply voltage of 147V to the DAF circuit is thus fed via resistor R3901.
In normal wide screen display transistor Q590 is biased into conduction, via a pull-up resistor R1141 (located at pin 79 of IC1101). This results in current flow being fed via R599 (connected to the 15V supply line), the relay winding and the collector-emitter junction of transistor Q590. This current flow via the relay winding of RL590 results in the switch closing, short circuiting coil L595 and resistors R594 and R595. The horizontal signal is then finally fed via coils L595, L591 and L594 back to the FlyBack Transformer (FBT) T551.
When an RGB 4:3 display is being processed the base of transistor Q3922 is pulled LOW by pin 79 of the microprocessor IC1101. With transistor Q3922 switched OFF the opto-isolator D3922 is biased into conduction by a HIGH level fed via resistor R3902, R3903 fed from the 12V supply line. This results in transistor Q3923 also being biased into conduction by a HIGH level fed via the collector-emitter junction of D3922. With transistor Q3923 now conducting this series regulator configured transistor reduces the supply to the DAF circuit to approximately 90V. By reducing the supply voltage to the DAF circuit the DAF signal is also reduced, ensuring optimum picture conditions as described in chapter 4 section 6.
However when an RGB signal is input and displayed in 4:3 format the relay contact of RL590 is opened. This is achieved again under the control of transistor Q590 and pin 79 of the microprocessor IC1101, which pulls the base of Q590 LOW. This results in the transistor switching OFF and the relay contact opening. When the contact of relay RL590 is open, the path the horizontal signal follows changes. This sees the horizontal signal being fed from the horizontal scan coil (as mentioned earlier) via capacitor C596, the relay contact and coil L595. The relay contact
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Audio Signal Processing in the Euro 4 Technical Guide, section 20.
As with all EURO 4 models, audio processing is provided by the MSP3410 IC2101. The MSP3410 is designed as a Multi-standard Sound Processor used in the processing of analogue and digital audio signals. A full description of its operation can be found
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: Pin 41 - SC1_In_L
Input Signal Processing Path
: Pin 47 - ANA_In1 This left audio channel input which was originally fed directly from AV2, is now fed from the audio switching IC3151 pin 15 located on the H-Board (see chapter 4 section 9.5.2.).
This signal input has not changed, the signal input via pin 47 of the MSP IC2101 being fed directly from the tuner SIF output. : Pin 37 / Pin 38 - SC3_In_L / _R Again this input processing path has not changed, the left and right audio signals fed from AV3 RCA terminals being fed directly to the MSP.
: Pin 42 - SC1_In_R
: Pin 39 / Pin 40 - SC2_In_L / R
This right audio channel input which was originally fed directly from AV2, is now fed from the audio switching IC3151 pin 16 located on the H-Board (see chapter 4 section 9.5.2.).
This input processing path again has no change which sees the left and right audio signals being fed from the 21 pin scart terminal of AV1 .
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Output Signal Processing Path
transistors Q2102 and Q2103 The right and left audio signals are then fed to the Z-Board where the audio signals are processed by the Acoustic Feedback (AFB) stage discussed in chapter 1, section 3.
: Pin 21 - DACA_R This left channel output is used to provide an independently controlled volume for the headphones, which when output from the MSP is fed to the M-Board and the headphone amplifier IC2405, before the audio signal is fed to the headphone terminal (see chapter 4 section 8.).
: Pin 27 - SC2_Out_R The right channel audio signal output from pin 27 of the MSP IC2101 is then fed directly to the audio switching IC3151 pin 21 (see chapter 4 section 9.5.1.).
: Pin 22 - DACA_R This right channel audio output is used to provide an independently controlled volume for the headphones, which when output from the MSP is fed to the M-Board and the headphone amplifier IC2405, before the audio signal is fed to the headphone terminal (see chapter 4 section 8.).
: Pin 28 - SC2_Out_L The left channel audio signal output from pin 28 of the MSP IC2101 is then fed directly to the audio switching IC3151 pin 4 (see chapter 4 section 9.5.1.). : Pin 30 - SC1_Out_R
: Pin 24 / Pin 25 - DACM_R / L
This output is also fed directly to the audio switching IC IC3151 pin 20, mon Rin terminal (see chapter 4 section 9.5.1.).
The left and right audio signals output from pins 24 and 25 of IC2101 are now fed via the Acoustic Feedback (AFB) stage These changes result in the right audio signal being output from pin 24 and the left audio signal being output from pin 25 of the MSP3410 IC2101. From here the left and right audio signals are then fed via
: Pin 31 - SC1_Out_L This output is also fed directly to the audio switching IC IC3151 pin 5, mon Lin terminal (see chapter 4 section 9.5.1.).
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Common Circuits
Headphone Processing E-Board), its operation being discussed in section 10.1 of the EURO 4 Technical Guide.
On the EURO 4D chassis, although not Dolby Pro Logic, independant volume control for the headphone output is used. This independent volume control is provided by the MSP3410 IC2101, which outputs the headphone audio signals via pins 21 and 22.
During the ON and OFF periods the mute control signal is fed via connectors E22 / M6 pin 4 to the emitter of transistor Q2435. The mute control line during the ON / OFF periods is of a HIGH level which causes transistor Q2435 into conduction, biasing on transistors Q2436 and Q2437 which mute the left and right headphone audio signals by pulling them to ground.
The headphone audio signals output from the MSP IC2101 are then fed to the M-Board via connectors E22 / M6 pins 1 and 3. Once on the M-Board the headphone audio signals are then fed to the headphone amplifier IC IC2405 pins 3 (L) and 5 (R).
8.1.1.
The supply voltage for the headphone amplifier IC IC2405 is taken from the 12V supply produced by the 12V regulator IC851, located on the E-Board. This 12V supply being fed via connectors E17 / M2 pin1. On the M-Board this 12V supply is fed to the collector of the series configured transistor Q2440 via diode D2413. This same 12V supply is also fed via resistor R2556 charging capacitor C2510 delaying the switch ON of Q2440 until the charge of the capacitor is sufficient to bias transistor Q2440 into conduction. With Q2440 biased into conduction the supply voltage for IC2405 is thus fed to pin 8 of IC2405.
Here the audio signals are amplified before being output via pins 1 and 7. From the output of the headphone amplifier IC2405 the headphone audio signals are then fed directly to the headphone terminal. 8.1.
Headphone Amplifier IC Supply
Switch ON / OFF POP Mute
At switch ON and OFF times the headphone audio signals are muted to prevent POP. The mute control is generated by transistor Q2101 (located on the
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Audio and Video Switching 1.
Analogue:- This option allows the standard analogue TV signals be output via AV2. Once an analogue TV signal has been selected you are then free to change to a DVB channel, as AV2 out remains set to the selected analogue TV channel
2.
DVB:- When this option is selected the digital terrestrial signals processed by the DVB decoder are output via AV2. As with previous analogue selection, once the DVB signal is selected you are then free to change to an analogue TV channel, as AV2 remains set to the selected DVB channel.
: AV2 21 pin scart terminal
3.
Monitor:- This selection basically means what ever is viewed on screen is output via AV2.
AV2 like AV1 allows the input of a composite video signal which is input via pin 20. However unlike AV1, an S-VHS signal can also be input via AV2 with the luminance signal being input via pin 20 and the chrominance signal input via pin 15. The left and right audio signals input via AV2 are input via pins 2 (right audio in) and 6 (left audio in). Unlike other Euro 4 models AV2 has a selectable output which allows the selection between the analogue TV signals and the DVB signals. This selection can be found under the Setup Menu labelled as AV2 out, where the options for Analogue, DVB and Monitor can be made. These three options being discussed below.
: RS232 Terminals
9.1. H-Board Overview The audio and video switching circuit which consists of two ICs, IC3401 and IC3151 are both located on the H-Board. Also located on the H-Board are the following: : AV1 21 pin Scart terminal AV1 allows the input of a composite video signal input pin 20, RGB and fast blanking signals input via pins 7, 11, 15 and 16 with accompanying audio inputs input via pins 2 (right audio in), and 6 (left audio in). As well as these inputs AV1 also allows for the output of a composite video signal fed via pin 19 and the left and right audio signals output via pins 1 and 3.
Also located on the H-Board are two RS232 connectors, one male, one female. The male connector allowing the connection of a modem, while the female connector as yet has no commercial application. : Audio Monitor Out The Audio monitor out terminal allows for the connection of an external amplifier and speakers, allowing for the reproduction of the audio signal accompanying the programme being viewed on screen at that time.
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9.2. Video Switching Outline The switching of the video, luminance and chrominance signals is provided by IC3401, TEA6415C.
inputs, five fixed level outputs and one variable gain output. The switching of this matrix is controlled via I2C bus 4 at pins 2 and 4. This makes it possible to have multiple inputs and outputs switched at the same time.
This IC consists of a switching matrix which has eight
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9.3. Video Signal Source 9.3.1.
output from pin 13. This detection being used to ensure that no interference occurs in any of the subsequent processing paths.
Video Switching Inputs
Signals input to the video switching IC IC 3401, are applied from a number of sources. These are shown below:
To detect a chrominance signal output via pin 15 a d.c. bias level is applied to the chrominance signals input to the switching IC IC3401, this is achieved via 100K resistors located at the inputs. This d.c. bias is then used to switch transistor Q3441 ON allowing the chrominance signal to be buffered and output via Q3441 where the signal is split into two paths.
: Pin 1 - Mon Vin The input at pin 1 is the monitor input, when this input is selected what is being viewed on screen is output via AV2. : Pin 3 - DVB Vin Pin 3 allows the input of a video signal fed from the DVB decoder located on the V-Board
The first path feeds the chrominance signal via transistor Q3442 where the signal is fed to pin 60 of the VDP IC601 located on the E-Board for further processing.
: Pin 5 - DVB Yin The luminance component of a S-VHS signal fed from the DVB decoder is input via pin 5.
The second path that the chrominance signal follows from the output of transistor Q3441 is to transistor Q3443. Here the chrominance signal is mixed with the luminance signal fed from pin 59 of the VDP IC601. This mixed chrominance and luminance video signal is once again buffered by transistor Q3444 before being fed to back to the switching IC IC3401 and the monitor input pin 1 mentioned in the previous section..
: Pin 6 DVB Cin This input allows the chrominance component of an S-VHS signal to be input fed from the DVB decoder. : Pin 10 - AV3 Cin Pin 10 is fed the chrominance component of an S-VHS signal source input via the 4 pin S-VHS AV3 terminal, located on the M-Board.
Where there is no chrominance signal output from pin 13 of the switching IC IC3401 then the buffered transistor Q3441 is switched OFF. However a video signal output from the pin 59 is then fed to via transistors Q3443, Q3444 and again fed to the monitor input pin 1 of IC3401.
: Pin 11 - TV In The video information fed from the tuner located on the E-Board is input via pin 11, from here the video signal is fed to the VDP IC601 for further processing as well as being fed to either AV1 or AV2 terminals.
: Pin 14 - Main Y / V out
: Pin 20 - AV2 Cin
Pin 14 of the switching IC IC3401 outputs either the luminance component of an S-VHS source or a composite video signal which is then fed to the VDP pin 61 for further processing and viewing on screen.
The AV2 terminal allows the input of a chrominance signal via pin 15, fed from an S-VHS source which is input via pin 20 of IC3401. 9.3.2.
: Pin 15 - AV1 Vout
Video Switching Outputs
: Pin 13 - Main Cout
Pin 15 allows the output of a video signal which is then fed to pin 19 of the AV1 21 pin scart terminal.
The output via pin 13 is the chrominance signal fed from any of the chrominance inputs mentioned above. The chrominance signal output from pin 13 of IC3401 is fed to the base of buffer transistor Q3441, which is also used to detect the chrominance signal being
:
Pin 16 - AV2 Vout
Output from pin 16 of the switching IC IC3401 is a video signal which is fed to the AV2 21 pin scart terminal.
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9.4. Audio Switching Outline The audio switching is performed by IC3151 TEA6420. This switching matrix has the same features as the TEA6415 except that it contains a left
and right matrix with five inputs and four outputs. I2C bus 4 control is via pins 23 and 24.
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9.5. Audio Signal Source 9.5.1.
Audio Switching Inputs
monitor audio output terminal JK3403 located on the H-Board.
Signals input to the audio switching IC IC3151, are applied from a number of sources. These are shown below:
: Pin 21 - TV Rin The input at pin 21 sees the right audio signal output from the MSP IC2101 pin 27 (located on the E-Board), this right audio signal being fed to pin 1 of the 21 pin scart terminal, AV2. This right audio signal being accompanied by left audio signal (see pin 4)
: Pin 4 - TV-Lin The input at pin 4 sees the left audio signal output from the MSP IC2101 pin 28 (located on the E-Board), this left audio signal being fed to pin 3 of the 21 pin scart terminal, AV2. This left audio signal being accompanied by right audio signal (see pin 21)
9.5.2.
Audio Switching Outputs
: Pin 9 - AV1 Lout
: Pin 5 - Mon Lin
The left channel audio signal output from 9 is fed to the AV1 21 pin terminal pin 3.
Input at pin 5 is the left audio signal which is output from the MSP IC2101 pin 31 and which is output to both AV1 pin 3 of the 21 pin scart terminal. and the monitor audio output terminal JK3403 located on the H-Board.
: Pin 10 - AV1 Rout The right channel audio signal output from 10 is fed to the AV1 21 pin terminal pin 1.
: Pin 6 - AV2 Lin
: Pin 11 - AV2 Lout
This input is used for the left audio signal fed from the 21 pin scart terminal AV2 pin 6 (located on the H-Board). This left audio signal being accompanied by the right audio signal (see pin 19)
The selected left channel audio signal output from pin 11 of IC3151 is then fed to the 21 pin scart terminal pin 3 of AV2. : Pin 12 - AV2 Rout
: Pin 7 - DVB Lin
The selected right channel audio signal output from pin 12 of IC3151 is then fed to the 21 pin scart terminal pin 1 of AV2.
The left audio signal fed from the DVB decoder located on the V-Board is input to pin 7 of IC3151. This left audio signal being accompanied by the right audio signal (see pin 18)
: Pin 13 - Mon Lout This output is used to feed a left channel audio signal to the audio monitor output JK3403.
: Pin 18 - DVB Rin
: Pin 14 - Mon Rout
The right audio signal fed from the DVB decoder located on the V-Board is input to pin 18 of IC3151. This right audio signal being accompanied by the left audio signal (see pin 18).
This output is used to feed a right channel audio signal to the audio monitor output JK3403. : Pin 15 - AV2 / DVB Lout
: Pin 19 - AV2 Rin
This output of IC3151 is used to feed either the selected left channel audio signal fed from AV2 or the DVB decoder, to the MSP IC2101 (located on the E-Board) pin 41 for further processing.
This input is used for the right audio signal fed from the 21 pin scart terminal AV2 pin 2 (located on the H-Board). This right audio signal being accompanied by the left audio signal (see pin 19).
: Pin 16 - AV2 / DVB Rout
: Pin 20 Mon Rin
This output of IC3151 is used to feed either the selected right channel audio signal fed from AV2 or the DVB decoder, to the MSP IC2101 (located on the E-Board) pin 42 for further processing.
Input at pin 20 is the right audio signal which is output from the MSP IC2101 pin 30 and which is output to both AV1 pin 1 of the 21 pin scart terminal. and the
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