STM32 Seminar Peripherals
Agenda 09:00 09:30 09:40 09:45 10:30 11:30
Registration Introduction to ST STM32 Overview ARM – an introduction to Cortex-M3 STM32 Cortex-M3 Core and System Coffee
11:45 12:45
Hitex – Tools, DMA, RTOS Lunch
13:30 15:00 15:15 15:45 16:15
STM32 Peripherals Coffee STM32 Libraries examples and Usage STM32-Primer demo Summary, Questions, and Close
STM32 Seminar
8th October 2007
2
Agenda 09:00 09:30 09:40 09:45 10:30 11:30
Registration Introduction to ST STM32 Overview ARM – an introduction to Cortex-M3 STM32 Cortex-M3 Core and System Coffee
11:45 12:45
Keil Tools Lunch
13:30 15:00 15:15 15:45 16:15
STM32 Peripherals Coffee STM32 Libraries examples and Usage STM32-Primer demo Summary, Questions, and Close
STM32 Seminar
8th October 2007
3
STM32 Peripherals Communications Peripherals Analog to Digital Converter Timers Demo: USB Device Firmware Upgrade
STM32 Seminar
8th October 2007
4
STM32 Communication Peripherals
STM32 Seminar
8th October 2007
5
CORTEXM3 CORTEXM3 CPU CPU 72 72 MHz MHz
2 x SPI 2 x I2C 3 x USART CAN2.0B USB 2.0 Full Speed
JTAG/SW JTAG/SWDebug Debug Nested Nestedvect vectIT ITCtrl Ctrl 1x 1xSysTick SysTickTimer Timer DMA DMA 77Channels Channels
ARMLite LiteHi-Speed Hi-SpeedBus Bus ARM Matrix//Arbiter Arbiter(max (max72MHz) 72MHz) Matrix
Nine Communications Peripherals:
FlashI/F I/F Flash
STM32F10x Series Block Diagram 32kB-128kB 32kB-128kB Flash FlashMemory Memory 512kB 512kBto tocome come e/o 2007 e/o 2007
Power PowerSupply Supply Reg Reg1.8V 1.8V POR/PDR/PVD POR/PDR/PVD XTAL XTALoscillators oscillators 32KHz 32KHz++4~16MHz 4~16MHz
Up Upto to20kB 20kBSRAM SRAM 64kB 64kBto tocome comee/o e/o 2007 2007
Int. Int.RC RCoscillators oscillators 32KHz 32KHz++8MHz 8MHz
20B 20BBackup BackupRegs Regs
PLL PLL
Reset ResetClock Clock Control Control
RTC RTC//AWU AWU
ARM Peripheral Bus Bridge Bridge
Up Upto to16 16Ext. Ext.ITs ITs 32/49/80 32/49/80I/Os I/Os 1x 1xSPI SPI 1x 1xUSART/LIN USART/LIN Smartcard/IrDa Smartcard/IrDa Modem-Ctrl Modem-Ctrl
STM32 Seminar
3x 3x16-bit 16-bitTimer Timer
8th October 2007
(max 72MHz)
Synchronized SynchronizedAC AC Timer Timer
1x 1xUSB USB2.0FS 2.0FS
Bridge Bridge ARM Peripheral Bus
1x 1x16-bit 16-bitPWM PWM
(max 36MHz)
Independent Independent Watchdog Watchdog Window WindowWatchdog Watchdog
1x 1xbxCAN bxCAN2.0B 2.0B 2x 2xUSART/LIN USART/LIN Smartcard Smartcard//IrDa IrDa Modem ModemControl Control
2x 2x12-bit 12-bitADC ADC 16 channels 16 channels//1Msps 1Msps
1x 1xSPI SPI
Temp TempSensor Sensor
2 2x 2xII2CC
6
SPI Serial Peripheral Interface Two SPIs: SPI1 on high speed APB2 and SPI2 on low speed APB1 Up to 18 MHz data rate in either Master or Slave modes Full duplex and simplex synchronous transfers supported Programmable data frame size: 8/16-bit transfer frame format selection Programmable data order: MSB-first or LSB-first shifting Programmable clock polarity & phase Hardware or software nSS management Interrupt/DMA request generation: Tx Buffer Empty, Rx Buffer Not Empty, Bus Fault, Overrun
Hardware CRC support: CRC8 / CRC16-CCITT standard
STM32 Seminar
8th October 2007
7
SPI Data Frame Format Programmable data frame size: 8 or 16-bit frame format Programmable data order: MSB or LSB-first
0xD7
MSB first
0xD7
LSB first
8-bit long
Master SCK MISO MOSI
VDD
NSS
0xD739
MSB first
0xD739
LSB first
16-bit long
STM32 Seminar
8th October 2007
8
SPI Full Duplex Communication Standard full duplex 3-wire transfer
Slave
Master SCK
SCK
MISO
MISO
MOSI NSS
MOSI VDD NSS
Full Duplex
STM32 Seminar
8th October 2007
9
SPI Simplex Communication Simplex modes for pin saving Bi-directional: two wire, direction control bit Slave Rx-Only: two wire, uni-directional
Slave
Master
Slave
Master
SCK
SCK
SCK
SCK
MISO
MISO
MISO
MISO
MOSI
MOSI
MOSI NSS
VDD NSS
NSS
NSS
Bi-directional
STM32 Seminar
MOSI VDD
Rx Only
8th October 2007
10
(Slave)
SPI NSS Hardware & Software Management Hardware NSS
Software NSS
Slave
Slave
Full Duplex pin saving mode Frees Master and Slave NSS pins SCK MISO MOSI NSS
SCK MISO MOSI NSS
Dynamic Master/Slave reconfiguration
VDD SCK MISO MOSI NSS
SCK MISO MOSI NSS
Master
Master
STM32 Seminar
8th October 2007
11
SPI Single Master: SS Output Management
Slave
Slave Each device can be a unique
Enable SS output capability
master by enabling its NSS as output and driving it low: all
SCK MISO MOSI NSS
SCK MISO MOSI NSS
other devices became slaves.
No need for external GPIO pin to drive slaves NSS pins SCK MISO MOSI NSS
SCK MISO MOSI NSS
Master
Slave
STM32 Seminar
8th October 2007
12
SPI SD/MMC Card Support Basic SD/MMC support (SPI protocol): Performance: speed up to 18MHz Error checking: hardware CRC calculation VDD
VDD R = 4.7 K
Ω
MISO SCK MOSI
9
CS
1 2 3 4 5 6 78
Master
STM32 Seminar
8th October 2007
13
SPI CRC Calculation Example of n data transfer between two SPIs followed by the CRC transmission of each one in Full-duplex mode
Taken from SPI1 TXCRC register and sent to SPI2
MOSI
Data 1
Data 2
…
Data n
CRC[1..n] Taken from SPI2 TXCRC register and sent to SPI1
MISO
Data’ 1
Data’ 2
…
Data’ n
CRC’[1..n]
SCK
STM32 Seminar
8th October 2007
14
Inter Integrated Circuit (I2C)
STM32 Seminar
8th October 2007
15
I2C Features (1/3) Multi-Master and Slave capability Controls all I²C bus specific sequencing, protocol, arbitration and timing Standard and fast I²C modes (up to 400kHz) 7-bit and 10-bit addressing modes Clock stretching supported Dual addressing capability to acknowledge 2 slave addresses Configurable PEC (Packet Error Checking) Generation or Verification: PEC value can be transmitted as last byte in Tx mode PEC error checking for last received byte
STM32 Seminar
8th October 2007
16
I2C Features (2/3) Error flags: Arbitration lost condition for master mode Acknowledgement failure after address/ data transmission Detection of misplaced start or stop condition Overrun/Underrun if clock stretching is disabled
2 Interrupt vectors: 1 Interrupt for successful address/ data communication 1 Interrupt for error condition
SMBus 2.0 (System Management Bus) Compatibility – http://smbus.org PMBusTM (Power Management Bus) Compatibility – http://pmbus.org
STM32 Seminar
8th October 2007
17
I2C Features: DMA (3/3) DMA supported for TX and RX Requests mapped on separate DMA channels, supporting simultaneous bidirectional transfers Calculated PEC value is automatically transmitted at end of frame
STM32 Seminar
8th October 2007
18
I2C Dual Addressing Mode
I2C supports dual addressing capability to acknowledge 2 slave addresses
VDD
Slave
Master
Slave
SDA
SDA
address1
SCL
SCL
Slave address2
STM32 Seminar
8th October 2007
19
I2C SMBus Mode Intel System Management Bus SMBus 2.0 Compatibility Low cost, more robust than standard I²C Clock stretching support for different speed devices Timeout: 25ms clock low timeout delay H/W Packet Error Checking (PEC) with ACK control Address Resolution Protocol (ARP) supported SMBALERT# line for interrupts Host Notify Protocol
STM32 Seminar
8th October 2007
20
Universal Synchronous Asynchronous Receiver Transmitter (USART)
STM32 Seminar
8th October 2007
21
USART Features (1/2) Three USART: USART1 High speed APB2 and USART2/3 on Low speed APB1 Fully-programmable serial interface characteristics: 8 or 9 bit data Even, odd or no-parity generation and detection 0.5, 1, 1.5 or 2 stop bits Programmable fractional baud rate generator (12-bit Integer, 4-bit Fraction) Hardware flow control (CTS and RTS)
Dedicated transmission and reception flags (TxE and RxNE) with interrupt capability Support for DMA Receive DMA request
Up to 4.5 Mbps
Transmit DMA request
STM32 Seminar
8th October 2007
22
USART Features (2/2) 10 interrupt sources to ease software implementation LIN Master/Slave compatible Synchronous Mode: Master mode only IrDA SIR Encoder Decoder Smartcard Capability Single Wire Half Duplex Communication Multi-Processor communication USART can enter Mute mode Mute mode: disable receive interrupts until next header detected Wake up from mute mode (by idle line detection or address mark detection)
STM32 Seminar
8th October 2007
23
USART DMA Capability DMA supported for TX and RX Requests mapped on separate DMA channels, supporting simultaneous bidirectional transfers
STM32 Seminar
8th October 2007
24
USART Synchronous Mode USART supports Full duplex synchronous communication mode Full-duplex, three-wire synchronous transfer USART Master mode only Programmable clock polarity (CPOL) and phase (CPHA) Programmable Last Bit Clock generation Transmitter Clock output (SCLK)
Slave
Master SCK
SCLK Rx
MISO
Tx
MOSI
USART
NSS
SPI
Full Duplex STM32 Seminar
8th October 2007
25
USART Single Wire Half Duplex mode USART supports Half duplex synchronous communication mode Only Tx pin is used (Rx is no longer used)
Used to follow a single wire Half duplex protocol.
VDD
Ω
USART2
R = 10 K
USART1 Tx
Tx
Half Duplex
STM32 Seminar
8th October 2007
26
USART Smart Card mode USART supports Smart Card Emulation ISO 7618-3 Half-Duplex, Clock Output (SCLK) 9Bits data, 0.5 Stop Bit in receive, 1.5 Stop Bits in transmit Parity Error Generation with NACK transmission Programmable Guard Time Programmable Clock Prescaler to guarantee a wide range clock input
USART Tx
SCLK
STM32 Seminar
8th October 2007
27
USART IrDA SIR Encoder Decoder USART supports the IrDA Specifications Half-duplex, NRZ modulation, Max bit rate 115200 bps 3/16 bit duration for normal mode Low power mode: 1.42MHz
