N5416A Automated USB 2.0
Pre--Compliance Test Solutions Pre
Today’s Schedule USB 2.0 Overview USB 2.0 Compliance Testing Examples of Compliance Tests Demo of the Agilent Solution Q&A
USB 2.0 Overview USB Integrators’ Forum Created by Compaq, HewlettPackard, Intel, Lucent, Microsoft, NEC and Philips
The USB-IF (www.usb.org) governs the specification and use of USB, and resolves any issues that arise
USB 2.0 Overview Data Rates USB Peripherals can be Host, Device or Hub The USB-IF combined all USB 1.1 and 2.0 speed buses into the USB 2.0 specification USB 2.0 consists of 3 modes-Low-speed (LS) Full-speed (FS) High-speed (HS)
Data Rates 1.5 Mb/s 12 Mb/s 480 Mb/s
USB 2.0 now offer Host/Device Dual Role Peripherals This capability is referred as OTG
Rise Times 75ns – 300ns 4ns – 20ns 500ps
USB 2.0 Overview Physical Characteristics Cables can be up to 5m long; hubs up to 5 levels deep Downstream data flows from PC to peripherals Upstream data flows from peripherals to PC USB Cable + Shield
VBUS D+ DGround
USB 2.0 Overview Signal Levels Signal Level Transfer Full/Low Speed 3.3V, 12/1.5Mbps High Speed 400mV, 480Mbps Required bandwidth BW = 0.35/Tr= ~1 GHz (Tr = ~400 ps)
USB 2.0 Overview Path Impedances Characteristic measurements during mechanical test (High/Full speed cables Characteristic Impedance Differential 90 15% Common Mode 30 30% Cable Attenuation
5.8dB @ 400MHz
Propagation Delay
26ns
D+/D- Propagation Skew 100ps
USB 2.0 Overview Transmission Modes Full Speed and Low Speed modes are determined by the location of the Rpu resistor (on D+ or D-). The bus starts in full speed mode using the Rpu resistor After Chirp Handshake, if high speed mode is available, the Rpu resistor is disconnected and bus changes to high speed mode.
USB 2.0 Overview Full Speed Packet Makeup Packet 1
SYNC
PID(SOF)
Frame No. CRC EOP
Packet 2
SYNC
Packet 3
PID(IN) ADDR ENDP CRC EOP
frame
SYNC PID(NAK) EOP
USB 2.0 Overview High Speed Packet Makeup Signal Amplitude 400mV SYNC: 32(Minimum 12) bit Idle : SE0 EOP re-definition: NRZ 01111111 w/o bit stuffing (SOF EOP is 40 bit) SYNC
PID(IN) ADDR ENDP CRC
EOP
Today’s Schedule USB 2.0 Overview USB 2.0 Compliance Testing Examples of Compliance Tests Demo of the Agilent Solution Conclusion Q&A
USB 2.0 Compliance Testing Involves a set of test procedures (available from www.usb.org) performed in a specific order The USB 2.0 HS test procedure (v1.0) has been available since December 2001 The USB-IF performs the official compliance testing
USB 2.0 Compliance Testing Interoperability Test
USB 2.0 Compliance Testing Electrical Tests Full/Low speed signal quality In-rush current Droop/Drop Backdrive voltage High speed test OTG Specific Tests
FS/LS
HS
USB 2.0 Compliance Testing Required Test Software
INTEL HS Electrical Test Tool
In order to place your USB 2.0 Device in Test Modes you will need Intel HS Electrical Test Tool installed on a Windows based PC. Full Speed Tests requires Loop Descriptor Mode High Speed Test requires HS Test Packets Mode
USB 2.0 Compliance Testing Full/Low Speed Tests Signal quality In-rush current Droop/Drop Backdrive voltage
USB 2.0 Compliance Testing Full/Low Speed Signal Quality
USB Test Process 1. Connect Probe to Test Fixture 2. Connect device to Test Fixture 3. Place Device in Loop Descriptor test Mode 3. Select Proper Test in N5416A Script 4. Run Test
USB 2.0 Compliance Testing DEVICE Upstream Host / System
Up stream Hub
USB System (PC) HUB
Oscilloscope
HUB
HUB
Adjacent Device
HUB
Devices
In FS tests, connect D+ of the adjacent device to scope ch 3 Connect D+ to ch 2 Connect D- to ch 1
HUB
DUT SQiDD
5m cable
USB 2.0 Compliance Testing Full/Low Downstream Setup
USB 2.0 Compliance Testing Upstream Trigger Setup
The logic trigger occurs when the EOP is reached and the Adjacent device is idle (Trigger Setup is done automatically)
USB 2.0 Compliance Testing Measurement Data Automated Measurement Setup & Result
USB 2.0 Compliance Testing Full Speed Test Results Example Signal eye: *** eye failure! (14 data points violate eye) *** *** waiver granted. *** EOP width: 170.2029ns EOP width passes Consecutive jitter range: -1703.52ps to 2268.87ps RMS jitter 576.53ps Paired KJ jitter range: -584.58ps to 0.00ps, *** jitter failure *** *** waiver granted ***
USB 2.0 Compliance Testing Understanding Full Speed Test Results Measurement Items: D+ Dcommon mode voltage crossover location eye diagram ref. eye violation
green blue purple yellow diamond yellow circle red dots
USB 2.0 Compliance Testing Device Inrush Current Test Types of Devices Tested Bus powered devices Self-powered devices Vbus
attach >120µf GND
=2GHz
USB 2.0 Compliance Testing High Speed Test High Speed Signal Quality Time Domain Reflectometry( TDR ) Reciever Sensitivity and Squelch J and K Voltage CHIRP Packet Parameters Suspend/Resume
USB 2.0 Compliance Testing HS Electrical Test Tools The test mode can be any of the following: Test J Test K Test _SE0_NAK Test Packet Test Force Enable
USB 2.0 Compliance Testing HS Signal Integrity Test packet output by HS Electrical Test Tool The signal is isolated from the host by the HS Test Fixture Waveform is measured through a 90 ohm differential termination
Differential Probe
HS Relay
90Ω 90 Ω
Device
USB 2.0 Compliance Testing Measuring High Speed Signal Quality Test packet output
USB 2.0 Compliance Testing HS Signal Quality Test Results Required Tests Overall result: pass! Signal eye: eye passes EOP width: 7.98 bits EOP width passes Receivers: reliable operation on tier 6 receivers pass Measured signaling rate: 480.0641MHz signal rate passes
USB 2.0 Compliance Testing Device HS Signal Quality EL_2
Data rate specification (480 Mb/s 0.05%)
EL_4
TP3 eye pattern requirement
EL_5
TP2 eye pattern requirement (device with captive cable)
EL_6
10-90% differential rise/fall times (longer than 500ps)
EL_7
Monotonic data transitions for high speed drivers in the eye pattern template
USB 2.0 Compliance Testing HS Packet Parameters The device is controlled by the Electrical Test Tool on the PC The reply packet from the device is received and evaluated for: Sync EOP Spacing between packets
USB 2.0 DEVICE Compliance Testing HS Packet Parameters Sync Field : 32 bit
EOP : 8 bit
USB 2.0 DEVICE Compliance Testing CHIRP, SUSPEND/RESUME/RESET Timing
USB Test Fixture
Probe Probe 90Ω 90 Ω
Device
USB 2.0 DEVICE Compliance Testing CHIRP Test Reset duration CHIRP K Duration HS termination assertion
Device’s Chip Latency (2.5us 3ms)
Device turns on HS termination Chirp KJKJKJ (500us)
CHIRP K (1ms 7ms)
USB 2.0 DEVICE Compliance Testing CHIRP Test
Device’s Chip Latency (2.5us 3ms)
Enable High Speed Termination After Chirp KJKJKJ (within 500us)
USB 2.0 DEVICE Compliance Testing Suspend Timing
Suspend : 3.000ms 3.125ms D+ Voltage > 2.7V
USB 2.0 DEVICE Compliance Testing Resume Timing
Resume : < 2 bit time
USB 2.0 DEVICE Compliance Testing Reset Timing
Device CHIRP K
Reset : 3.1ms 6ms
USB 2.0 DEVICE Compliance Testing Reset Timing
Reset from Suspend : 2.5us 3.000ms
USB 2.0 DEVICE Compliance Testing High Speed Receiver Sensitivity Automated control
Pulse Generator
SMA
Device
HS Relay
In SE0_NAK test mode, pulse generator outputs IN token; device must not respond to tokens 150mV
USB 2.0 DEVICE Compliance Testing High Speed Receiver Sensitivity
Data generator Packet
Device response Packet
USB 2.0 DEVICE Compliance Testing High Speed Receiver Sensitivity Note: A waiver may be granted if the receiver does not indicate squelch at +/-50mV of 150mV differential amplitude
USB 2.0 DEVICE Compliance Testing Time Domain Reflectometry Confirm the signal is less than 10mV
TDR
Use TDR to measure impedance of connector, circuit board, and active termination SMA HS Relay
DEVICE
USB 2.0 DEVICE Compliance Testing TDR Test Results 70
ZHSTHRU
110
80
ZHSTERM
100
Differential impedance USB Connector
Termination impedance
Thru impedance D- odd impedance D+ odd impedance
Today’s Schedule USB 2.0 Overview USB 2.0 Compliance Testing Examples of Compliance Tests Demo of the Agilent Solution Conclusion Q&A
Examples of Compliance Tests Test Example 1: Impedances The effects of source and termination impedances A(w H(w)
ZS
R1(w)
T(w)
Z0 H(w)
R2(w) ZL
Unregulated output impedance of a driver could cause significant overshoot or undershoot
Examples of Compliance Tests Test Example 2: Full Speed *** Overall result: fail! *** Signal eye: *** eye failure! *** (33 data points violate eye)
USB OTG Compliance Testing Get Completely Automated Certification of USB OTG Peripherals N5416A Software provides Automated control of: N5417A USB OTG Test Fixture to sequence tests E3631A Power Supply 34401A Voltmeter. Equipment list for complete Automation: Agilent Oscilloscope with >=2GHz BW N5416A USB Compliance software 2 High Impedance Passive Probes 82357B USB->GPIB Adapter or equiv. Agilent E3631A Powersupply or equiv. Agilent 34401A Multimeter or equiv. GPIB Cable 10833B or equiv.
Examples of Compliance Tests Test Example 2: A Detailed Look Coupling between D+ and D-
Examples of Compliance Tests Cautions with USB 2.0 Measurements Hub quality can affect full/low speed upstream measurements For identical measurements to those in compliance tests, use Intel’s CHUB For high speed signal quality measurements, take care in handling low level signals. Be careful of: Adjusting the offset and performing calibration Effects of fixturing impedance on signal quality The bandwidth of the probe
Today’s Schedule USB 2.0 Overview USB 2.0 Compliance Testing Examples of Compliance Tests Demo of the Agilent Solution Conclusion Q&A
Today’s Schedule USB 2.0 Overview USB 2.0 Compliance Testing Examples of Compliance Tests Demo of the Agilent Solution Conclusion Q&A
Conclusion Summary Compliance testing is a requirement Compliance testing involves framework layer evaluation and physical layer evaluation In physical layer evaluation, signal quality is influenced by components, circuit layout, and driver circuitry An easy-to-use oscilloscope is an important factor in efficiently performing compliance testing
Conclusion Reference Material Universal Serial Bus Specification
Rev 2.0 (USB-IF)
USB-IF Signal Integrity Test Description (USB-IF) USB Design by Example (John Hyde, John Wiley & Sons INC) Universal Serial Bus System Architecture (Don Anderson, MINDSHARE INC) USB 2.0 High Speed Electrical Test Procedure v1.0
Recommanded USB 2.0 Test Configurations DSO90254A Agilent 2.5GHz Oscilloscope (or DSO80204A/B or 54852A) N5416A USB 2.0 Compliance test Application High Speed Tests: 5 Self Powered High Speed USB Hubs + 5m USB Cables E2649B USB 2.0 HS Test Fixtures 1130A 1.5GHz Differential Probe +E2678A Socket-in Probe Head 81134A Pulse Pattern Generator (optional for Squelch Test) OTG Tests: N5417A USB 2.0 OTG Automated Test Fixture 82357A/B USB to GPIB Interface (Optional) 34401A Voltmeter (Optional) E3631A Power Supply (Optional) 10833B GPIB Cable (Optional) Low/Full Speed Tests: 1 Self Powered FULL Speed USB Hub 4 Self Powered High Speed USB Hubs + 5m USB Cables E2646A LS/FS USB Test Fixture 3 High Impedance Passive Probes or 3 Single Ended Active Probes USB Powered Devices/HUB Inrush Current -> N2774A Current Probe +N2775A Probe PSU
Today’s Schedule USB 2.0 Overview USB 2.0 Compliance Testing Examples of Compliance Tests Demo of the Agilent Solution Conclusion Q&A
