PLCs and Other Logic Devices
5
5.1 BINARY LOGIC DIAGRAMS FOR PROCESS OPERATIONS 880 1. Purpose 880 2. Scope 880 3. Use of Symbols 880 4. Symbols 881 Appendix A: General Application Example 888 A1. Introduction 888 A2. Simplified Flow Diagram 888 A3. Word Description 888 A4. Logic Diagram 890 Appendix B: Complex Time-Element Example 891 B.1 Word Description 891 Appendix C: Loss of Power Supply for Memory 891 Bibliography 892 5.2 LADDER DIAGRAMS
893
Introduction 893 Ladder Diagram Symbols 893 Developing a Ladder Diagram 894 Automatic Mode of Operation 895 Summary 895 Ladder Diagram Analysis 895 Start-Up and Shutdown 896 Dynamic Breaking of a Motor 896 Fail-Safe Design 897 Documentation 897 Conclusions 897 Bibliography 897
5.3 OPTIMIZATION OF LOGIC CIRCUITS
898
Optimization Building Blocks 898 Graphic Logic Functions 900 Ladder Diagrams from Logic Diagrams 901 Optimized Logic Circuit Construction 901 Logic Circuit Synthesis 902 Logic Simplification with Boolean Algebra 903 Logic Simplification through Logic Maps 903 Negative vs. Positive Logic Usage 904 Summary 904 Bibliography 905 5.4 PLCs: PROGRAMMABLE LOGIC CONTROLLERS
906
Introduction 907 History 907 PLC Sizes 909 Nano PLCs 909 Basic PLC Components 909 Central Processor Unit (Real Time) 910 Memory Unit 910 I/O Systems 912 PLC Power Supply 915 Additional PLC Components 915 Communications Modules 915 Remote I/O 915 Peer-to-Peer Communications 916 Peripheral Devices 917 Local Operator Interface 917 Human-Machine Interface 918 Printers 919 877
© 2006 by Béla Lipták
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PLCs and Other Logic Devices
Programmers and Workstations 919 Justification for the Use of PLCs 920 PLCs vs. Relays and Stand-Alone Controllers 920 PLC vs. DCS 921 PLC vs. Personal Computers 922 Summary 922 Project Execution 923 Systems Analysis 923 Open Systems 925 PLC Hardware, System Sizing, and Selection 926 PLC Installation and Panel Design 928 Software (Program) Development 932 Software/Hardware Integration 938 System Checkout and Start-Up 939 After Start-Up 939 Conclusion 940 References 940 Bibliography 941 5.5 PLC PROGRAMMING
Ladder Logic Advances 968 Program Flow Modification 968 Indirect Addressing 969 Assembly Language-Like Extensions 971 Communication with Intelligent Devices 971 Fast I/O Updating Methods 972 Graphic, Flowchart-Like Languages 972 IEC 61131-3 PLC Language Standard 973 Conclusion 974 References 974 Bibliography 975 5.7 PRACTICAL LOGIC DESIGN
Design Philosophy 976 Open/Close Valves 976 Definitions 976 Auto Mode 978 Motor-Operated Valves 979 Failure Logic 979 Solenoid Valves 981 Pumps 981 Definitions 981 Auto Mode 983 Pump Fail 984 Other Common Problems with Pump Logic Design 984 Pumps with Two Outputs 984 Controlling Two Pumps Together 984 Breakers 986 Analog Controls 986 Switchover 986 Pop Open/Clamp Closed 986 Override Open and Close 988 Feedforward 988 Cascade 989 Three-Transmitter Select 989 Switch to Manual Mode 990 Changing the Set Point with Changes in the Number of Pumps Running 990 Start-Up and Shutdown Sequences 990 Operation and Customization 992 A Note on Safety 992 Bibliography 992
944
Introduction 944 What Is a PLC? 944 System Hardware and Operation 944 Programming Languages 946 Instruction List 946 Structured Text 946 Sequential Function Charts 946 Function Block Diagrams 947 Ladder Logic Programming 947 Ladder Logic Structure 947 Ladder Logic Programming Basic Instructions 948 Memory Structure 952 Ladder Logic Programming Devices 953 Programming Considerations 953 Program Documentation 954 PLC Hardware Configuration 954 Ladder Program Structure 955 Typical GE Fanuc PLC 955 Typical Allen-Bradley PLCs 956 Typical Modicon PLC 984 958 Access and Programming Modes 958 Developing the PLC Program Logic 960 Testing and Simulation 962 Advances in Programming 964 Reference 965 Bibliography 965 5.6 PLC SOFTWARE ADVANCES
© 2006 by Béla Lipták
5.8 PROGRAMMABLE SAFETY SYSTEMS
966
Introduction 966 Graphic Description of Control Requirements
976
966
993
Introduction 993 Risk Reduction 994 History 994 Safety Standards 996 IEC 61508: General Safety Standard 996 IEC 61511: Safety Standard for Process Industries 996
Contents of Chapter 5
ANSI/ISA-84.01 Standard 997 Management Considerations 999 Hazard and Risk Analysis 999 As Low as Reasonably Practicable (ALARP) 999 Required Safety Integrity Level 999 Semi-Quantitative Risk Analysis Techniques 1001 Risk Graphs 1001 Safety System Certification 1001 Major Trends 1003 Overall Safety 1003 Separation from the Control System 1003 Flexibility and Scalability 1003 Function Blocks 1004 Safety System Selection 1004 Acknowledgments 1004 Acronyms 1004 References 1005 Bibliography 1005 5.9 RELAYS
1006
Introduction 1007 Relay Types and Features 1007 Special Relays 1007 Relay Characteristics 1008 Rating, Size, and Other Selection Criteria Contact Configurations 1008 Mechanical Structures 1009 Contact Materials 1010 Contact Shape and Mounting 1011 Selection and Application 1011 Selection 1011 Relative Costs 1012 Relays vs. Solid-State Devices 1012 Electromechanical Advantages 1012 Solid-State Advantages 1013 Conclusions 1013 Bibliography 1013 5.10 SOLID-STATE LOGIC ELEMENTS
5.11 SYSTEM INTEGRATION: COMPUTERS WITH PLCS 1023 Introduction 1023 PCs for Programming the PLC 1024 PCs for Monitoring and Supervising the PLC 1024 SCADA System 1024 Handling of Tasks 1025 Implementation 1025 Serial Link 1025 Communication Networks 1025 Performance 1027 Generation Time (Tg) 1027 Transmission Time (Tt ) 1027 Te, Tr, and Trd 1028 Conclusions 1028 References 1028 Bibliography 1028 5.12 TIME DELAY RELAYS
1030
General Characteristics 1031 Timer Modes and Characteristics Types of Time Delays 1032 Types of Designs 1033 Bibliography 1035 5.13 TIMERS AND PROGRAMMING TIMERS
1015
Introduction 1015 Analog Circuit Elements 1016 Transistor Switch 1016 Diodes and Their Switching 1017 Transistors 1017 Integrated Circuit Elements 1018 Families of IC Switching 1018 Applications 1020 Merging Human and Instrument Inputs Time Synchronization 1020
© 2006 by Béla Lipták
1008
Implementation Options 1021 Solid-State Logic Options 1021 Bibliography 1022
1020
1031
1036
Introduction 1036 Mechanical Timers and Sequencers 1036 Cam Timers 1036 Band or Drum Programmers 1037 Punched-Card Programmers 1037 Timers 1037 One-Shot Timers 1037 Monostable and Astable Designs 1037 Delay on Break 1038 555 Devices 1039 Hybrid Timing Circuits 1039 Digital Sequencers 1040 Asynchronous Sequencers 1041 Electronic Sequencers 1042 Conclusions 1042 Bibliography 1042
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5.1
Binary Logic Diagrams for Process Operations Standard formatted for publication in this handbook by:
J. E. JAMISON
(2005)
Reprinted by permission. Copyright © 1976, Instrument Society of America. From ANSI/ISA-S5.2-1976 (R 1992), ‘‘Binary Logic Diagrams for Process Operations,’’ reaffirmed July 13, 1992. Also, permission was granted by ISA for inclusion of the latest thinking on binary logic, memory, and time functions from Draft 4 of ISA Draft 1 5.01.01 Instrumentation Symbols and Identification, Copyright 2000 ISA, which now includes the previous S5.2.
1. PURPOSE 1.1 The purpose of this Standard is to provide a method of logic diagramming of binary interlock and sequencing systems for the start-up, operation, alarm, and shutdown of equipment and processes in the chemical, petroleum, power generation, air conditioning, metal refining, and numerous other industries. 1.2 The Standard is intended to facilitate the understanding of the operation of binary systems and to improve communications among technical, management, design, operating, and maintenance personnel concerned with the systems. 2. SCOPE 2.1 The Standard provides symbols, both basic and nonbasic, for binary operating functions. The use of symbols in typical systems is illustrated in the appendices. 2.2 The Standard is intended to symbolize the binary operating functions of a system in a manner that can be applied to any class of hardware, whether it be electronic, electrical, fluidic, pneumatic, hydraulic, mechanical, manual, optical, or other. 3. USE OF SYMBOLS 3.1 By using the symbols designated as “basic,” logic systems may be described with the use of only the most fundamental logic building blocks. The remaining symbols, not basic, are more comprehensive and enable logic systems to be diagrammed more concisely. Use of the nonbasic symbols is optional. 3.2 A logic diagram may be more or less detailed depending on its intended use. The amount of detail in a logic diagram depends on the degree of refinement of the logic and on whether auxiliary, essentially nonlogic, information is included.
As an example of refinement of detail: A logic system may have two opposing inputs, e.g., a command to open and a command to close, which do not normally exist simultaneously; the logic diagram may or may not go so far as to specify the outcome if both the commands were to exist at the same time. In addition, explanatory notes may be added to the diagram to record the logic rationale. Nonlogic information may also be added, if desired, e.g., reference document identification, tag numbers, terminal markings, and so on. In these ways, the diagram may provide the level of detail appropriate, for example, for communication between a designer of pneumatic circuits and a designer of electric circuits, or may provide a broad-view system description for a plant manager. 3.3 The existence of a logic signal may correspond physically to either the existence or the nonexistence of an instrument signal, depending on the particular type of hardware 2 system and the circuit design philosophy that are selected. For example, a high-flow alarm may be chosen to be actuated by an electric switch whose contacts open on high flow; on the other hand, the high-flow alarm may be designed to be actuated by an electric switch whose contacts close on high flow. Thus, the high-flow condition may be represented physically by the absence of an electric signal or by the presence of the electric signal. The Standard does not attempt to relate the logic signal to an instrument signal of any specific kind. 3.4 A logic symbol that is shown in Section 4 with three inputs—A, B, and C —is typical for the logic function having any number of two or more inputs. 3.5 The flow of intelligence is represented by lines that interconnect logic statements. The normal direction of flow is from left to right, or top to bottom. Arrowheads may be added to the flow lines wherever needed for clarity and shall be added to lines whose flow is not in a normal direction. 2
1
A disclaimer to any future ISA Standards documents is hereby stated. The reader is cautioned that the Draft ISA Document that provided Table 5.1a has not been approved as of the time of this writing. Therefore, it cannot be presumed to reflect the position of ISA or any other committee, society, or group.
880 © 2006 by Béla Lipták
In process operations, binary instrument signals are commonly either ON or OFF. However, as a more general case, logic systems exist that make use of binary hardware having signals with two alternate real values, e.g., +5 V and –3 V. In positive logic, the more positive signal, +5 V, represents the existence of a logic condition, e.g., pump stopped. In negative logic, the less positive signal, –3 V, represents the existence of a logic condition of pump stopped.
5.1 Binary Logic Diagrams for Process Operations
3.6 A summary of the status of an operating system may be put in the diagram wherever it is deemed useful as a reference point or landmark in the sequence. 3.7 There may be misunderstanding of binary logic statements involving devices that are not recognizable as inherently having only two specific alternative states. For example, if it is stated that a valve is not closed, this could mean either (a) that the valve is open fully, or (b) that the valve is simply not closed, namely, that it may be in any position from almost closed to wide open. To aid accurate communication between writer and reader of the logic diagram, the diagram should be interpreted literally. Therefore, possibility (b) is the correct one. If a valve is an open-close valve, then, to avoid misunderstanding, it is necessary to do one of the following: 1. Develop the logic diagram in such a way that it says exactly what is intended. If the valve is intended to be open, then it should be so stated and not be stated as being not closed. 2. Have a separate note specifying that the valve always assumes either the closed or the open position. By contrast, a device such as a motor-driven pump is either operating or stopped, barring some special situations. To say that the pump is not operating usually clearly denotes that it has stopped. The following definitions apply to devices that have open, closed, or intermediate positions. The positions stated are nominal to the extent that there are differential-gap and dead band in the instrument that senses the position of the device. Open position: a position that is 100% open. Not-open position: a position that is less than 100% open. A device that is not open may or may not be closed. Closed position: a position that is 0% open. Not-closed position: a position that is more than 0% open. A device that is not closed may or may not be open. Intermediate position: a SPECIFIED position that is greater than 0% and less than 100% open. Not-at-intermediate position: a position that is either above or below the SPECIFIED intermediate position. For a logic system having an input statement that is derived inferentially or indirectly, a condition may arise that will lead to an erroneous conclusion. For example, an assumption that flow exists because a pump motor is energized may be false because of a closed valve, a broken shaft, or other mishap. Factual statements, that is, statements based on positive measurements that a certain condition specifically exists or does not exist, are generally more reliable. 3.8 A process operation may be affected by loss of the 3 power supply to memories and to other logic elements. In order to take such operating eventualities into account, it may therefore be necessary to consider the effect of loss of power to any logic component or to the entire logic system. In such
© 2006 by Béla Lipták
881
cases, it may be necessary to enter power supply or loss of power supply as logic inputs to a system or to individual logic elements. For memories, the consideration of power supply may be handled in this manner or as shown in sections 10–12 in Table 5.1a. By the same token, it may be necessary to consider the effect of restoration of power supply. Logic diagrams do not necessarily have to cover the effect of logic power supplies on process systems but may do so for thoroughness. 3.9 It is recommended, for clarity, that a single timefunction symbol, as appropriate, be used to represent each time function in its entirety. Though not incorrect, the representation of a complex or uncommon time function by using a time-function symbol in immediate sequence with a second time-function symbol or with a NOT symbol should be avoided (see Table 5.1a). 3.10 Process instrument symbols and designations follow ANSI/ISA Standard S5.1-1984 (formerly American National Standards Institute Standard Y32.20-1975), “Instrumentation Symbols and Designations.” However, these symbols are included for illustrative purposes only, and are not part of Standard S5.2. 3.11 If a drawing, or set of drawings, uses graphic symbols that are similar or identical to one another in shape or configuration and that have different meanings because they are taken from different standards, then adequate steps shall be taken to avoid misinterpretation of the symbols used. These steps may be to use caution notes or reference notes, comparison charts that illustrate and define the conflicting symbols, or other suitable means. This requirement is especially critical if the graphic symbols used, being from different disciplines, represent devices, conductors, flow lines, or signals whose symbols, if misinterpreted, may result in danger to personnel or damage to equipment. 4. SYMBOLS The symbols for diagramming binary logic are defined in Table 5.1a and are the latest thinking of the ISA SP5.1 subcommittee: The symbols in Table 5.1a are never used in piping and instrument diagrams (P&IDs) and are used to help document and diagram logic control designs and narratives. The present Standard ISA S5.2 (ANSI/ISA-S5.2-1976(R1992) is now being revised and rolled into the new ANSI/ISA-5.01.01 standard as proposed in the current (as of this writing) Draft 4. Symbols, Truth Tables, Definitions, and Graphs used here in Section 5.1 are in accordance with Draft 4 and are very different from S5.2. These are given here to illustrate to the reader the latest thinking in this area, including expanded timing functions. Application information and examples on 3
The term “power supply” covers the energizing medium, whether it be electric, pneumatic, or other.
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PLCs and Other Logic Devices
TABLE 5.1a Instrument and Control System Functional Diagramming Symbols-Binary Logic, Memory, and Time Functions (Proposed for the next revision of ISA S5.1 (now ANSI/ISA-5.01.01) at the time of this writing)
No
Symbol
Definition
Truth Table
Graph
01 A B C
A N D
x
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
02
1. AND gate. 2. Output true only if all inputs are true.
A 0 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1
B 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1
O
C 0 0 0 1 0 0 1 0 1 0 1 1 0 1 1 1
x 0 0 0 0 1 0 0 1 0 1 1 0 1 1 1 1
O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
1 0
A B C X O 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
t
1. OR gate. 2. Output true if any input is true.
A B C
OR
O
x
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
© 2006 by Béla Lipták
A 0 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1
B 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1
C 0 0 0 1 0 0 1 0 1 0 1 1 0 1 1 1
x 0 0 0 0 1 0 0 1 0 1 1 0 1 1 1 1
O 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0
A B C X O 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
t
5.1 Binary Logic Diagrams for Process Operations
883
TABLE 5.1a (continued) Instrument and Control System Functional Diagramming Symbols-Binary Logic, Memory, and Time Functions (Proposed for the next revision of ISA S5.1 (now ANSI/ISA-5.01.01) at the time of this writing)
No 03
Symbol
Definition
Truth Table
Graph
A B C
≥n
O
1. Qualified OR gate with greater than or equal to qualifications. 2. Output equals “1” if number of inputs equal to “1” are greater than or equal to “n” inputs. 3. Truth table and graph are for “n” equals 2.
x
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
04
A 0 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1
B 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1
A B C
C 0 0 0 1 0 0 1 0 1 0 1 1 0 1 1 1
x 0 0 0 0 1 0 0 1 0 1 1 0 1 1 1 1
>n
O 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
O
1 0
A B C X O 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
t
1. Qualified OR gate with greater than qualifications. 2. Output equals “1” if number of inputs equal to “1” are greater than but not equal to “n” inputs. 3. Truth table and graph are for “n” equals 2.
x ˙ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
© 2006 by Béla Lipták
A 0 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1
B 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1
C 0 0 0 1 0 0 1 0 1 0 1 1 0 1 1 1
x 0 0 0 0 1 0 0 1 0 1 1 0 1 1 1 1
O 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
1 0
A B C X O 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
t
884
PLCs and Other Logic Devices
TABLE 5.1a (continued) Instrument and Control System Functional Diagramming Symbols-Binary Logic, Memory, and Time Functions (Proposed for the next revision of ISA S5.1 (now ANSI/ISA-5.01.01) at the time of this writing)
No 05
Symbol
Definition
Truth Table
Graph
A B C
≤n
O
1. Qualified OR gate with less than or equal to qualifications. 2. Output equals “1” if number of inputs equal to “1” are less than or equal to “n” inputs. 3. Truth table and graph are for “n” equals 2.
x
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
06
A 0 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1
B 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1
A B C
C 0 0 0 1 0 0 1 0 1 0 1 1 0 1 1 1
x 0 0 0 0 1 0 0 1 0 1 1 0 1 1 1 1
