5.3

Optimization of Logic Circuits P. M. KINTNER

(1970)

R. A. GILBERT

Instrumentation and controls is an engineering discipline, expertise, and practice that relies heavily on information presented in P&ID function, and circuit diagrams. An interesting but challenging aspect of function and circuit diagrams is the fact that the logic circuits depicted have often been optimized. Process control loop element cost and assembly drive this optimization. Since logic simplification always means less hardware, circuits that are less expensive and more reliable, and simpler circuits for troubleshooting, new control scheme circuit designers are encouraged to expand their knowledge in this area beyond the introductory material presented here. Extensive optimization accents the need for two skills. Today, most personnel involved in instrumentation and controls comprehend optimized function diagrams and, to some extent, create optimized logic circuits. This section presents the building blocks for the optimization of basic function diagrams. The section begins with a brief review of logic elements and the impact of the inversion operator on logic functions. Classically, the design and optimization of logic circuits have centered on the synthesis of switching element (static or relay-type) interconnections that will satisfy the switching functions required by the process. With the development of computer control there is an increased need for instrument and control engineers who understand and can apply logic techniques for process control. In addition, new computeraided design software produces function diagrams equivalent but not visually similar to the initial design idea. The ability to recognize this equivalency is essential to avoid lost time, energy, and money altering something that does not need to be altered. This awareness begins with a sound appreciation of the fundamental building blocks.

OPTIMIZATION BUILDING BLOCKS The basic logic components and operations are straightforward and have their origins in ancient Greek philosophy. Modern engineering uses of logic expand the application of the AND, NAND, OR, and NOR operations to decision making—e.g., whether equipment is to be turned on or off, a voltage level is to be high or low, or a valve is to be opened or closed. Figure 5.3a illustrates these four cornerstone operations with respective truth tables. 898 © 2006 by Béla Lipták

(1985, 1995, 2005)

A1 1 0 1 0

AND B1 Q10 1 1 A1 Q10 1 0 B1 0 0 0 0

C2 1 0 1 0

OR D2 Q12 1 1 C1 Q12 1 1 D1 0 1 0 0

NAND

A2 Q13 1 0 1 0

B2 Q13 1 0 1 1 0 1 0 1

NOR

A2 Q14 1 0 1 0

B2 Q14 1 0 1 0 0 0 0 1

A2 B2

C2 D2

FIG. 5.3a Summary of fundamental logic operations.

Equation 5.3(1) is a succinct statement of a control scheme that only permits a backup pump to engage if both the liquid level and tank pressure are below sensor alarm values. Z0 = 1 only if LSL = 1 and PSL = 1

5.3(1)

This equation presents logic signals or logic variables, such as the ones into or out of logic switching elements, as alphanumeric characters with possible values of “1” or “0.” In this example, Z0 represents the pump, and LSL and PSL stand for level sense low and pressure sense low, respectively, and symbolize the low-level and low-pressure alarm status within the tank. Thus, LSL = 1 indicates the liquid has dropped below the low-level limit while PSL = 0 indicates that the pressure within the tank is above an established minimal value. The AND symbol with its truth table in the upper left side of the Figure 5.3a also summarizes the idea presented in Equation 5.3(1). The reader must be comfortable with that fact and also recognize the unique properties of the other symbols in the figure. For example, the NOR is the only logic operation that provides a logic “0” when any of its inputs are at logic “1.” The unique output situation for the NAND, also logic “0,” occurs when all of its inputs are high, while the OR only goes to logic “0” when all its inputs are at logic “0.” Figure 5.3b provides a nonoptimized function diagram for an application that involves a timing requirement. The diagram presents two AND devices, one NAND device, and a 555 pulse-generating device. The circuit also has two inverter devices, shown as triangles with circles attached. Although the discussion of this diagram is delayed, it does provide a segue to review the properties of the inverter.

5.3 Optimization of Logic Circuits

V

1 8

R9

VPower

2 On

I-1, B-4

3

555

I-2, D-2

7

C10 (−)

(+)

4

5

I-3, A-1

M-2, I-5

C11

P-2, I-6 R11

I-4, C-3

FIG. 5.3b Nonoptimized logic circuit application.

The inverter is a circuit element that performs the inversion operation. This mathematical operator is often known as the NOT, and the top left section of Figure 5.3c provides its symbolic as well as mathematical representation. The value of the input variable, A0 in this case, is inverted and expressed as the variable Q. The line, or bar, over the A0 is a visual reminder that if A0 is at logic “1,” then output Q will be at logic “0.” Thus, the NOT operation is merely the inverse

Symbol Representation A0

Q

Equation Equation

Symbol Representation

Q1 = Q = A1

A1

Q1

Q3 = C3 + D3

C3 D3

Q3

Q5 = C5 ⋅ D5

C5 D5

Q5

C7 Q6 = A6 ⋅ B6 Q7 = (C7 + D7) D7 Q6 = Q7 = A4 + B4

Q7

Q = A0

Q = Q1 = A0 A2 B2

Q2

A4 B4

Q4

Q2 = A2 ⋅ B2

Q2 = Q3 = A2 ⋅ B2 Q4 = A4 + B4

Q4 = Q5 = A4 + B4 A6 B6

Q6

Q1 is the inverse of Q Q5 is the inverse of Q4

FIG. 5.3c Logic function negation examples.

© 2006 by Béla Lipták

of the current value of the input variable; i.e., if A0 = 0, then Q will equal 1 after the NOT operation. The inversion operation can also be performed on sets or subsets of logic variables. For example, Z1 = ( A ⋅ B) + (C ⋅ D)

6 Off

R10

Q3 is the inverse of Q2 Q7 is the inverse of Q6

899

5.3(2)

is an extremely succinct method of stating that two outputs from two AND operations based on variables (A, B and C, D, respectively) are the inputs to an OR operation; the results of this are inverted to provide a value for the variable Z1. The reader should confirm that Equation 5.3(2) is fundamentally a NOR idea because the only way Z1 can be at logic “1” is when the results of both AND operations are “0.” The mathematics of logic circuit optimization involves the use of the inversion (negation) operation. Figure 5.3c summarizes the results when the negation (inversion) operation is performed on a set of basic logic operations. The figure is vertically divided, with the results of the negation shown to the right of the dashed line. For example, the symbol and equation for an inverter are presented as the top left entry in the diagram. If a negation is performed on output variable Q, the resulting symbol, a triangle without an attached circle, and the equality, Q1 = A1, are shown on the right. Now Q1 also equals A0 and Q1 is the inverse of Q. Although this is an obvious result, the other examples suggest why inversion can appear to be confusing. The symbol and equation on the bottom left side of Figure 5.3c represent the NAND operator. A review of the AND and NAND truth tables in the top row of Figure 5.3a indicates that the inverse of the NAND is an AND. However, the symbol in the bottom right section of Figure 5.3c does not match the AND symbol in Figure 5.3a. This is not a mistake, discrepancy, or deception but recognition that even though there is more than one way to symbolize the results of an inversion, the truth table results are identical. The value of Q7 is the inverse of Q6. Likewise, the symbol to the right of the AND symbol in the second row of Figure 5.3c is equivalent to a NAND symbol, and the value of Q3 is always the inverse of Q2. The reader should develop the truth table for the equation for Q5 on the right side of the third row of the figure to confirm that the complex logic symbol associated with Q5 also represents a NOR, with its equivalent truth table presented in Figure 5.3a. Figure 5.3d summarizes the results if an additional negation is performed. The operational principle is the fact that two cascaded inversions cancel, because this amounts to a double negation. Stated in symbolic form A= A

5.3(3)

where it is indicated that the logic signal A has been inverted twice, returning it to its original value. The progression of

900

PLCs and Other Logic Devices

Symbol Representation A0

Q

A2 B2

Q2

A4 B4

Q4

A6 B6

Q6

Equation Equation

Q = A0

Q2 = A2 ⋅ B2

Q4 = A4 + B4

Q6 = A6 ⋅ B6

Q1 is equivalent to Q Q5 is equivalent to Q4

Symbol Representation

Q1 = (A1) = Q

A1

Q1

Q3 = (C3 + D3)

C3 D3

Q3

Q5 = (C5 ⋅ D5)

C5 D5

Q5

Q7 = (C7 + D7)

C7 D7

Q7

FIG. 5.3d Examples of cascaded negation logic operations (DeMorgan equivalent circuits).

negations from left to right in the first row of Figure 5.3c and then in the right side of the first row of Figure 5.3d also illustrates this double negation effect. The inverter output variable, Q1, shown in Figure 5.3c is the inverse of Q, while the subsequent inversion of Q1 in Figure 5.3d returns the value of Q1 to the original Q value state. Following the same presentation pattern, the reader should confirm that the remaining three logic functions illustrated on the right side of Figure 5.3d are identical to the respective AND, OR, and NAND in the left portion of the corresponding row of Figures 5.3c and 5.3d. As an instructional example of how a double inversion cascade is performed, consider Equation 5.3(4). 5.3(4)

A single inversion of Equation 5.3(4) can certainly be represented as Equation 5.3(2), where Z1 is the inverse of Z2. However, the expression on the right side of Equation 5.3(2) is not the only possible representation. To develop an addition equivalent logic statement, the inversion of every input signal and simultaneous interchange of the AND and OR operations (DeMorgan’s theorem) is performed on Equation 5.3(2). Equation 5.3(5) summarizes these operations as Z1 = Z 2 = ( A + B) ⋅ (C + D)

5.3(5)

Following this same set of rules, the second inversion is performed on Z1 to return to Equation 5.3(4). In this case, the individual inversion symbols above variables A, B, C, and D are removed, and the OR operation within each parenthesis becomes an AND operation, while the AND

© 2006 by Béla Lipták

A + B = A⋅B

5.3(6)

and the NAND operation

Q3 is equivalent to Q2 Q7 is equivalent to Q6

Z 2 = ( A ⋅ B) + (C ⋅ D)

operation that separates the parentheses now becomes an OR operation. This cascade inversion process can be used to obtain equivalent forms of both the NOR operation

A⋅B = A + B = A + B

5.3(7)

The respective left and right sides of Equation 5.3(6) and Equation 5.3(7) are called DeMorgan equivalents. The right side of Figure 5.3d shows the DeMorgan equivalent symbols for the NAND as well as the OR, AND, and the inverter. Because the inverter only has a single input, the DeMorgan equivalent for the inverter is sometimes depicted as a triangle with the circle moved to its input side. Although the DeMorgan equivalent for the NOR is not included in Figure 5.3d, the reader, after re-examination of Figure 5.3c, should realize that the NOR equivalent symbol is associated with variable Q5. Graphic Logic Functions Control logic schemes are mathematical relationships between input and output variables that can be represented graphically through logic diagrams. Figure 5.3e illustrates a chemical storage and filling station. The figure provides a description of the tank filling process from three distinct perspectives. The equation at the top of the diagram connects the storage tank fill (STF) operation to all of the variables affecting that filling step. The P&ID diagram provides the visual details of the interconnections among the equipment, sensors, and actuators. The panel in the center left portion of the figure presents the function diagram that emphasizes the seal-in action included in the control scheme. A good way to appreciate the utility of logic diagrams and the complication optimization can create is to review Figure 5.3e. The example illustrates the tank section for a chemical process. The drawing shows three pumps (equipment 400, 402, and 404), a low-pressure sensor (PSL 1010), two pressure control valves (PCV 1008 and 1009), and a flow quantity indicator and controller (FQIC 1011). For simplicity, consider the filling operation for this system because it involves only one pump and two control elements, PSL 1010 and FQIC 1011. In this example it will be assumed that the logic function for this part of the operation is STF = (( FQIC 1011 ⋅ STF ⋅ PSL 1010) + START P. B.) ⋅ STOP P. B.

5.3(8)

where START P.B. and STOP P.B. are the variables assigned to the start and stop pushbuttons in the system and STF is the variable associated with the operation of the pump. STF

5.3 Optimization of Logic Circuits

901

PCV 1009

STF = [(FQIC 1011 ⋅ STF ⋅ PSL 1010) + Start P.B.] ⋅ Stop P. B.

N2

(Tank 401 and 403 Predetermined count)

SR-Base TK-401

STM

FQIC 1011 T

Pump discharge Press. [