PLASMA TV SERVICE MANUAL We can separate plasma tv into parts of •= •= •= •= •= •= •=

Analog board: 11AN42Y IR board: 11IR42Y Digital board: 11DG42Y Interface board: 11NEC42 Plasma display panel Glass Filter Mechanical parts: Chasis cover, back cover, front panel, IR box, and speaker boxes

IR BOARD 11IR42Y Ir board 11IR42Y is designed to place ir eye and two leds representing the status of the TV.

ANALOG BOARD 11AN42Y 11AN42Y board is composed of 3 parts: Power part, IR part, Analog part.

11AN42Y-Power Part On the power part, the main voltages generated are (the followings are typical voltages, you can see these voltages in detail in Adjustment part) : Vs (Sustaining voltage) Va (Addresing voltage) Vaudio Other voltages

: 180V dc : 60V dc : 30V dc : 12, 5.1, 5, 3.3 V dc

12V and 5V dc are used on the analog and digital board in order to supply fans and ICs. 3.3V dc is used to supply digital board ICs, which run with 3.3V. 5.1V dc is used to supply logic part (dsp, memory management, data driving, multiplexing) of the plasma display panel.

Vaudio (30V dc) is used for audio amplifier TDA 7262 for audio output power management. Vs and Va are used for plasma display panel. Vs is to sustain the picture (colors) on the screen and Va is to address the lines of the plasma display panel.

Power part of 11AN42Y can be separated into parts of •= •= •= •= •= •=

Stand-by power management, PFC management, 12V management, Va and Vaudio management, Vs management, Other voltages’ management

Stand-by power management is achieved with transformator L3 and a 5V regulator LM7805. PFC management, as a requirements of the norms, is achived with an active solution. IC4 L4981B is used for active solution. 12V management includes both 12Vdc generation and 60V regulation. 12V generation is achived with TR2. Va and Vaudio generation is achieved by TR2. The regualtion os these voltages are managed with IC6 TDA4605 and a regulation circuit around the IC. Va voltage is also controlled by Vs voltage by a transistor circuit with T27 STP40N10. Adjustment of Va voltage is mentioned in Adjustments part. Vs voltage is managed by IC2 SG3626 under control of Vrr voltage fed back from plasma display panel. Along with transistors T1, T5 180V is generated through L6. Adjustment of Vs voltage is mentioned in Adjustment part. Other voltages’ management, 5.1V, 5V and 3.3V, are achieved by 2 regulator ICs IC11, IC12 L4992.

11AN42Y- IR Part IC3 AT90S1200A 8-bit microcontroller is used for •= IR decoding : IR signal which is coming from ir board is processed parallelly with main controller ST10 on digital board

•= Supply and driving of green and red leds: Leds are located on ir board •= TV on/off : Drives relay REL1 and TV turns on or off •= Helping Vrr voltage 11AN42Y- Analog Part Anolog part can be divided into 2 parts Video processsing, which is managed by VPC3215C-CIP3250A concept and Sound processing, which is managed by MSP3410D-TDA8752. Video signals have two similar paths since TV has PIP(Picture In Picture)/PAP(Picture And Picture) features. In order to make it easier to understand the explanations, video path without PIP/PAP is called as Normal path, and the path with PIP/PAP is called PIP path. Video signals can be from Tuner, TUN1 CTT5000, 2 scarts PR6, PR4, and svhs input PR5. In TV mode, terresterial signal from tuner TUN1 is fed into IF box, IF1 IF3353, and cvbs (composite video signal) from IF box is fed into VPC3215C, IC21 if the path is normal or IC17 if it is PIP path. Concerning scarts, cvbs is directly fed into VPC 3215C, IC21 if the path is normal or IC17 if it is pip path. Concerning s-vhs, Y(Luma)/C(Chroma) is fed into VPC 3215C, IC21 if the path is normal or IC17 if it is pip path. VPC3215C is a video processor which is used for color decoding, comb filtering, sync processing and horizantal scaling and output formating. It is driven by a 20.25Mhz clock, X3. Output video data signals, 8-bit Y and 8-bit C, from VPC3215C is fed into CIP3250A, IC22 if the path is normal or IC18 if it is pip path. CIP3250A is a component interface processor which is used for interfacing video signals YUV coming from VPC315C, RGB signals from scart or teletext processor, and then CIP3250A outputs digital 8-bit YUV signal in 4:2:2 format to be fed into digital processing part on digital board.

IC26 TPU3050, which is a teletext processor, is used as an RGB switch and teletext processor along with IC27 GM76C8128, which is a memory IC. TPU3050 switches RGB signals from scart and output of teletext information. Sound signals can be from IF box as sound IF and audio L, R signals from scarts and audio sockets for pc and s-video inputs. Sound processing is achieved by IC24 MSP3410D. It is driven by the xtal X4 18.432Mhz. Output of MSP3410D, which is audio L,R, is fed into IC13 TDA7262 for amplification of 2x15 watts on 4 ohm speakers. MSP3410D also outputs 2 line out audio signals via PR14B on analog board.

DIGITAL BOARD 11DG42Y Digital 8-bit YUV signals in 4:2:2 format are fed into GMVLX1A, IC14 if the path is normal or IC1 if it is pip path. GMVLX1A is used for de-interlacing, image scaling and gamma correction along with KM4132G512A SGRAM, IC15 if the path is normal or IC2 if it is pip path. Output of GMVLX1A is RGB each of 8-bit. PC signal, which consists of analog RGB, horizantal and vertical syncronization signals are fed into digital board via J2 DB15. Analog RGB signals are fed into IC11 TDA8752, which is an analog to digital converter, in order to be converted into digital 8-bit RGB. According to the input mode selected, through buffer memories IC9, IC10 for PC RGB and IC16, IC17 for normal video path, PC or normal video RGB and syncronization signals are fed into IC18 GMFRC1A, which is a frame rate conversion chip. PIP 8-bit RGB signal is fed into IC3 GMFRC1A for frame rate conversion. GMFRC1A manages frame rate conversion along with SDRAMs MT48LC1M16A IC19, 20, 21 if the path is normal or IC4, 5, 6 if it is pip path. After frame rate conversion process in GMFRC1As, video signals are fed into IC22 EPF10K30AQC, which is a 30K size PLD (Programmable Logic Device). This pld is used for digital board management and some special dsp applications on video signal such as rounding, error diffusion. After PLD, video signal; RGB each 8-bit with syncronization signals are ready to be sent to Plasma display panel via Nec interface board.

OSD and menu managements are also carried out by this pld along with an osd sdram IC23. Main control of the TV is carried out by IC26 ST10R165 16-bit romless microcontroller along with a flash ram of size 4Mbit, IC27 M29F040. Main controller mainly manages analog board control and starts pld at the beginning.

INTERFACE BOARD 11NEC42 Note: This board is not used when plasma display panel is from FUJITSUHITACHI company. Interface board is used to manage the interfacing between 68 pin connector and 80 pin connector. Through this board, the communication between main controller ST10R165 and plasma display panel for some special applications (such as PLE: Peak Luminance Enhancement) is achieved.

ADJUSTMENTS If it FujitsuFujitsu-Hitachi panel, Plasma Display TV has two important voltage adjustments and these adjustments are related with plasma display panel. The voltages are, Vs (Panel driver circuit voltage), and Va (Address driver circuit voltage). These voltages are produced by 11AN42Y analog board power part. Vs and Va are adjusted according to the feedback voltages from plasma display panel. These feedback voltages are Vrr, Vrs, and Vra. According to these feedback voltages, Va and Vs are adjusted via P1 and P2 potentiometers, respectively. The following tables presents the settings of these voltage adjustments: No. 1

2

Item Panel Driver Voltage Voltage Ripple/Noise Stability Setting accuracy Current (average) Current (instant) Address Driver

Symbol

Term/Cond’n Min

Value Typ.

Max

Unit

165 -

-

185 500 +/- 1.5 +/- 0,5 1.5 12

Circuit Vs Vnrs Is Isp Circuit

165+10xVrs

APC function operation

V mV % % A A

3

Voltage Voltage Ripple/Noise Stability Setting accuracy Current (average) Current (instant) Logic Circuit Voltage Voltage Ripple/Noise Current (average) Current (instant)

Va Vnrs Ia Iap

55+10xVra

Vcc Vnrs Icc Icp

Fixed

55 -

-

-

65 500 +/- 1.5 +/- 0,5 1.8 3.0

V mV % % A A

4,75 -

5,0 -

5,25 200 5.0 5.0

V mVp-p A A

1. PDP unit will not operate under the following conditions. When in this condition, panel driver circuit current “Is” will be less than 50mA. •= “Vcc” has not been applied to the PDP unit. •= 2 second period from power on until all power supply voltages (Vs, Va, and Vcc) have settled to normal operating levels. •= “Vs” is outside of the standart range. •= “Va” is outside of the standart range. •= No vertical synchronous signal present at signal interface. 2. Reference voltage Vrs is the output from the PDP unit for “Vs” voltage setting. 3. Is current is automatically controlled to approximately 1.0A by the APC (Automatic Power Control) function. However, at start-up (1 minute or less), it can reach up to 4.0 A and then it goes down gradually to the convergent value for about 3 minutes. The APC setting value on start-up is approximately 300W (APC start-up display load ratio is approximately 20%). 4. Reference voltage Vra is the output from the PDP unit for “Va” voltage setting. 5. Vrr is the sequence control voltage to Vs and Va. When Vrr is “Enable level”, Vs and Va voltages are able to be input to the PDP unit. However, when Vrr is “Disable level”, Vs and Va voltage should be deactivated. No. 1

2

Item Vs setting voltage Voltage (variable) Ripple/Noise Stability (average) Current Va setting voltage

Symbol

Cond’n Min.

Value Typ.

Max.

Unit

Vrs

0.0

-

2.0

V

Vnrr -

-

-

+/-500 +/- 0.2

mV %

Irs

-

-

3

mA

3

Voltage (Variable) Ripple/Noise Stability (average) Current Sequence conttrol high voltage to Vs and Va Voltage (Fixed)

Ripple/Noise Stability (average) Current

Vra

0.0

-

2.0

V

Vnrr -

-

-

+/-500 +/- 0.2

mV %

Ira

-

-

3

mA

Enable level

2.0

-

3.5

V

Disable level

0.0

-

1

V

Vnrr -

-

-

+/-500 +/- 0.2

mV %

Irr

-

-

3

mA

Vrr

1. Vrs is set at a value obtained from the following formula which is relative to Vs. Vs= 165+10xVrs [Vrs: 0 to 2.0V] 2. Vra is set at a value obtained from the following formula which is relative to Va. Va=55+10xVra [Vra: 0 to 2.0V] 3. When the PDP-unit is powered on, Vrr is output at a value of about 0V. Then if Vs and Va are able to be input to the PDP-unit from 11PWB42 board, Vrr is output at a value of about 3.0V. 4. Load resistor for each output signal are set at a value of 1kohm.

If it NEC panel, 1. SUSTAIN POWER SUPPLY (Vs)

2. DATA POWER SUPPLY (Va)

3. LOGIC POWER SUPPLY

14

15

16

gnd 13

gnd

gnd

gnd

AFC

CVBS

AF AM

IFO

AGC

NC

NC

SCL

SDA

5VT

5VP

32V

Z9 BZV55C 5V1

gnd

gnd

gnd

PR5 SVHS

gnd

AUDIO_IN R

C252 100nF

1 2 3 4

6

5

4

1nF

gnd

gnd

gnd

C253 100nF

gnd

gnd

gnd

gnd

R233 75R

gnd gnd

R351 100R

BZV55C 5V1

R250 75R

C257 390pF

R246 5K6

SCL

gnd

Z8

5K6

R239 100K

R237 100K

330pF

C246

Z7

R210 4K7 1/2W

+5Va

R373 100K

gnd

gnd

5K6

R244

gnd

ET FI

gnd

R371 10R

GND

SV

MVI

R

MR

V

MV

B

MB

SG

SD

gnd

PERITEL

EV

MC

CR

ML

BUS

BUS

CL

EG

MA

ED

PR6

R378 330R

T36 BC847B

R376 10R

R372 330R

+5V

1

1

gnd

21

19

17

15

13

11

9

7

5

3

1

+5Va

+5Va

R226 68R

gnd

gnd

R216 330R

R214 330R

PAST8

R248 75R

R245 75R

R240 75R

R227 1K

gnd

gnd

gnd

gnd

R242 100K

R238

R236

gnd gnd

R241 100K

gnd

GND

C339 10pF

sv_peri2

8

IC23 PCF8574T

peri_B peri_CR Y_peri

p e ri _G

peri_R

T23 BC847B

R208 33R

+12V

R200 10K

R198 22K

R298 68R

PAST7

gnd

gnd

R209 2K2

+5Va

gnd

T20 BC847B

2

R212 3K9

T24 BC847B

gnd

C214 470nF

C204 10uF 16V

+33V SDA SCL +12V gnd +5V

T35 BC847B

R252 75R

20

18

16

14

12

10

8

6

4

2

R234 470R R235 470R

gnd

R377 33K

R375 33K

gnd

gnd

+5Va

R374 100K

gnd Y_db25

+60V

R202 22K

gnd

R205 10K

1K

BZX85C 33V

SDA

gnd

C344 220nF

C245 330pF

R232 75R

50V

C8 2uF2

gnd

TUNER 2

3

J16

12 11 10 9 8 7 6 5 4 3 2 1

R199

gnd

C234 10uF 16V

gnd

+5V

R224 4K7

gnd

+33V

gnd

C211 1nF

1K

gnd

gnd

gnd

T21 BC847B

1000uF

25V

R231 10K

R243

gnd

C193 100nF

gnd

100nF

R230 10K

gnd

gnd

C233 470nF

gnd

R350 100R

gnd

15K

R229

C228 220pF

R223 330R

gnd

C216 gnd 470nF L23 10uH

gnd

R197

C199

C195

+5Va

25V

C346 100uF

L21 10uH

R221 330R

gnd

C221

gnd

+5V

C212 100uF 25V

gnd

CINCH PR13B

C232 1nF

gnd

100pF

C227

1

2

3

4

5

6

7

8

9

10

11

R149 150R 1/2W

+12V

2 1

AUDIO_IN L

1

2

3

4

5

6

7

9

11

IF IN

B/G

L

NORM

TUN1 CTT5000

gnd

gnd TUN AGC

gnd

gnd

12V

5V

SOUND IF

IF1 IF3353

gnd gnd gnd gnd

8 10 12 13

P0

4

1

2

R182

R181

A2

5

P1

470R

470R

R363 10K

R364 470R

gnd

VCC

C215 22pF

C247 1nF

gnd

10K

C248 1nF

10K

R386

g

g

gnd

C_svhs

Y_svhs

gna

C220

C347 100nF

C225 100nF

L24 10uH

gna

C218

47pF

10pF

C205 10pF

SCL

gna

23

22

21

20

19

18

17

16

15

14

13

12

11

10

C229 330nF

C226 100uF 25V

26

47pF 25

47pF 24

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

com_L com_16/9

peri_on/off

C235 100nF

gna

gna

X4 1 8 M h z 432

L22 10uH

SDA

SDA

C217

33pF

X5 1 8 M h z 432

C328 100uF 25V

SCL

gna

C320

C210

gna

Y_tv

+5V

R384 10K

gnd

reset

MUTE

+5V

R183 1K

C327 100nF

g

g

C314 33pF

SCL

SDA

C236 1uF 50V

gna

AVSUP

ANA_IN1+

ANA_IN-

ANA_IN2+

TESTEN

XTAL_IN

XTAL_OUT

DMA_SYNC

AUD_CL_OUT

NC

NC

NC

D_CTR_OUT1

D_CTR_OUT0

ADR_SEL

STANBYQ

NC

R193 330R

9 gna

I2s_in1 I2s_out I2s_ws

gna

I2s_cl

R190 330R

AVSUP

NC

NC

NC

TESTEN

XTAL_IN

XTAL_OUT

D_CTR_IN

AUD_CL_OUT

NC

NC

NC

D_CTR_IO1

D_CTR_IO0

ADR_SEL

STANBYQ

NC

R308 330R

R303 330R

I2s_cl

C237 330nF

g

g

4

SC3_in_r

SC3_in_l

C301 22nF

C300 22uF 16V

gndd 3

L27 10uH

gndd

C196 22uF 16V C197 22nF

g

gndd

gndd

gnd

gnd

C292 1nF

gna

g

gndd

R186 10K

IC24 MSP3410D {OBSERVATION} {FOURNISSEUR}

g

gndd

R300 10K

67

I2s_in1

66

I2s_out

C294 330pF

R295 100K

R293 100K

R290 470R

gna

1nF

gndd

C198 100nF

gnd

Y_db25

gnd

C293

g

gndd

C302 100nF

64

+5V

L28 10uH

R385

R369 1K

C343 22pF

R219 1K

1K

16

330R

330R

gnd

1K

1K

R192

R194

1K

1K

R189

T34 BC847B

R362 2K2

+5V

R185

R187

Y_db25

gnd

+5V

R361 27K

6

A1

P2

14

AO

15

SCL

7

P3

9

P4

10

SDA

P5

13

INT

P7

J20

7

P6

11

12V Adaptateur NEC

7

6 5

gnd gnd

27

I2C_CL

8 I2C_DA

12

27 I2C_CL

I2C_DA

6 I2S_WS

5 SC1_IN_L

7 I2S_CL

AVSS 9 AVSS

MONI_IN 28 8 MONI_IN

28

VREFTOP 29 7 VREFTOP

29

I2S_CL 30 6 SC1_IN_R 30

4

SC1_IN_R I2S_WS

31 5 I2S_DA_OUT 330nF

SC1_IN_L 31 C238

I2S_DA_OUT1 32

ASG1 33

I2S_DA_IN1

2 NC

I2S_DA_IN1 3 330nF

ASG1 32 C239

SC2_IN_R 33

NC 2 SC2_IN_L 34 C240

SC2_IN_R

SC2_IN_L 34

NC

68 NC

65 I2S_DA_IN2

1 36 C241

ASG2 35 330nF

SC3_IN_R 330nF

S_DA_IN

ASG2 35 1 S_ID

NC 36 68

SC3_IN_L 37 67 DVSUP

SC3_IN_R S_CL

DVSUP 66 DVSS

38

ASG4 39 C290

330nF

SC3_IN_L 37 C242

ASG4 38

DVSS 39 65 SC4_IN_R 330nF

NC 40 NC

NC I2S_DA_IN2

I2S_DA_OUT2

gna

6

4

2

gnd

20

18

16

14

12

ASG3

NC

NC

NC

DACM_L

DACM_R

VREF2

DACA_L

DACA_R

reset

DPL3519A

CAPL_C1

AHVSUP

CAPL_C2

SCI_OUT_L

SC1_OUT_R

VREF1

SC2_OUT_L

SC2_OUT_R

ASG3

NC

NC

NC

DACC1_L

DACC1_R

VREF2

DACC2_L

DACC2_R

reset

PR4 SD

GND

SV

MVI

R

MR

V

MV

B

MB

SG

PERITEL2

EV

MC

CR

ML

BUS

BUS

CL

EG

MA

ED

gna

C231 3uF3 50V

CAPL_M

AHVSUP

CAPL_A

SCI_OUT_L

SC1_OUT_R

VREF1

SC2_OUT_L

SC2_OUT_R

C230 100nF

gna

8 C295 330pF 10

gnd

R291 470R

gna

62 NC

61 RESETQ

63 NC

NC 42

64 SC4_IN_L 40 C291

NC 41 63 NC

41 330nF

AGNDC NC

AHVSS RESQ

42 62 AGNDC

43 61 AHVSS 43

21

19

17

15

13

11

9

7

5

3

1

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

gnd

C222 10uF 16V

100R

R213

R211 100R

gna C206 C208

R217

R215 100R

C203 1nF

gnd

gn

R297 100K

R294 470R

C224 10uF 16V

R220 100R 1/2W +12V

C201 2uF2 50V

daca_l

daca_r

gna

gnd

gnd

R353 10K

R218 470R

R289 100R

gna

3

2

1

gnd

C209 10nF

C207 10nF

R335 100K

1

2

3

R327 100K

audio2_L

audio2_R

gnd

CINCH gnd

LINOUT_1 L

PR14B

LINOUT_1 R

gnd

gnd

LINOUT_2 L

PR14A

LINOUT_2 R

gnd

gnd

CINCH

AUDIO PC_IN R

AUDIO PC_IN L

R228 100K

4

5

6

R222 100K

gnd

gnd

audio_L

audio_R

gnd

CINCH PR13A

T22 BC857B

R201 2K2

T19 BC857B

R288 100R

C243 22uF 16V

R207 10K

R203 6K8

R196 10K

R333 470R

R331 470R

C319 10nF

C316 10nF

T29 BC857B

R311 2K2

T28 BC857B

R302 2K2

R188 2K2

R225 470R

R319 10K

R312 6K8

R309 10K

R304 6K8

R191 6K8

gnd

gnd

R352 10K

1 2 3

J18

C308 2uF2 50V

C303 2uF2 50V

C200 2uF2 50V

gna

C244 22uF 16V

gna

22uF 16V

22uF 16V

daca_l

C194 100uF 25V

C332 1nF

R349 100R

100R

22uF 16V

R348

daca_r

gn

C298 100uF 25V

22uF 16V

gnd

gnd

gna

R292 470R

sv_peri2

R296 100K

BZX84C 8V2 gn

SZ1

C219 100R 10uF +12Vc 16V C223 100nF

gnd

gn

g

gna

C202 1nF

100R

gna

gna

R184 100R

R206 100R

C289 1uF 50V gn R204

C 2 8 81 u F 5 0 V

1nF

C287

+5V

1nF

gn

+12Vc

gna

C318

C315

C331 1nF

C311 1nF

100R

R322

C321 10uF 16V

100R

R315 100R

R313

R321 100R

gna

C310 1nF

C286

C326 10uF 16V

gn

g

gna

gn

C329 100nF

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

IC29

+5V

R299 100R

8

gndb

1

2

3

4

5

6

7

8

9

10

11

gndb

+30V

C107 220pF

gndb

IC13 TDA7262

gndb

gndb

C325 100nF

gndb

+30Vb

25V

gndb

Mute

Entrée GAUCHE a u d i o _ L

Entrée a u d i o _ R DROITE

gndb

C112 100nF

1uF

gndb

Mute

gndb

T14 2N7002

50V

C108

C104 1uF 50V

C95 220pF

Entrée GAUCHE a u d i o 2 _ L

1uF

T31 2N7002

50V

C317

C312 1uF 50V

C306 220pF

Entrée a u d i o 2 _ R DROITE

C102 100uF

C111 1000uF 50V

gndb

+30Vb

25V

C309 100uF

{FOURNISSEUR}

R118 6R8 4W

1

2

3

4

5

6

7

8

9

10

11

{FOURNISSEUR}

M11 110066

C313 220pF

IC28 TDA7262

{FOURNISSEUR}

M13 110066 1 1

I2s_ws

8

7

2

2

gndb

gndb

gndb

C109 100nF

R126 2K7 gndb

R114 68K gndb

R340 2K7 gndb

R324 68K

C322 100nF

22K 22K

gndb

gndb

R122 68K

T15 2N7002

gndb

R336 68K

R106 220R

gndb

T32 2N7002

R314 220R

gndb

gndb

R334 33K

gndb

gndb

R127 2K7

R120 33K

C110 100nF

gndb

R116 68K

R110 33K

T13 BC847B

R341 2K7 gndb

R326 68K

T16 BC857B

Z6 BZX84C 8V2

C97 47uF 16V

C86 47uF 16V

C307 47uF 16V

C299 47uF 16V

gndb

R125 2K2

gndb

R123 100K

gndb

R119 22K

R124 4K7

R320 33K

T30 BC847B

C323 100nF

22K 22K

R323 R113

R325 R115

gndb

C305 100nF

R317 1R 1/4W

R310 1K5

R316 33R

R98 1R 1/4W R97 33R

gndb

R108 1R 1/4W R107 33R

Date:

Size

gndb

2 1

J9

2 1

J8

2 1

J15

2 1

J14

Thursday, December 30, 1999

Document Number

Sheet

208070

ANALOG_HF FI AMPLI BF PL2

AMITEK

21, Rue Galilée 77420 CHAMPS SUR MARNE Title

Amplificateur Audio 2x15W

C94 100nF

R105 1K5

gndb

R99 100R 1/4W

gndb

R109 100R 1/4W

gndb

1000uF 35V

C93

C81 100nF

R96 1K5

C76 1000uF 35V

gndb

R307 100R 1/4W

gndb

R318 100R 1/4W

gndb

1000uF 35V

Amplificateur2 Audio 2x15W

T17 BC847B

R121 33K

R117 150K

R306 1R 1/4W

R305 33R

C304

C297 100nF

R301 1K5

C296 1000uF 35V

2

of

5

C

Rev

Tél 01 64 73 95 70 Fax 01 64 73 95 58 e_mail :[email protected]

HP-GAUCHE

HP-DROIT

HP-GAUCHE

HP-DROIT

R100 1M

gnd

gnd

gnd

gnd

R104 1M

TERRE1

gnd

10nF

10nF

C103

10nF

R112 270R

CRST PWROK RUN5 VREF SGND NOSKIP OSC RUN3

10nF

R92 270R

C74

C283

9 10 11 12 13 14 15 16

gnd

1

PR1

C79

+12V

C26 100nF

R258 4K7

+5 IR

C89 100uF 25V

+5 IR

gnd

gnd_2

C91 4uF7 2 5 V

1 2 3 4 5 6 7 8 9 10

Alimentation Digital

R102 1M

J3

5285-NA

1uH

L25

gnd

2

H5GA H5SRC R5GA PGND5 PGND3 R3GA H3SRC H3GA

I

IC11 L 4 9 92

32 31 30 29 28 27 26 25

gnd_2

12Va

6

7

3

2

20 19 18 17 16 15 14 13 12 11

100nF

C100 1uF 50V

C82 1uF 50V

D24 BAS16

Z5

6

NC S S G

IC7

D D D D

4 3 2 1

8 7 6 5

D D D D

SI9410DY

G S S NC

IC14

C96 100uF 25V

5 6 7 8

C87 100uF 25V

SI9410DY

1 2 3 4

gnd

R260 4K7

A_MISO_IR

L14 47uH

C98 100uF 25V

D D D D

R94 20mR

G S S NC

IC15

D D D D

R111 20mR

SI9410DY

4 3 2 1

+5 IR

5 6 7 8

8 7 6 5

1 2 3 4 5 6

J19

LED

IR

gnd

C105 2200uF 10V

12Va

12Va

0V

gnd_2

+5V

gnd_2

R53 0.02R

gnd

REL1 RELAI 1RT

C31 4nF7

+3V3

gnd

R380 10K

R379 33K

A2 A1

1

T37 BC847B

R360 +12V 47R 1/2W

D9 1N4007

C68 2200uF 10V

R14 1K

T3 BC847B

gnd

A_RESET

SI9410DY

IC8 1 NC 2 S 3 S 4 G

D51 BAS16

gnd

gnd

R24 220R

+5 IR

C23 47uF 16V

R359 4K7

R10 3K3

Z10 BZV85C 15V

gnd

C7 220uF 25V

gnd

BAS16

D56

R2 10R 1/2W

47uH

C84 100uF 25V

L12

R259 4K7

C342 10nF

gnd

A_OFF_CLK

A_MOSI

D57 1N4007

C3 220nF 250V

IR_OUT

R257 1K

R255 8K2

6

7

S T P S 5 L 2 5B

gnd_2

D37 BAS16

gnd

5

S T P S 5 L 2 5B

T26 BC847B

BAS16

D59

Z3

BAS16

D35

470R

R29 470R

R31

BAS16

BAS16

D15 1N4007

D7 1N4007

1

R367 330R

D49

D45

D14 1N4007

D8 1N4007

R 3 8 23 K 3

C77 100uF 25V

+5 IR

4K7

gnd

R366

C10 47uF 25V

4K7

1

L3 Myrra/4457 1 0

3

2

In 220AC N

6

7

R365

VCC SCK/PB7 MISO/PB6 MOSI/PB5 PB4 PB3 PB2 AIN1/PB1 AIN0/PB0 PD6

100nF

22uF 1 6 V

C72

C281

gnd

gnd

C22

O

IC1 L M 7 8 05

C9 100nF

3

A T 9 0 S 1 2 0 0 A - 4 SC Atmel

RESET PD0 PD1 XTAL2 XTAL1 PD2/INT0 PD3 PD4/T0 PD5 GND

IC3

peri_on/off

1 2 3 4 5 6 7 8 9 10

+5 IR

Entrée Secteur vers l'inter

T4AH

F2

3

2

9 7

L31 42V32

3

2

R103 1M

gnd_1

C92 4uF7 2 5 V

R101 1M

R54 3K9

5K1

R49

1 2 3 4 5 6 7 8 9 10

D5 BY255

D2 BY255

C6 1nF 1KV

C333 220nF 100V

9 10 11 12 13 14 15 16

10nF

10nF

R93 270R

1

C284 10nF

CRST PWROK RUN5 VREF SGND NOSKIP OSC RUN3

C80

C75

+12V

C338 1uF 50V

PGND IPK OVP IAC CA-OUT LFF VRMS MULT-OUT ISENSE SGND

IC4 L4981B

1uH

L26 2

GDRV VCC COSC ROSC FREQ-MOD P-UVLO VFEED VA-OUT SS VREF

R11 1M 1/2W

R354 R355 560K 1/4W 560K 1/4W

250V

C276 470nF

C334 220nF

C90 100uF 25V

0V

0V

0V R357 33K

R356 390K

D4 BY255

Alimentation Plasma

R45 3K9

39K

R38

R35 220R

1KV

C5 1nF

D1 BY255

R1 0R47 7W

H5GA H5SRC R5GA PGND5 PGND3 R3GA H3SRC H3GA

L4 O R E G 6 6 3 9 - 01

R16 47R 1/2W

D18 BA159

D10 BA159

R50 27K 1/4W 1%

IC12 L 4 9 92

32 31 30 29 28 27 26 25

gnd_1

12Vb

C345 100nF

R 2 7 6 1M

100nF

22uF 1 6 V

C73

C282

C38 10uF 16V

20 19 18 17 16 15 14 13 12 11

R12 39K 2W

2 3 4 19 18 17

L30 42V32

C39 1nF2

D19 BA159

D11 BA159

C83 1uF 50V

C78 100uF 2 5 V

16 15

L29 42V32

L5 OREG6639-01

0 V0 V

D36

Z4

0V

NC S S G

IC9

25V

C88

8 7 6 5

100uF

D D D D

SI9410DY

1 2 3 4

R358 39K 2W

C335 470pF 2KV

S T P S 5 L 2 5B

C32 330nF

3K9

R41

D25 BA159

0V

0V

R5 100K 1/4W

BAS16

gnd_1

R43 120K

R36 1R 5% 1/4W

R34 15R 1/2W 5%

C19 220uF 25V

Z1 BZX85C 18V

7 8 9

14 13 12

C2 220nF 250V

2 3 4 19 18 17

Prise avec filtre secteur

1

16 15

T 4 AH

G

2

7 8 9

14 13 12

1 2

BA159 D55

J1

M7 1 1 0 0 66

T8 S T W 1 5 N B 50

R3 820K 1W 1%

D3 MUR1560

1KV

C13 100pF

47uH

C85 100uF 25V

L13

NC S S G

IC10 D D D D

R95 20mR

SI9410DY

1 2 3 4

R51 10K

R368 470R

1

8 7 6 5

1%

R52 10K 1/4W

C337 1uF 250V

C336 1uF 250V

R4 909K 1W 1%

F3

12Vb

C70 2200uF 10V

4AT

R17 1M 1/2W

R13 1M 1/2W

C17 470uF 250V

C11 470uF 250V

+5.1V

gnd_1

C18 470uF 250V

C12 470uF 250V

440V

J7 1 2 3 4 5 6 7 8 9

gnd

+5.1V

VRR

VRA

VRS

gnd_1

R32 3K3

PR15

gndd

C65 100nF

0V

0V

gnda

10nF 50V

C62

gnd

gndb

R83 220R

R383 3K3

D58 BAS16

gnd

R33 10K

T7 BC847B

gnd

R88 1K

R84 2K2

R66 470K 1W

R25 2K2

R18 2K2

+12V

g

0V

gna

R282 270K 1W

gnd_2

R76 3K3

gnd

R39 1K

R37 18K

T4 BC640

gn

4

3

2

1

sgnd

5

6

7

8

R42 470K

R280 39K 2 W

PR8

R75 22R 1/2W

220nF

C60

630V

gnd 60V

OUT

VCC

ST

ZERO

R62 39K 2 W

C 4 7 18nF

R279 39K 2 W

R46 5K6

C29 220pF

BAS16

D17

R26 6K8

BAS16

D13

C21 10nF

P1 1K

TDA4605

GND

V IN

PCUR

FB

gnd_1

R67 330K 1W

gnd

C27 100nF

IC6

gnd gnd

gnd

C20 470uF 25V

gnd

18

F1 In 220AC N

1

15

16 0V

14

12

1 2 3 4

0V

LM56CIM

C15 1nF5

6R8 1/2W

8 7 6 5

+5V

110066

C61 100pF

R73 470R

1

2

M14

100K

R347 4K7

gnd

R346 33R

R342 100K

3

6

gnd

1 2 3 4

T33 BC857B

4

5

L6 O R E G 6 6 4 0 - 01

SI9410DY

NC S S G

D D D D

R284 470R

8 7 6 5

1

gnd

gnd

S6 0R

1 110067

M16

1W

1 2

1 2

gnd

J17

J2

1KV

200V

BYV28

1KV

100pF

1 110067

M19

S1 6

F1 9

R86 1K

T11 BC847B

1

gnd

R91 1K

R87 10K

gnd

gnd

C280 100nF

gnd

AMITEK

C56 100nF

BAS16

gnd

0V

Date:

Size

2

1 M1 110066

2

1

Out_12V

C285 10uF 100V

OUT 60V

R44 39K 2W

R381 27K

0V

M2 110066

M T W 1 4 N 50E 500V/14A

T5

T1 M T W 1 4 N 50E 500V/14A

Thursday, December 30, 1999

Document Number Sheet

+12V

gndb

+30V

gnd 60V

1 2 3 4 5 6 7 8 9 10

J6

gnd

1

of

5

C

Rev

Tél 01 64 73 95 70 Fax 01 64 73 95 58 e_mail :[email protected]

R285 22K 1/2W

gnd

5V1

Z11 BZV55C

4M7 R28 1W

+180V

208070

ANALOG_ALIMENTATION PL2

21, Rue Galilée 77420 CHAMPS SUR MARNE Title

gnd

C64 100nF

gnd

D54

R278 10K

C36 1uF 250V

R8 4K7

R21 4K7

C35 220uF 200V

T27 STP40N10

R277 150K 1/2W

+180V

10R

R275

10R

R274

L7 47uH

C55 1000uF 16V

R58 22K 1/2W

R79 4K7

+60V

C34 220uF 200V

Z2 BZV55C 5V1

R85 8K2

L11 47uH

R283 33K 1/4W

C45 100uF 100V

C54 1000uF 16V

2

T12 BC847B

R78 220R

C279 1000uF 35V

C44 100uF 100V

L9 47uH

F3

S3

4

F2

3

S2

2

1

O R E G 6 5 9 7 - 02

TR1

R90 470R

110067

M18

MUR1560

1

M U R 1 5 60 200V/3A

C66 22nF

D31

100pF

C58

D33

C43

D29

200V/3A

D27 MUR1560

D23 MUR1560

R370 10R

+12V

gnd

R89 3K3

1K

P3

R82 33K

17 16

15 14

19

18

13

12

D26 MUR1560

D22 MUR1560

O R E G 6 7 8 7 - 01

TR2

IC31

2

1

+12V

0V

9

8

4 3

6 5

110067

M17

1

110067

M15

C57 100pF 1KV

S T M S T W 7NA 1000V/7A

T10

1

1

440V

0V

gnd

ISO1 T C D T 1 1 01G

0V

R281 22R 1/2W

4AT

R344

F4

R48 150K

gnd

IC2 S G 3 5 26

D32 BA159

Vref V+ Vt2 O U T 1 Vt1 O U T 2 G N D Vtemp

IC30

R72 10K

C278 100uF 25V

D53 BA159

R47 120K

R40 2K7

10

Régulation de température

R345 15K

13 gnd

R81 4K7

0V

R343 12K

0V

C30 100pF

gnd

R9

1/2W

6R8

R6

2 3 4 19 18 17

Entrée Secteur venant de l'inter

8 7 6 5 4 3 2 1

SOFT5 COMP5 I5SNS V5SNS V5SW REG5 VIN H5STR

SOFT3 COMP3 I3SNS V3SNS V131N REG12 (*) H3STR

17 18 19 20 21 22 23 24

8 7 6 5 4 3 2 1 SOFT5 COMP5 I5SNS V5SNS V5SW REG5 VIN H5STR SOFT3 COMP3 I3SNS V3SNS V131N REG12 (*) H3STR 17 18 19 20 21 22 23 24

2

17

VREF +ER 1

VCC -ER 2

OUT-B COMP 3

GND CS-START 4

VC 4uF7 2 5 V

RESET 5 C28

OUT-A 6

-CS 7

SYNC +CS

11 8

CT RT 9

RDETIME SHDOWN 1

7 8 9

14 13 12

0V

0V

g

g

g

g

3

3

3

3 4

4

4

4

4

4 U14 TRAVERSEE4

U6 TRAVERSEE4

U4 TRAVERSEE4

U2 TRAVERSEE4

1

1

1

1

U23 TRAVERSEE4

g

0V

0V

0V

3

U20 TRAVERSEE4

3 BRIDE1

2 1 1 0 1 91 {FOURNISSEUR}

g

g

2 3

3

3

3

3

3 4

4

4

4

4

4 PAST2 FIX

2 PAST1 FIX

U3 TRAVERSEE4

U5 TRAVERSEE4

U7 TRAVERSEE4

U15 TRAVERSEE4

U21 TRAVERSEE4

g

g

g

g

g

PAST4 FIX

U24 TRAVERSEE4

PAST3 FIX

g

g

g

2

2

2

2 3

3

3

3

3

3 4

4

4

4

4

4

PAST6 FIX

2 PAST5 FIX

g

g

U8 TRAVERSEE4

U9 TRAVERSEE4

U12 TRAVERSEE4

U16 TRAVERSEE4

U22 TRAVERSEE4

U25 TRAVERSEE4

687 FIX

g

686 FIX

g

g

1 g

g

g

g

g

g

g

2 2 2 2 2 2 2 2

1 1 1

1 1 1 1 1 1 1

2

g

1

2 g

1

2

1

2 g g {OBSERVATION}

1

2

1

1

1

2

1

1 1 1

2

1

2

2

2 1

2 1

1 1 1 1 1 1 208070C SIGLE

1

U10 TRAVERSEE2

U11 TRAVERSEE2

U13 TRAVERSEE2

U17 TRAVERSEE2

U18 TRAVERSEE2

U19 TRAVERSEE2

U26 TRAVERSEE2

U27 TRAVERSEE2

+ 5V

+ 5V

Y_tv Y_peri Y_db25 Y_svhs C_svhs

Y_tv Y_peri Y_db25 Y_svhs C_svhs

L18 10uH

Y_tv Y_peri Y_db25 Y_svhs C_svhs

C175 10uF 16V

gnda

10uF 16V

C133

L16 10uH

1nF

C131

680nF

680nF

C169

C170

gnda

gnda

C180 68pF

C179 68pF

C177 100nF

+5V

gnda

C176 2nF2

1nF

680nF

C168

C174

16V

10uF

C181 10uF 16V

20Mhz25

X3

gnda

gndd

C178 10uF 16V

10uF 16V

C149

gnda

C137

C145 4nF7

680nF

+5V

gnda

100nF

C167

2nF2

gnda

680nF

C127

C136

680nF

C126

C134

680nF

680nF

C125

C124

61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9

C182 2nF2

VIN2 VIN1 CIN VOUT ASGF VSUPF I SG N D VRT GNDF GNDF CLK5 VSTBY XTAL2 XTAL1 GNDF NC GNDP

VIN2 VIN1 CIN VOUT ASGF VSUPF I S G ND VRT GNDF GNDF CLK5 VSTBY XTAL2 XTAL1 GNDF NC GNDP

2nF2

C150

gndd

gndd

gndd

gndd

gnda

Yb_out

gndd

gnda

61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9

gnda

R134 330R gndd

R132 330R

gndd

SCL SDA

IC17 VPC3215C {OBSERVATION}

gnda

R179 330R gndd

gndd

reset

C164 10uF 16V

R176 330R

+5V

SCL

13Mhz5_a 27Mhz_a Hsync_a Vsync_a odd/even_a

IC21 VPC3215C {OBSERVATION}

C2 C3 C4 C5 C6 C7 NC VSUPP GNDP GNDD NC NC VSUPD CLK20 Y0 Y1 NC

13Mhz5_b 27Mhz_b Hsync_b Vsync_b odd/even_b

gndd

gndd

43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27

SCL

C166 10nF

gnda

gndd

43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27

C159 1nF

S DA _ 1

C165 1nF

C2 C3 C4 C5 C6 C7 NC VSUPP GNDP GNDD NC NC VSUPD CLK20 Y0 Y1 NC

reset

C115 10nF

C160 10nF

1nF

C190

R180 330R

C161 10uF 16V

R135 330R

R133 330R

R177 330R

SDA

C191 10nF

Href_a gnda

+5V

C192 10uF 16V

RC0 AVO AVI FSY SCL SDA PRIO2 PRIO1 PRIO0 C0 C1 C2 C3 C4 C5 C6 C7

RC0 AVO AVI FSY SCL SDA PRIO2 PRIO1 PRIO0 C0 C1 C2 C3 C4 C5 C6 C7

+5V

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

gndd

+ 5V

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

C116 1nF

+3V3

C117 10nF

C118 10uF 16V

IC18 CIP3250A {OBSERVATION}

C154 10uF 16V gndd

C155 10nF

gndd

C156 1nF

gndd

IC22 CIP3250A {OBSERVATION}

C185 10uF 16V

+ 5V

gndd

C186 10nF

gndd

C187 1nF

gndd

C157 2nF2

gnda

gnda

100nF

C184

C188 2nF2

gnda

gnda

100nF

C183 10uF 16V

gnda

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

reset

B0 B1 B2 B3 B4 B5 B6 B7 STANDBY GNDRV RV GNDGY GY GNDBU BU GNDFB FB

gnda

gnda

C189 10uF 16V

L19 10uH + 5V

680nF

C272 FB

680nF

680nF

C271

C270

gndd

C172 10nF

uvb0 uvb1 uvb2 uvb3 uvb4 uvb5 uvb6 uvb7

C158 10uF 16V

L17 10uH

BU

GY

RV

gnd

peri_CR

peri_B

peri_G

peri_R

R287 75R

SC3_in_l

yb[0..7]

+3V3 C173 10uF 16V

uvb[0..7]

R286 75R

yb0 yb1 yb2 yb3 yb4 yb5 yb6 yb7

+ 5V

680nF

FB

680nF

C140

680nF

ya0 ya1 ya2 ya3 ya4 ya5 ya6 ya7

uva4 uva5 uva6 uva7

C143

C138

MNR14

gnda

C171 1nF

M N R 1 4 R175 100Rx4 7 8 5 6 3 4 1 2 7 8 5 6 3 4 1 2 R178 100Rx4

M N R 1 4 R172 100Rx4 7 8 5 6 3 4 1 2 7 8 5 6 3 4 1 2 M N R 1 4 R174 100Rx4

C153

C152 10uF 16V

gnda

gnda gnda

R159 100R

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

reset

B0 B1 B2 B3 B4 B5 B6 B7 STANDBY GNDRV RV GNDGY GY GNDBU BU GNDFB FB

MNR14

M N R 1 4 R131 100Rx4 7 8 5 6 3 4 1 2 7 8 5 6 3 4 1 2 R136 100Rx4

M N R 1 4 R128 100Rx4 uva0 7 8 uva1 5 6 uva2 3 4 uva3 1 2 7 8 5 6 3 4 1 2 M N R 1 4 R129 100Rx4

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

C114 1nF

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

VIN3 GNDF VIN4 TEST SCL SDA RESQ FPDAT VGAV GNDP PR2 PR1 PR0 C0 C1 NC NC

INTLC NC VS FSY MSY/HS HELPER HC AVO LLC2 LLC1 Y7 Y6 Y5 Y4 Y3 Y2 GNDP

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

VIN3 GNDF VIN4 TEST SCL SDA RESQ FPDAT VGAV GNDP PR2 PR1 PR0 C0 C1 NC NC

INTLC NC VS FSY MSY/HS HELPER HC AVO LLC2 LLC1 Y7 Y6 Y5 Y4 Y3 Y2 GNDP

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

gnd

C113 10uF 16V

Href_b

SC3_in_r

RC1 RC2 RC3 RC4 RC5 RC6 RC7 PVDD PVSS GL0 GL1 GL2 GL3 GL4 GL5 GL6 GL7 L0 L1 L2 L3 L4 L5 L6 L7 DVSS DVDD CLK RESQ TMODE AVDD AVSS ADREF SUBS 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RC1 RC2 RC3 RC4 RC5 RC6 RC7 PVDD PVSS GL0 GL1 GL2 GL3 GL4 GL5 GL6 GL7 L0 L1 L2 L3 L4 L5 L6 L7 DVSS DVDD CLK RESQ TMODE AVDD AVSS ADREF SUBS 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

+ 5V

12 11 10 9 8 7 6 5 4 3 2 1

J13

reset

10K

C132 47uF 16V

D52 BAS16

R270

Yb_out

gnd

ya[0..7]

uva[0..7]

Y_db25

+ 5V

gndd

gnd

gnda

gnda

sgnd

sgnd

C268 1uF 50V

C260

1K

R144

T18 BC847B

R138 100R

+ 5V

SCL

SDA

10nF

+ 5V

R271 330R

R273 330R

Hsync_b

Vsync_b

clk20 C269

100nF

C266

C265 47uF 16V

C263 10uF 16V

C259 2nF2

C135 100nF

4R7

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

26

25

A16 24

R272

FB

gnda

sgnd

3

2

D1 1 D0

gnd

gndd

13Mhz5_b 27Mhz_b Hsync_b Vsync_b Href_b odd/even_b

R148 2K2

100nF

gnd

yb0 yb1 yb2 yb3 yb4 yb5 yb6 yb7

C264 10uF 16V

C267 2nF2

gndd

R147 10K

R137 10K

+ 5V

uvb0 uvb1 uvb2 uvb3 uvb4 uvb5 uvb6 uvb7

IR_out com_L com_16/9

SCL SDA S D A _1

A_MISO_IR A_MOSI A_OFF_CLK A _R E S E T

IC26

SCL

SDA

A16

A15

A14

A13

A12

A11

PGND

PVSUP

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5/CAS

D4/RAS

WE

D3/DATA

HSYNC/MSYNC

VSYNC/CSYNC

XTAL2

D2 TEST

ya[0..7]

uva[0..7]

XTAL1/CLK20

RESET

FBIN/PRIO0

BIN/PRIO1

GIN/PRIO2

RIN/COL4

DVSUP

DGND

FBOUT/COL3

BOUT/COL2

GOUT/COL1

ROUT/COL0

AGND

AVSUP

VIN1

SGND

VIN2

VRT

D0

D1

TPU3050

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

J10

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

A15

A14

A13

A12

A11

gndd

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

45 D 7

46 D 6

47 D 5

48 D 4

49

50 D 3

51

52 D 2

+12V

+3V3

+ 5V

gndd

C274 100nF

gndd

gnd

gndd

gndd

+ 5V

Date:

Size

D7 D6 D5 D4 D3

A10

A13 A8 A9 A11

A15

Thursday, December 30, 1999

Document Number

ANALOG_VIDEO PL2

21, Rue Galilée 77420 CHAMPS SUR MARNE Title

AMITEK

+ 5V

D[0..7]

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

C273 + 5V 100nF

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

J11

Vcc A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GM76C8128

NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND

IC27

gndd

gndd

1 A16 2 A14 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 13 14 15 16

A[0..16]

R 266 1K

13Mhz5_a 27Mhz_a Hsync_a Vsync_a Href_a odd/even_a

ya0 ya1 ya2 ya3 ya4 ya5 ya6 ya7

uva0 uva1 uva2 uva3 uva4 uva5 uva6 uva7

D0 D1 D2

Sheet

208070 4

of

5

C

Rev

Tél 01 64 73 95 70 Fax 01 64 73 95 58 e_mail :[email protected]

C277

C141 47pF

X2

C249

S3 S2

100uF 25V Dalle NEC

20Mhz25

47uF 16V 110V Seul

0R

S4 0R S5 0R

R23

470R

0R

AMITEK 21, Rue Galilée 77420 CHAMPS sur MARNE Tél 01 64 73 95 70 Fax 01 64 73 95 58 [email protected] Title

{Title} Size A4

Document Number

Date:

Thursday, December 30, 1999

Rev

{Doc} Sheet

{RevCode} 5

of

5

8

7

6

5v

5

C259

27

gnda

16

C

VCC

C1+

1

C258

2

C+

C1-

3

100nF

6

C-

C2+

4

15

GND

C2-

5

14 13

RSOUT1 RSIN1

TTLIN1 TTLOUT1

11 12

7 8

RSOUT2 RSIN2

TTLIN2 TTLOUT2

10 9

C261

1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13

3

IC31 M AX202EC SE

100nF PR1

D

4

100nF D

C262 100nF

5v

txd rxd

gnd 330R

gnda

D2

D3

BAS16

BAS16

R124

sda

gnda

sc3_in_r sc3_in_l

C

330R

R125

scl

12v

1K

1

C260

100nF

gnd

2

D4

D5

BAS16

BAS16

gnda

R127

ir_out D7

gnda

BAS16 26

C264 390pF

R129 75R

C263 R126 100nF 75R

gnda

B

gnda

gnda

R128

gnda J9

75R

y_db25

1 2 3 4 5 6 7 8 9 10 11 12

470R 470R

R130

R142

75R

R143

2 3 1

PR2

2 3 1

PR3

2 3 1

PR4

12v

5v B

12v 5v gnd gnd gnda gnda

gnda

R141 100K

CON12 A

R140 100K

gnda

AMITEK A

gnda Title PDE: Digital Analog I/O gnda

8

7

gnda

6

5

4

Size A

Document Number ANA.SCH

Date:

Thursday, December 30, 1999 3

Rev B Sheet 2

2

of

11 1

A

B

C

D

10pF

C273

10pF

C274

10pF

8

gen2_sclk gen2_sdata

gnd_cg2

5v 3v3 gnd

gen1_sclk gen1_sdata

gnd_cg1

C82

10pF

C81

8

330R 330R

gnd

5v

330R 330R

R152 R153

X3 14.31818MHz

3v3

R28 R29

X1 14.31818MHz

7

12 14

16 15 1 2

6 7 11

12 14

16 15 1 2

6 7 11

7

IC32 ICD2061ASC-1 Cypress

INIT0 INIT1

PWRDWN INTCLK S0/CLK S1/DATA

XTALIN XTALOUT FEATCLK

IC7 ICD2061ASC-1 Cypress

INIT0 INIT1

PWRDWN INTCLK S0/CLK S1/DATA

XTALIN XTALOUT FEATCLK

GND

VDD AVDD

ERROUT

MCKLOUT VCLKOUT OE

GND

VDD AVDD

ERROUT

MCKLOUT VCLKOUT OE

6

gnd_cg2

5

13 3

10

8 9 4

gnd_cg1

5

13 3

10

8 9 4

6

gnd

R65

R64

T P 21 TEST

R33

22R

gnd

T P 90 TEST

R77

FB9 B L M 2 1 A 1 21S

/gen2_err

22R

FB7 B L M 2 1 A 1 21S

22R

FB8 B L M 2 1 A 1 21S

/gen1_err

22R

FB4 B L M 2 1 A 1 21S

R32

FB3 B L M 2 1 A 1 21S

22R

R30 22R

5

5v

100nF

C74

100nF

C271

gnd_cg2

5v

gnd

3v3

10nF

C76

frc1_clk frc2_clk

dice2_ref_clk

dice1_ref_clk

frc2_ref_clk

gnd_cg1

T P 23 TEST

R151 22R

gnd_cg2

C272 100nF

5v

T P 89 TEST

fs1_ref_clk

fs2_ref_clk

gnd_cg1

C75 100nF

5v

T P 22 TEST

5

4

gnd

4

100pF

C78

R34 75R

100pF

C80

10nF

C77

T P 25 TEST

100pF

C79

T P 26 TEST

3

3

5 12

4 13

9 8

16 1

6 7 10 11

2 3 14 15

2

Thursday, December 30, 1999

Date:

R31

Document Number CLOCK.SCH

PDE: Clock Driver

22R

FB2 B L M 2 1 A 1 21S

Size B

Title

A M I T EK

CLKB1 CLKB2 CLKB3 CLKB4

CLKA1 CLKA2 CLKA3 CLKA4

CY2308SC-1 Cypress

GND GND

VDD VDD

S1 S2

FBK REF

IC8

2

T P 20 TEST

T P 24 TEST

Sheet

3 1

of

frc1_ref_clk

/clock_bypass

1

11

Rev B

A

B

C

D

A

B

C

D

gnd

8

sda_1 sda scl

10 9 8 7 6 5 4 3 2 1

100nF

C250

5v

gnd

5v

sclk

dnld

s_mosi /scs usb_l_e s_miso usb_id

R148 4K7

gnd

J8 Download

pc_vsync s_miso s_mosi txd rxd /scs sclk

com_l com_16/9 pc_hsync pc_h_pol pc_v_pol /vid_reset

R147 4K7

5v

gnd

5v

a_miso/ir a_mosi a_sclk/off a_reset

/sdi_oe sdi_error

5v

gnd

5v

NC

VCC

CLK

GND

TP65 TEST

TP70 TEST

TP69 TEST

gnd

TP75 TEST

TP68 TEST

2

3

TP66 TEST

TP71 TEST

40MHz/FXO-31F KSS

1

4

IQ3

TP67 TEST

TP79 TEST

R106 4K7

5v

TP74 TEST

7

7

TP77 TEST

gnd

4K7

4K7

gnd

R114

4K7

R99

cpu_addr16 cpu_addr17 cpu_addr18

com_l com_16/9 pc_hsync pc_h_pol pc_v_pol /vid_reset usb_id pc_vsync s_miso s_mosi txd rxd /scs sclk

usb_d_r usb_l_e

R108

R116

22R

FB11 BLM21A121S

TP76 TEST

4K7

gnd

5v

4K7

C300 10nF

100nF

C251

sda_1 sda scl

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

gnd

R112

R115

gnd

4K7

R100

5v

a_miso/ir a_mosi a_sclk/off a_reset

R181 4K7

dnld

P5.11 P5.12 P5.13 P5.14 P5.15 VSS XTAL1 XTAL2 VDD P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.15 P4.0 P4.1 P4.2 P4.3 VSS VDD

gnd

5v

6

5v

R183 4K7

R173 4K7

gnd

5v SDI option R182 4K7

NO SDI

5v

4K7

/cs1

R107

d_miso d_mosi d_sclk d_reset

IC26 ST 10R 165 B Q 1 SGS

6

gnd

5v

gnd

5v

100nF

C248

100nF

C243

gnd

4

3

2

1

100nF

C244

/cpu_ready /cpu_wr /cpu_rd

VCC

SDA

SCL 5

6

7

8

100nF

C246

SW1 SW BTL

MOD/WC

100nF

C245

ST24C16M1 SGS

VSS

PB1

PB0

PRE

IC28

gnd

VDD VSS P1H.7 P1H.6 P1H.5 P1H.4 P1H.3 P1H.2 VSS VDD P1H.1 P1H.0 P1L.7 P1L.6 P1L.5 P1L.4 P1L.3 P1L.2 P1L.1 P1L.0 P0H.7 P0H.6 P0H.5 P0H.4 P0H.3 P0H.2 P0H.1 P0H.0 VSS VDD

R97

5

R98

100nF

330R

5v

4K7

sda

scl

100nF

C249

1K

1K

gnd

R103 R104 R105

cpu_data7 cpu_data6 cpu_data5 cpu_data4 cpu_data3 cpu_data2 cpu_data1 cpu_data0

R102

1K 1K 1K

R101

nconfig dclk

pld_data

cpu_addr9 cpu_addr8 cpu_addr7 cpu_addr6 cpu_addr5 cpu_addr4 cpu_addr3 cpu_addr2 cpu_addr1 cpu_addr0

R174

C247

gnd

100nF

C252

cpu_addr15 cpu_addr14 cpu_addr13 cpu_addr12 cpu_addr11 cpu_addr10

330R

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

5

gnd

4

4

5v

gnd

IC25 MAX809

cpu_data1 cpu_data2 cpu_data3 cpu_data4 cpu_data5 cpu_data6 cpu_data7

cpu_addr7 cpu_addr6 cpu_addr5 cpu_addr4 cpu_addr3 cpu_addr2 cpu_addr1 cpu_addr0 cpu_data0 5 6 7 8 9 10 11 12 13

IC27 M29F040-90K1 SGS

cpu_addr17 cpu_addr18 cpu_addr16 cpu_addr15 cpu_addr12

2

8

3 RST VCC GND 1

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

P5.10 P2.15 P2.14 P2.13 P2.12 P2.11 P2.10 P2.9 P2.8 P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 NMI RSTOUT RSTIN

P4.4 P4.5 P4.6 P4.7 RD WR/WRL READY ALE EA VDD VSS VPP P0L.0 P0L.1 P0L.2 P0L.3 P0L.4 P0L.5 P0L.6 P0L.7

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

A7 A6 A5 A4 A3 A2 A1 A0 Q0

5v

3

4 3 2 1 32 31 30 A12 A15 A16 A18 VCC W A17 Q1 Q2 VSS Q3 Q4 Q5 Q6 3

14 15 16 17 18 19 20 gnd

A14 A13 A8 A9 A11 G A10 E Q7

TP81 TEST

29 28 27 26 25 24 23 22 21

TP80 TEST

R113 4K7

0R

0R

R176

R175

TP73 TEST

100nF

C253

NC

TP72 TEST

gnd

5v

cpu_addr10

cpu_addr14 cpu_addr13 cpu_addr8 cpu_addr9 cpu_addr11

5v

2

2

Document Number CPU.SCH Thursday, December 30, 1999

Date:

PDE: CPU Size C

Title

AMITEK

/pld_cs

/cpu_ready

cpu_data[0..7] cpu_addr[0..18]

pld_data nconfig dclk

power_good

pdp_hqen

bolt_power

d_miso d_mosi d_sclk d_reset

/debug_plug

Sheet 1

1

4

of

11

Rev B

A

B

C

D

A

B

C

D

8

3v3 gnd

dice1_ref_clk

dice1_clk

dice1_red[0..7]

dice1_blue[0..7]

dice1_green[0..7]

dice1_hblank dice1_vs dice1_vblank dice1_dv

dice1_hs

/vid_reset

s_mosi s_miso sclk /cs_dice1

vid1_clk

vid1_y[0..7]

vid1_uv[0..7]

vid1_hs vid1_vs vid1_href vid1_odd

8

gnd

3v3

dice1_clk

dice1_red0 dice1_red1 dice1_red2 dice1_red3 dice1_red4 dice1_red5 dice1_red6 dice1_red7

dice1_blue0 dice1_blue1 dice1_blue2 dice1_blue3 dice1_blue4 dice1_blue5 dice1_blue6 dice1_blue7

dice1_green4 dice1_green5 dice1_green6 dice1_green7

dice1_green0 dice1_green1 dice1_green2 dice1_green3

gnd

TP3 TEST

TP1 TEST

R7 75R NC

C4 100pF NC

s_mosi s_miso sclk /cs_dice1

TP4 TEST

7

TP5 TEST

7

TP6 TEST

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

gnd

3v3

R4 R5 R6

SCS RGB RESET OPSIZE0 OPSIZE1 OPSIZE2 ITU601 ITU656 HSYNC VDD GND HBLANK VSYNC VBLANK DV GIN2/GPO GIN3/GPO GND GREEN0 GREEN1 GREEN2 GREEN3 VDD GREEN4 GREEN5 GREEN6 GREEN7 GIN4 GND GND VDD GIN5 UV/BLUE0 UV/BLUE1 UV/BLUE2 UV/BLUE3 UV/BLUE4 UV/BLUE5 UV/BLUE6 VDD

330R 330R 330R

vid1_y0 vid1_y1 vid1_y2 vid1_y3 vid1_y4 vid1_y5 vid1_y6 vid1_y7

vid1_clk

TP8 TEST

6

vid1_uv0 vid1_uv1 vid1_uv2 vid1_uv3 vid1_uv4 vid1_uv5 vid1_uv6 vid1_uv7

vid1_hs vid1_vs vid1_href vid1_odd

5

gnd

R15 10K

160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 IC1 G M V L X1A Genesis

SCLK SDO SDI IPCLK VDD GND Y/RIN7 Y/RIN6 Y/RIN5 VDD GND Y/RIN4 Y/RIN3 Y/RIN2 Y/RIN1 Y/RIN0 UV/BIN7 UV/BIN6 UV/BIN5 UV/BIN4 UV/BIN3 UV/BIN2 UV/BIN1 UV/BIN0 VS CREF HREF HS ODD GND VDD AFPRFF RAMDQ31 RAMDQ30 RAMDQ29 RAMDQ28 RAMDQ27 RAMDQ26 GND RAMDQ25

UV/BLUE7 GND GIN6 GIN7 Y/RED0 Y/RED1 Y/RED2 Y/RED3 VDD DCLK GND GND Y/RED4 Y/RED5 Y/RED6 Y/RED7 GIN0/GPO GIN1/GPO VDD OPFSYNC OPCLK DTG/EN OE RAMDSF RAMCKE GND RAMWE RAMCAS GND RAMCLK VDD RAMRAS RAMOE RAMCS RAMADDR00 RAMADDR01 GND RAMADDR02 RAMADDR03 RAMADDR04

6

dice1_ref_clk

gnd

3v3

gnd

3v3

5

100nF

100nF

C20

100nF

100nF

C21

C23

C22

/ram1cs /ram1oe /ram1ras ram1clk /ram1cas /ram1we ram1cke ram1dsf

41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

100nF

C19

100nF

C24

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

100nF

C18

100nF

C25

RAMDQ24 RAMDQ23 RAMDQ22 RAMDQ21 RAMDQ20 VDD RAMDQ19 RAMDQ18 RAMDQ17 GND RAMDQ16 RAMDQ15 RAMDQ14 RAMDQ13 RAMDQ12 RAMDQ11 RAMDQ10 RAMDQ09 RAMDQ08 VDD GND GND RAMDQ07 RAMDQ06 VDD RAMDQ05 RAMDQ04 RAMDQ03 RAMDQ02 RAMDQ01 RAMDQ00 RAMADDR11 GND RAMADDR10 RAMADDR09 RAMADDR08 RAMADDR07 RAMADDR06 RAMADDR05 VDD

4

C29

100nF

C16

100nF

C27

ram1addr4 ram1addr3 ram1addr2 ram1addr1 ram1addr0

100nF

C15

100nF

gnd

100nF

3

ram1dq22 ram1dq23

ram1dq5 ram1dq4 ram1dq3 ram1dq2 ram1dq1 ram1dq0

C28

ram1dq20 ram1dq21

ram1dq7 ram1dq6

ram1addr9 ram1addr8 ram1addr7 ram1addr6 ram1addr5

ram1dq18 ram1dq19

ram1addr0 ram1addr1 ram1addr2 ram1addr3 ram1addr4 ram1addr5 ram1addr6 ram1addr7 ram1addr8

/ram1oe /ram1we /ram1cas /ram1ras /ram1cs ram1addr9

ram1dq16 ram1dq17

ram1dq6 ram1dq7

ram1dq4 ram1dq5

ram1dq16 ram1dq15 ram1dq14 ram1dq13 ram1dq12 ram1dq11 ram1dq10 ram1dq9 ram1dq8

100nF

C17

3v3

gnd

3v3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

ram1dq3

ram1dq0 ram1dq1 ram1dq2

10K

R8

10K

R9

10K

R10

3v3

ram1dq19 ram1dq18 ram1dq17

10K

R11

10K

R12

10K

R13

10K

R14

gnd

ram1addr[0..9]

ram1dq[0..31]

3

ram1dq24 ram1dq23 ram1dq22 ram1dq21 ram1dq20

ram1dq31 ram1dq30 ram1dq29 ram1dq28 ram1dq27 ram1dq26 ram1dq25

100nF

C26

4

100nF

C9

100nF

C10

DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ VDD VSS DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ DQM0 DQM2 WE CAS RAS CS A9 NC

gnd

3v3

gnd

3v3

2

100nF

C8

100nF

C11

100nF

C7

100nF

C12

100nF

C6

100nF

C13

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 IC2 KM4132G271A-12 Samsung

DQ28 VDDQ DQ27 DQ26 VSSQ DQ25 DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ NC DQM3 DQM1 CLK CKE DSF NC A8

DQ2 VSSQ DQ1 DQ0 VDD NC NC NC NC NC NC NC NC NC NC VSS DQ31 DQ30 VSSQ DQ29 A0 A1 A2 A3 VDD NC NC NC NC NC NC NC NC NC NC VSS A4 A5 A6 A7 2

Document Number DICE1.SCH Thursday, December 30, 1999

Date:

PDE: De-Interlacing/Scaling 1 Size C

Title

AMITEK

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

Sheet

100nF

C5

100nF

C14

1

1

5

/ram1oe ram1clk ram1cke ram1dsf

ram1dq9 ram1dq8

ram1dq11 ram1dq10

ram1dq13 ram1dq12

ram1dq15 ram1dq14

ram1dq25 ram1dq24

ram1dq27 ram1dq26

ram1dq28

10K

R150

ram1dq31 ram1dq30 ram1dq29

of

3v3

11

Rev B

A

B

C

D

A

B

C

D

3v3 gnd

dice2_ref_clk

/dice2_oe

dice2/pc_red[0..7]

dice2/pc_blue[0..7]

dice2/pc_green[0..7]

dice2/pc_hs dice2_hblank dice2/pc_vs dice2_vblank dice2_dv dice2/pc_clk

/vid_reset

s_mosi s_miso sclk /cs_dice2

vid2_clk

vid2_y[0..7]

vid2_uv[0..7]

vid2_hs vid2_vs vid2_href vid2_odd

8

8

gnd

3v3

100nF

C165

gnd

3v3

C168

100nF

100nF

3v3

100nF

C166

3v3

C167

dice2/pc_blue0 dice2/pc_blue1 dice2/pc_blue2 dice2/pc_blue3 dice2/pc_blue4 dice2/pc_blue5 dice2/pc_blue6 dice2/pc_blue7 dice2/pc_red0 dice2/pc_red1 dice2/pc_red2 dice2/pc_red3 dice2/pc_red4 dice2/pc_red5 dice2/pc_red6 dice2/pc_red7

gnd

3v3

dice2/pc_hs dice2_hblank dice2/pc_vs dice2_vblank dice2_dv dice2/pc_clk dice2/pc_green0 dice2/pc_green1 dice2/pc_green2 dice2/pc_green3 dice2/pc_green4 dice2/pc_green5 dice2/pc_green6 dice2/pc_green7

gnd

gnd

GND GND GND GND GND GND GND GND

VCC VCC VCC VCC

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16

S1 S2 S3 S4 S5 S6 S7 S8

M1 M2 M3 M4

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16

IC17

GND GND GND GND GND GND GND GND

VCC VCC VCC VCC

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16

7

S1 S2 S3 S4 S5 S6 S7 S8

M1 M2 M3 M4

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16

CY74UBL3911PAC Cypress

6 12 17 23 34 40 45 51

9 20 37 48

4 5 7 8 10 11 13 14 15 16 18 19 21 22 24 25

CY74UBL3911PAC Cypress

6 12 17 23 34 40 45 51

9 20 37 48

4 5 7 8 10 11 13 14 15 16 18 19 21 22 24 25

IC16

7

1 2 27 28 29 30 55 56

3 54 31 26

53 52 50 49 47 46 44 43 42 41 39 38 36 35 33 32

1 2 27 28 29 30 55 56

3 54 31 26

53 52 50 49 47 46 44 43 42 41 39 38 36 35 33 32

gnd

gnd

3v3

/dice2_oe

dice2_blue0 dice2_blue1 dice2_blue2 dice2_blue3 dice2_blue4 dice2_blue5 dice2_blue6 dice2_blue7 dice2_red0 dice2_red1 dice2_red2 dice2_red3 dice2_red4 dice2_red5 dice2_red6 dice2_red7

3v3

/dice2_oe

dice2_clk dice2_green0 dice2_green1 dice2_green2 dice2_green3 dice2_green4 dice2_green5 dice2_green6 dice2_green7

dice2_vs

dice2_hs

3v3

R62 10K

gnd

TP42 TEST

TP37 TEST

R53 75R NC

C138 100pF NC

s_mosi s_miso sclk /cs_dice2

TP38 TEST

TP39 TEST

6

6

TP40 TEST

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

gnd

3v3

R50 R51 R52

22R

R63

FB6 BLM21A121S

SCS RGB RESET OPSIZE0 OPSIZE1 OPSIZE2 ITU601 ITU656 HSYNC VDD GND HBLANK VSYNC VBLANK DV GIN2/GPO GIN3/GPO GND GREEN0 GREEN1 GREEN2 GREEN3 VDD GREEN4 GREEN5 GREEN6 GREEN7 GIN4 GND GND VDD GIN5 UV/BLUE0 UV/BLUE1 UV/BLUE2 UV/BLUE3 UV/BLUE4 UV/BLUE5 UV/BLUE6 VDD

330R 330R 330R

vid2_y0 vid2_y1 vid2_y2 vid2_y3 vid2_y4 vid2_y5 vid2_y6 vid2_y7 vid2_clk

TP43 TEST

vid2_uv0 vid2_uv1 vid2_uv2 vid2_uv3 vid2_uv4 vid2_uv5 vid2_uv6 vid2_uv7

5

vid2_hs vid2_vs vid2_href vid2_odd

gnd

R61 10K

160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 IC14 G M V LX1A Genesis

SCLK SDO SDI IPCLK VDD GND Y/RIN7 Y/RIN6 Y/RIN5 VDD GND Y/RIN4 Y/RIN3 Y/RIN2 Y/RIN1 Y/RIN0 UV/BIN7 UV/BIN6 UV/BIN5 UV/BIN4 UV/BIN3 UV/BIN2 UV/BIN1 UV/BIN0 VS CREF HREF HS ODD GND VDD AFPRFF RAMDQ31 RAMDQ30 RAMDQ29 RAMDQ28 RAMDQ27 RAMDQ26 GND RAMDQ25 UV/BLUE7 GND GIN6 GIN7 Y/RED0 Y/RED1 Y/RED2 Y/RED3 VDD DCLK GND GND Y/RED4 Y/RED5 Y/RED6 Y/RED7 GIN0/GPO GIN1/GPO VDD OPFSYNC OPCLK DTG/EN OE RAMDSF RAMCKE GND RAMWE RAMCAS GND RAMCLK VDD RAMRAS RAMOE RAMCS RAMADDR00 RAMADDR01 GND RAMADDR02 RAMADDR03 RAMADDR04 5

dice2_ref_clk

gnd

3v3

gnd

3v3

C154 100nF

100nF

100nF

100nF

C155

C157

C156

/ram2cs /ram2oe /ram2ras ram2clk /ram2cas /ram2we ram2cke ram2dsf

41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

4

100nF

C153

100nF

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

100nF

C152

100nF

C159

RAMDQ24 RAMDQ23 RAMDQ22 RAMDQ21 RAMDQ20 VDD RAMDQ19 RAMDQ18 RAMDQ17 GND RAMDQ16 RAMDQ15 RAMDQ14 RAMDQ13 RAMDQ12 RAMDQ11 RAMDQ10 RAMDQ09 RAMDQ08 VDD GND GND RAMDQ07 RAMDQ06 VDD RAMDQ05 RAMDQ04 RAMDQ03 RAMDQ02 RAMDQ01 RAMDQ00 RAMADDR11 GND RAMADDR10 RAMADDR09 RAMADDR08 RAMADDR07 RAMADDR06 RAMADDR05 VDD

C158

4

100nF

C150

100nF

C161

ram2addr4 ram2addr3 ram2addr2 ram2addr1 ram2addr0

100nF

C151

3v3

C163

100nF

C149

100nF

3

gnd

100nF

ram2dq22 ram2dq23

ram2dq5 ram2dq4 ram2dq3 ram2dq2 ram2dq1 ram2dq0

C162

ram2dq20 ram2dq21

ram2dq7 ram2dq6

ram2addr9 ram2addr8 ram2addr7 ram2addr6 ram2addr5

ram2dq18 ram2dq19

ram2addr0 ram2addr1 ram2addr2 ram2addr3 ram2addr4 ram2addr5 ram2addr6 ram2addr7 ram2addr8

/ram2oe /ram2we /ram2cas /ram2ras /ram2cs ram2addr9

ram2dq16 ram2dq17

ram2dq6 ram2dq7

ram2dq4 ram2dq5

ram2dq16 ram2dq15 ram2dq14 ram2dq13 ram2dq12 ram2dq11 ram2dq10 ram2dq9 ram2dq8

100nF

C160

3v3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

gnd

ram2dq19 ram2dq18 ram2dq17

ram2dq3

ram2dq0 ram2dq1 ram2dq2

10K

R54

10K

R55

10K

R56

3v3

gnd

ram2addr[0..9]

ram2dq[0..31]

10K

R57

10K

R58

10K

R59

10K

R60

ram2dq24 ram2dq23 ram2dq22 ram2dq21 ram2dq20

ram2dq31 ram2dq30 ram2dq29 ram2dq28 ram2dq27 ram2dq26 ram2dq25

3

2

100nF

C141

100nF

C146

100nF

C140

100nF

C147

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

Sheet

100nF

C139

100nF

C148

1

ram2dq31 ram2dq30 ram2dq29

IC15 KM4132G271A-12 Samsung

DQ28 VDDQ DQ27 DQ26 VSSQ DQ25 DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ NC DQM3 DQM1 CLK CKE DSF NC A8

PDE: De-Interlacing/Scalling 2

Date:

Thursday, December 30, 1999

Size Document Number Custom D I C E 2 . S C H

Title

AMITEK

6

/ram2oe ram2clk ram2cke ram2dsf

ram2dq9 ram2dq8

ram2dq11 ram2dq10

ram2dq13 ram2dq12

ram2dq15 ram2dq14

ram2dq25 ram2dq24

ram2dq27 ram2dq26

ram2dq28

10K

100nF

C142

100nF

C145

1

R149

100nF

C143

100nF

C144

DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ VDD VSS DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ DQM0 DQM2 WE CAS RAS CS A9 NC

gnd

3v3

gnd

3v3

2

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQ2 VSSQ DQ1 DQ0 VDD NC NC NC NC NC NC NC NC NC NC VSS DQ31 DQ30 VSSQ DQ29 A0 A1 A2 A3 VDD NC NC NC NC NC NC NC NC NC NC VSS A4 A5 A6 A7 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

of

3v3

11

Rev B

A

B

C

D

A

B

C

D

gnd

3v3

100nF

100nF

8

5v 3v3 gnd

dice1_blue[0..7]

frc1_clk

frc1_ref_clk

dice1_green[0..7]

gnd

5v

TP15 TEST

C53

C54

100nF

100nF

dice1_vs dice1_clk dice1_cref dice1_hs dice1_red[0..7]

gnd

5v

gnd

C39

100nF

C33

C38

100nF

100nF

3v3

C32

C31

8

3v3

TP16 TEST

gnd

3v3

TP17 TEST

C52 100nF

100nF

C40

100nF

C34

frc1_green7 frc1_green6 frc1_green5 frc1_green4 frc1_green3 frc1_green2 frc1_green1 frc1_green0

dice1_blue7 dice1_blue6 dice1_blue5 dice1_blue4 dice1_blue3 dice1_blue2 dice1_blue1 dice1_blue0

frc1_clk

dice1_green4 dice1_green3 dice1_green2 dice1_green1 dice1_green0 frc1_ref_clk

dice1_green5

dice1_hs dice1_red7 dice1_red6 dice1_red5 dice1_red4 dice1_red3 dice1_red2 dice1_red1 dice1_red0 dice1_green7 dice1_green6

7

TP19 TEST

100nF

C42

100nF

C36

dice1_vs dice1_clk dice1_cref

TP18 TEST

C51 100nF

100nF

C41

100nF

C35

7

22R

R17 10K

157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208

gnd

3v3

R27

FB1 BLM21A121S

3v3

R16 10K

5v

3v3

100nF

C43

100nF

C37

6

5

156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105

GND IN/UV0 IN/UV1 IN/UV2 IN/UV3 IN/UV4 IN/UV5 GND IN/UV6 VCC IN/UV7 IN/Y0 IN/Y1 IN/Y2 IN/Y3 IN/Y4 IN/Y5 IN/Y6 IN/Y7 INVVS INODD INVHS INVCREF INVCLK +5V GND VCC INGVS INRAWGHS INGCLK INGCREF INGHS IN/RED7 IN/RED6 IN/RED5 IN/RED4 IN/RED3 IN/RED2 IN/RED1 IN/RED0 IN/GREEN7 IN/GREEN6 GND IN/GREEN5 VCC IN/GREEN4 IN/GREEN3 IN/GREEN2 IN/GREEN1 IN/GREEN0 REFOUTCLK GND Genesis

IC3 gmFC1CR1

GND FSD38 FSD39 FSD40 FSD41 FSD42 FSD43 FSD44 FSD45 GND GND VCC VCC FSD46 FSD47 FSDQM1 FSWE FSDQM0 FSCAS FSCLK GND FSRAS FSCKE FSCS FSA11 GND VCC FSA9 FSA10 FSA8 FSA0 GND FSA7 VCC FSA1 FSA6 FSA2 FSA5 FSA3 GND GND VCC VCC FSA4 FRAMERESET LREQ DATAREQ OUTODD OUTHS OUTVS OUTDFSYNC GND

VCC INVADC/SCP CLAMP/MSBF FSD0 FSD1 FSD2 FSD3 FSD4 GND FSD5 VCC FSD6 FSD7 FSD8 FSD9 FSD10 FSD11 GND FSD12 VCC FSD13 FSD14 FSD15 FSD16 FSD17 GND VCC FSD18 FSD19 FSD20 FSD21 FSD22 FSD23 GND FSD24 VCC FSD25 FSD26 FSD27 FSD28 FSD29 FSD30 GND FSD31 VCC FSD32 FSD33 FSD34 FSD35 FSD36 FSD37 VCC

VCC OUTCLK OUTSTALL IN/BLUE7 IN/BLUE6 IN/BLUE5 IN/BLUE4 IN/BLUE3 IN/BLUE2 IN/BLUE1 IN/BLUE0 OUT/GREEN7 +5V OUT/GREEN6 OUT/GREEN5 OUT/GREEN4 GND OUT/GREEN3 VCC OUT/GREEN2 OUT/GREEN1 OUT/GREEN0 OUT/BLUE7 OUT/BLUE6 OUT/BLUE5 GND VCC OUT/BLUE4 OUT/BLUE3 OUT/BLUE2 OUT/BLUE1 OUT/BLUE0 OUT/RED0 GND OUT/RED1 VCC OUT/RED2 OUT/RED3 OUT/RED4 OUT/RED5 OUT/RED6 VCC OUT/RED7 GND SCLK SCS RESET SDI SDO INACT/IRQ FSREFCLK VCC

6

5v

5

TP9 TEST

frc1_red7 frc1_red6 frc1_red5 frc1_red4 frc1_red3 frc1_red2 frc1_red1 frc1_red0 frc1_blue7 frc1_blue6 frc1_blue5 frc1_blue4 frc1_blue3 frc1_blue2 frc1_blue1 frc1_blue0

330R

330R 330R

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53

R20

R18 R19

4

frc1_irq sclk s_mosi /cs_frc1 s_miso /vid_reset

/frc1_lock

frc1_dreq

/frc1_sync /frc1_lreq

22RX4

fs1d38 fs1d39 fs1d40 fs1d41 fs1d42 fs1d43 fs1d44 fs1d45 fs1d46 fs1d47 fs1clk

fs1d0 fs1d1 fs1d2 fs1d3 fs1d4 fs1d5 fs1d6 fs1d7 fs1d8 fs1d9 fs1d10 fs1d11 fs1d12 fs1d13 fs1d14 fs1d15 fs1d16 fs1d17 fs1d18 fs1d19 fs1d20 fs1d21 fs1d22 fs1d23 fs1d24 fs1d25 fs1d26 fs1d27 fs1d28 fs1d29 fs1d30 fs1d31 fs1d32 fs1d33 fs1d34 fs1d35 fs1d36 fs1d37

4

22RX4

R23

R24

R25

TP10 TEST

1 3 5 7 1 3 5 7 1 3 5 7

1 3 5 7

1 3 5 7

fs1dqm1 /fs1we fs1qdm0 /fs1cas

TP13 TEST

TP12 TEST

2 4 6 8 2 4 R22 6 8 2 4 R21 6 8

frc1_red[0..7] frc1_green[0..7] frc1_blue[0..7]

sclk s_mosi /cs_frc1 s_miso /vid_reset

fs1_ref_clk

TP14 TEST

TP11 TEST

fs1a11 fs1a9 fs1a10 fs1a8 fs1a0 fs1a7 fs1a1 fs1a6 fs1a2 fs1a5 fs1a3 fs1a4

/fs1ras 2 fs1cke 4 /fs1cs 6 8 22RX4

2 4 6 8

fs1d[0..47]

/frc1_lock

frc1_dreq

/frc1_sync /frc1_lreq

fs1a[0..11]

3

3

gnd

R26 100R

100pF

C67

35 34 17 16 15 18 36 14

fs1clk fs1cke /fs1ras /fs1cas /fs1we /fs1cs fs1dqm1 fs1qdm0

35 34 17 16 15 18 36 14

fs1clk fs1cke /fs1ras /fs1cas /fs1we /fs1cs fs1dqm1 fs1qdm0

2

10nF

C63

VDD VDD VDDQ VDDQ VDDQ VDDQ

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

10nF

C70

VDD VDD VDDQ VDDQ VDDQ VDDQ

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

1 25 7 13 38 44

2 3 5 6 8 9 11 12 39 40 42 43 45 46 48 49

1 25 7 13 38 44

2 3 5 6 8 9 11 12 39 40 42 43 45 46 48 49

1 25 7 13 38 44

2 3 5 6 8 9 11 12 39 40 42 43 45 46 48 49

3v3

fs1d0 fs1d1 fs1d2 fs1d3 fs1d4 fs1d5 fs1d6 fs1d7 fs1d8 fs1d9 fs1d10 fs1d11 fs1d12 fs1d13 fs1d14 fs1d15

100nF

C71

3v3

fs1d32 fs1d33 fs1d34 fs1d35 fs1d36 fs1d37 fs1d38 fs1d39 fs1d40 fs1d41 fs1d42 fs1d43 fs1d44 fs1d45 fs1d46 fs1d47

100nF

C64

3v3

fs1d16 fs1d17 fs1d18 fs1d19 fs1d20 fs1d21 fs1d22 fs1d23 fs1d24 fs1d25 fs1d26 fs1d27 fs1d28 fs1d29 fs1d30 fs1d31

100nF

C58

Document Number FRC1.SCH Thursday, December 30, 1999

Size C Date:

PDE: Frame Rate Converter 1

100nF

10nF

Title

C69

VSS VSS VSSQ VSSQ VSSQ VSSQ

CLK CKE RAS CAS WE CS UDQM LDQM

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

C68

AMITEK

26 50 4 10 41 47

21 22 23 24 27 28 29 30 31 32 20 19

gnd

100nF

fs1a0 fs1a1 fs1a2 fs1a3 fs1a4 fs1a5 fs1a6 fs1a7 fs1a8 fs1a9 fs1a10 fs1a11

10nF

C57

IC4 KM416S1020BT-G/F10 Samsung

C62 10nF

VSS VSS VSSQ VSSQ VSSQ VSSQ

CLK CKE RAS CAS WE CS UDQM LDQM

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

C61

gnd

35 34 17 16 15 18 36 14

fs1clk fs1cke /fs1ras /fs1cas /fs1we /fs1cs fs1dqm1 fs1dqm0

26 50 4 10 41 47

21 22 23 24 27 28 29 30 31 32 20 19

fs1a0 fs1a1 fs1a2 fs1a3 fs1a4 fs1a5 fs1a6 fs1a7 fs1a8 fs1a9 fs1a10 fs1a11

100nF

VDD VDD VDDQ VDDQ VDDQ VDDQ

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

IC5 KM416S1020BT-G/F10 Samsung

C56

10nF

VSS VSS VSSQ VSSQ VSSQ VSSQ

CLK CKE RAS CAS WE CS UDQM LDQM

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

IC6 KM416S1020BT-G/F10 Samsung

C55

26 50 4 10 41 47

21 22 23 24 27 28 29 30 31 32 20 19

fs1a0 fs1a1 fs1a2 fs1a3 fs1a4 fs1a5 fs1a6 fs1a7 fs1a8 fs1a9 fs1a10 fs1a11

gnd

2

Sheet 1

10nF

C72

10nF

C65

10nF

C59

1

7

gnd

3v3

gnd

3v3

gnd

3v3

of

100nF

C73

100nF

C66

100nF

C60

11

Rev B

A

B

C

D

A

B

C

D

gnd

3v3

pc_hs ync

5v 3v3 gnd

8

gnd

5v

dice2/pc_blue[0..7]

frc2_clk

frc2_ref_clk

dice2/pc_green[0..7]

3v3

TP50 TEST

100nF

100nF

pc_clamp

C191

C192

100nF

100nF

dice2/pc_vs dice2/pc_clk dice2/pc_cref dice2/pc_hs dice2/pc_red[0..7]

gnd

5v

gnd

C177

100nF

C171

C176

100nF

100nF

3v3

C170

C169

8

C190 100nF

TP51 TEST

gnd

3v3

100nF

C178

100nF

C172

100nF

C180

100nF

C174

TP53 TEST

frc2_green7 frc2_green6 frc2_green5 frc2_green4 frc2_green3 frc2_green2 frc2_green1 frc2_green0

dice2/pc_blue7 dice2/pc_blue6 dice2/pc_blue5 dice2/pc_blue4 dice2/pc_blue3 dice2/pc_blue2 dice2/pc_blue1 dice2/pc_blue0

frc2_clk

dice2/pc_green4 dice2/pc_green3 dice2/pc_green2 dice2/pc_green1 dice2/pc_green0 frc2_ref_clk

dice2/pc_green5

dice2/pc_hs dice2/pc_red7 dice2/pc_red6 dice2/pc_red5 dice2/pc_red4 dice2/pc_red3 dice2/pc_red2 dice2/pc_red1 dice2/pc_red0 dice2/pc_green7 dice2/pc_green6

dice2/pc_vs dice2/pc_clk dice2/pc_cref

pc_hs ync

TP52 TEST

C189 100nF

100nF

C179

100nF

C173

7

7

3v3

R66 10K

5v

TP54 TEST

3v3

100nF

C181

100nF

C175

R67 10K

157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208

gnd

3v3

6

5

156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105

GND IN/UV0 IN/UV1 IN/UV2 IN/UV3 IN/UV4 IN/UV5 GND IN/UV6 VCC IN/UV7 IN/Y0 IN/Y1 IN/Y2 IN/Y3 IN/Y4 IN/Y5 IN/Y6 IN/Y7 INVVS INODD INVHS INVCREF INVCLK +5V GND VCC INGVS INRAWGHS INGCLK INGCREF INGHS IN/RED7 IN/RED6 IN/RED5 IN/RED4 IN/RED3 IN/RED2 IN/RED1 IN/RED0 IN/GREEN7 IN/GREEN6 GND IN/GREEN5 VCC IN/GREEN4 IN/GREEN3 IN/GREEN2 IN/GREEN1 IN/GREEN0 REFOUTCLK GND Genesis

IC18 gmFC1CR1

GND FSD38 FSD39 FSD40 FSD41 FSD42 FSD43 FSD44 FSD45 GND GND VCC VCC FSD46 FSD47 FSDQM1 FSWE FSDQM0 FSCAS FSCLK GND FSRAS FSCKE FSCS FSA11 GND VCC FSA9 FSA10 FSA8 FSA0 GND FSA7 VCC FSA1 FSA6 FSA2 FSA5 FSA3 GND GND VCC VCC FSA4 FRAMERESET LREQ DATAREQ OUTODD OUTHS OUTVS OUTDFSYNC GND

VCC INVADC/SCP CLAMP/MSBF FSD0 FSD1 FSD2 FSD3 FSD4 GND FSD5 VCC FSD6 FSD7 FSD8 FSD9 FSD10 FSD11 GND FSD12 VCC FSD13 FSD14 FSD15 FSD16 FSD17 GND VCC FSD18 FSD19 FSD20 FSD21 FSD22 FSD23 GND FSD24 VCC FSD25 FSD26 FSD27 FSD28 FSD29 FSD30 GND FSD31 VCC FSD32 FSD33 FSD34 FSD35 FSD36 FSD37 VCC

VCC OUTCLK OUTSTALL IN/BLUE7 IN/BLUE6 IN/BLUE5 IN/BLUE4 IN/BLUE3 IN/BLUE2 IN/BLUE1 IN/BLUE0 OUT/GREEN7 +5V OUT/GREEN6 OUT/GREEN5 OUT/GREEN4 GND OUT/GREEN3 VCC OUT/GREEN2 OUT/GREEN1 OUT/GREEN0 OUT/BLUE7 OUT/BLUE6 OUT/BLUE5 GND VCC OUT/BLUE4 OUT/BLUE3 OUT/BLUE2 OUT/BLUE1 OUT/BLUE0 OUT/RED0 GND OUT/RED1 VCC OUT/RED2 OUT/RED3 OUT/RED4 OUT/RED5 OUT/RED6 VCC OUT/RED7 GND SCLK SCS RESET SDI SDO INACT/IRQ FSREFCLK VCC

6

5v

5

TP44 TEST

frc2_red7 frc2_red6 frc2_red5 frc2_red4 frc2_red3 frc2_red2 frc2_red1 frc2_red0 frc2_blue7 frc2_blue6 frc2_blue5 frc2_blue4 frc2_blue3 frc2_blue2 frc2_blue1 frc2_blue0

330R

330R 330R

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53

R70

R68 R69

4

frc2_irq sclk s_mosi /cs_frc2 s_miso /vid_reset

/frc2_lock

frc2_dreq

/frc2_sync /frc2_lreq

22RX4

fs2d38 fs2d39 fs2d40 fs2d41 fs2d42 fs2d43 fs2d44 fs2d45 fs2d46 fs2d47 fs2clk

fs2d0 fs2d1 fs2d2 fs2d3 fs2d4 fs2d5 fs2d6 fs2d7 fs2d8 fs2d9 fs2d10 fs2d11 fs2d12 fs2d13 fs2d14 fs2d15 fs2d16 fs2d17 fs2d18 fs2d19 fs2d20 fs2d21 fs2d22 fs2d23 fs2d24 fs2d25 fs2d26 fs2d27 fs2d28 fs2d29 fs2d30 fs2d31 fs2d32 fs2d33 fs2d34 fs2d35 fs2d36 fs2d37

4

22RX4

R73

R74

R75

TP45 TEST

1 3 5 7 1 3 5 7 1 3 5 7

1 3 5 7

1 3 5 7

fs2dqm1 /fs2we fs2qdm0 /fs2cas

2 4 6 8 2 4 6 8 2 4 6 8

TP49 TEST

TP48 TEST

R71

R72

frc2_red[0..7] frc2_green[0..7] frc2_blue[0..7]

sclk s_mosi /cs_frc2 s_miso /vid_reset

fs2_ref_clk

TP46 TEST

TP47 TEST

fs2a11 fs2a9 fs2a10 fs2a8 fs2a0 fs2a7 fs2a1 fs2a6 fs2a2 fs2a5 fs2a3 fs2a4

/fs2ras 2 fs2cke 4 /fs2cs 6 8 22RX4

2 4 6 8

fs2d[0..47]

/frc2_lock

frc2_dreq

/frc2_sync /frc2_lreq

fs2a[0..11]

3

3

gnd

R76 100R

100pF

C206

35 34 17 16 15 18 36 14

fs2clk fs2cke /fs2ras /fs2cas /fs2we /fs2cs fs2dqm1 fs2qdm0

35 34 17 16 15 18 36 14

fs2clk fs2cke /fs2ras /fs2cas /fs2we /fs2cs fs2dqm1 fs2qdm0

2

10nF

C202

VDD VDD VDDQ VDDQ VDDQ VDDQ

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

10nF

C209

VDD VDD VDDQ VDDQ VDDQ VDDQ

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

1 25 7 13 38 44

2 3 5 6 8 9 11 12 39 40 42 43 45 46 48 49

1 25 7 13 38 44

2 3 5 6 8 9 11 12 39 40 42 43 45 46 48 49

1 25 7 13 38 44

2 3 5 6 8 9 11 12 39 40 42 43 45 46 48 49

3v3

fs2d0 fs2d1 fs2d2 fs2d3 fs2d4 fs2d5 fs2d6 fs2d7 fs2d8 fs2d9 fs2d10 fs2d11 fs2d12 fs2d13 fs2d14 fs2d15

100nF

C210

3v3

fs2d32 fs2d33 fs2d34 fs2d35 fs2d36 fs2d37 fs2d38 fs2d39 fs2d40 fs2d41 fs2d42 fs2d43 fs2d44 fs2d45 fs2d46 fs2d47

100nF

C203

3v3

fs2d16 fs2d17 fs2d18 fs2d19 fs2d20 fs2d21 fs2d22 fs2d23 fs2d24 fs2d25 fs2d26 fs2d27 fs2d28 fs2d29 fs2d30 fs2d31

100nF

C197

Document Number FRC2.SCH Thursday, December 30, 1999

Size C Date:

PDE: Frame Rate Converter 2

100nF

10nF

Title

C208

VSS VSS VSSQ VSSQ VSSQ VSSQ

CLK CKE RAS CAS WE CS UDQM LDQM

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

C207

AMITEK

26 50 4 10 41 47

21 22 23 24 27 28 29 30 31 32 20 19

gnd

100nF

fs2a0 fs2a1 fs2a2 fs2a3 fs2a4 fs2a5 fs2a6 fs2a7 fs2a8 fs2a9 fs2a10 fs2a11

10nF

C196

IC19 KM416S1020BT-G/F10 Samsung

C201 10nF

VSS VSS VSSQ VSSQ VSSQ VSSQ

CLK CKE RAS CAS WE CS UDQM LDQM

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

C200

gnd

35 34 17 16 15 18 36 14

fs2clk fs2cke /fs2ras /fs2cas /fs2we /fs2cs fs2dqm1 fs2dqm0

26 50 4 10 41 47

21 22 23 24 27 28 29 30 31 32 20 19

fs2a0 fs2a1 fs2a2 fs2a3 fs2a4 fs2a5 fs2a6 fs2a7 fs2a8 fs2a9 fs2a10 fs2a11

100nF

VDD VDD VDDQ VDDQ VDDQ VDDQ

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

IC20 KM416S1020BT-G/F10 Samsung

C195

10nF

VSS VSS VSSQ VSSQ VSSQ VSSQ

CLK CKE RAS CAS WE CS UDQM LDQM

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

IC21 KM416S1020BT-G/F10 Samsung

C194

26 50 4 10 41 47

21 22 23 24 27 28 29 30 31 32 20 19

fs2a0 fs2a1 fs2a2 fs2a3 fs2a4 fs2a5 fs2a6 fs2a7 fs2a8 fs2a9 fs2a10 fs2a11

gnd

2

Sheet 1

10nF

C211

10nF

C204

10nF

C198

1

8

gnd

3v3

gnd

3v3

gnd

3v3

of

100nF

C212

100nF

C205

100nF

C199

11

Rev B

A

B

C

D

A

B

C

D

pc_b_in

pc_g_in

pc_r_in

22R 1W

1nF

100nF

gnda

47uF 16V

C117

L2 12uH

100nF

C122

gnda

TP34 TEST

gnda

TP33 TEST

gnda

100nF

R47

R46

R45

R44

220nF

C137

C136

Z1

gnd

5v

gnd

gnda

gnda

gnda

1nF

C112

47uF 16V

C120

100R

100R

100R

7

R38

R37

R36

LM385Z-2.5 NS

gnda

TP32 TEST

100pF

220R

620R

100pF

220R

C118

C270 150pF

gnda

12v_pc_a

R139 120R gnda

R138 47R

gnda

C268 150pF

gnda

C266 150pF

BAS16

D11

BAS16

D10

gnd

5v

R135 47R

R136 120R gnda

BAS16

D9

BAS16

620R

5v

7

1

C91 22nF C93 10nF

100nF

C96 22nF C98 10nF

100nF

100nF

C111

gnda

C90

C99

C97

C94

C92

C89

1nF

C114

C100

C95

100nF

C113

10uF 16V

C123

C84

1nF5

C86

C88

10nF

5v_pc_in

R35 2K2

100nF

C121

6

1nF

6

C116

5v_pc_a

gnda

5v_pc_in

gnda

5v_pc_in

gnda

5v_pc_in

10

12

11

IC12E 74F14

IC12F 74F14

gnd

100nF

C119

4

3

2

5v

IC12B 74F14

IC12A 74F14

C85 22nF C87 10nF

100nF

gnda

gnd

IC13 L78M05CDT SGS I O 3

10nF

10nF

10nF

10nF

10nF

10nF

C83

13

1

5v

14

7

D8

gnd

5v

R132 47R

R133 120R gnda

C110

8

R43

5v_pll

R137 27R

R134 27R

R131 27R

TP36 TEST

TP35 TEST

C109

L3 12uH

gnda

12v

C269 680pF

C267 680pF

C265 680pF

pc_vsync_in

pc_hsync_in

8

G

2

100nF

C115

gnda

C102 39nF

NC DEC2 VREF DEC1 NC RAGC RBOT RGAINC RCLPC RDEC VCCAR RIN AGNDR GAGC GBOT GGAINC GCLPC GDEC VCCAG GIN AGNDG BAGC BBOT BGAINC BCLPC BDEC VCCAB BIN AGNDB NC

5v_pc_in

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

5v_pll

100K C131

R41

C130

R42

pc_hs ync pc_vsync

C101 150pF

gnd

100nF

gnd

100nF

100K

9

5

pc_clamp

22R

Philips

IC11 TDA8752H/6

gnda

12v 5v 3v3 gnd

5

gnda

gnd

5v

R39

330R

12v

R40

330R

3v3

sda

scl

CKREFO VCCOR R7 R6 R5 R4 R3 R2 R1 R0 OGNDR VCCOG G7 G6 G5 G4 G3 G2 G1 G0 OGNDG VCCOB B7 B6 B5 B4 B3 B2 B1 NC

R49

FB5 BLM21A121S

8

IC12D 74F14

6

IC12C 74F14

5

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC VCCAPLL CZ CP AGNDPL VCCD CKREF COAST CKEXT INV HSYNC CLP PWOFF OEN DGND VCCOPLL CKADCO CKBO OGNDPL CKAO NC I2C3W ADD1 ADD2 TCK TDO DIS SEN SDA VDD VSS SCL NC NC ROR GOR BOR OGNDB B0 NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

100nF

C124

3v3

4

1nF

C128

pc_vsync

4

R48 10K

100nF

C126

/pc_oe

3v3

/pc_oe

3v3

gnd

gnd

1nF

C127

A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1

M4 M3 M2 M1

S8 S7 S6 S5 S4 S3 S2 S1

IC9

B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1

VCC VCC VCC VCC

GND GND GND GND GND GND GND GND

IC10

A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1

M4 M3 M2 M1

S8 S7 S6 S5 S4 S3 S2 S1

100nF

C125

25 24 22 21 19 18 16 15 14 13 11 10 8 7 5 4

48 37 20 9

51 45 40 34 23 17 12 6

25 24 22 21 19 18 16 15 14 13 11 10 8 7 5 4

48 37 20 9

51 45 40 34 23 17 12 6

3

1nF

C129

B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1

VCC VCC VCC VCC

GND GND GND GND GND GND GND GND

CY74UBL3911PAC Cypress

32 33 35 36 38 39 41 42 43 44 46 47 49 50 52 53

26 31 54 3

56 55 30 29 28 27 2 1

CY74UBL3911PAC Cypress

32 33 35 36 38 39 41 42 43 44 46 47 49 50 52 53

26 31 54 3

56 55 30 29 28 27 2 1

3

100nF

100nF

C103

1nF

C107

100nF

C105

100nF

100nF

gnd

C132

C133

dice2/pc_green3 dice2/pc_green2 dice2/pc_green1 dice2/pc_green0 dice2/pc_blue7 dice2/pc_blue6 dice2/pc_blue5 dice2/pc_blue4 dice2/pc_blue3 dice2/pc_blue2 dice2/pc_blue1 dice2/pc_blue0

3v3

gnd

3v3

C134

100nF

gnd

3v3

C135

dice2/pc_hs dice2/pc_red7 dice2/pc_red6 dice2/pc_red5 dice2/pc_red4 dice2/pc_red3 dice2/pc_red2 dice2/pc_red1 dice2/pc_red0 dice2/pc_green7 dice2/pc_green6 dice2/pc_green5 dice2/pc_green4

dice2/pc_vs dice2/pc_clk

3v3

gnd

TP29 TEST

TP31 TEST

TP28 TEST

TP27 TEST

1nF

2

C106

Document Number PC_ADC Thursday, December 30, 1999

Date:

PDE: PC ADC

5v_pc_d

Size C

Title

AMITEK

dice2/pc_blue[0..7]

dice2/pc_green[0..7]

dice2/pc_red[0..7]

TP30 TEST

2

sda

scl

Sheet 1

12uH

L1

dice2/pc_blue[0..7]

9

dice2/pc_green[0..7]

dice2/pc_red[0..7]

dice2/pc_hs

dice2/pc_vs dice2/pc_clk

/pc_oe

pc_clamp

pc_hs ync pc_vsync

pc_v_pol

pc_h_pol

1

gnd

5v

of

11

Rev B

A

B

C

D

A

B

C

D

gnd

3v3

8

100nF

10nF

8

dice1_dv dice1_hblank dice1_vblank dice1_cref dice1_clk

frc1_red[0..7]

frc1_blue[0..7]

5v 3v3 gnd

frc1_green[0..7]

/frc1_lock /frc1_lreq frc1_dreq /frc1_sync

dis_clk

dis_vs

dis_hs

dis_red[0..7] dis_blue[0..7]

dis_en

dis_green[0..7]

C234

C236

osd_ram_data0 osd_ram_data1 osd_ram_data2 osd_ram_data3 osd_ram_data4 osd_ram_data5 osd_ram_data6 osd_ram_data7 osd_ram_data8 osd_ram_data9 osd_ram_data10 osd_ram_data11 osd_ram_data12 osd_ram_data13 osd_ram_data14 osd_ram_data15

osd_ram_data[0..15]

gnd

5v

VDD VDD VDDQ VDDQ VDDQ VDDQ

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

VSS VSS VSSQ VSSQ VSSQ VSSQ

CLK CKE RAS CAS WE CS UDQM LDQM

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

gnd

3v3

3v3

NC

TP57 TEST

C239 100nF

R94 0R

C240 100nF

TP88 TEST

gnd

R92 100R

100pF

C241

TP59 TEST

100nF

C233

gnd

7

gnd

3v3

frc2_clk osd_ram_cke /osd_ram_ras /osd_ram_cas /osd_ram_we /osd_ram_cs osd_ram_dqm

35 34 17 16 15 18 36 14

26 50 4 10 41 47

osd_ram_addr0 osd_ram_addr1 osd_ram_addr2 osd_ram_addr3 osd_ram_addr4 osd_ram_addr5 osd_ram_addr6 osd_ram_addr7 osd_ram_addr8 osd_ram_addr9 osd_ram_addr10 osd_ram_addr11

21 22 23 24 27 28 29 30 31 32 20 19

TP58 TEST

10nF

C238

FB10 BLM21A121S

TP56 TEST

100nF

C235

KM416S1020BT-G/F10 Samsung

1 25 7 13 38 44

TP55 TEST

10nF

C237

3v3

2 3 5 6 8 9 11 12 39 40 42 43 45 46 48 49

IC23

7

C215

220nF

C214

220nF

frc1_green4 frc1_green3 frc1_green2 frc1_green1 frc1_green0

TP86 TEST

nstatus

frc1_green7 frc1_green6 frc1_green5

/frc1_lock /frc1_lreq frc1_dreq /frc1_sync

dis_red6 dis_blue6 dis_red7 dis_blue7

dis_red4 dis_blue4 dis_red5 dis_blue5

dis_red2 dis_blue2 dis_red3 dis_blue3

dis_red0 dis_blue0 dis_red1 dis_blue1

dis_green7 dis_vs

dis_green6 dis_hs

dis_green5

dis_green0 dis_green1 dis_green2 dis_green3 dis_green4 dis_en

osd_ram_data15 osd_ram_data14 osd_ram_data13 osd_ram_data12

conf_done

TCK CONF_DONE NCEO TDO VCCINT IO IO IO IO GNDINT CLKUSR/IO IO IO IO IO VCCINT IO IO IO IO IO GNDINT RDYNBSY/IO IO IO INIT_DONE/IO VCCINT IO IO IO IO GNDINT IO IO IO IO VCCINT IO IO IO IO GNDINT IO IO IO IO VCCINT IO IO IO IO GNDINT IO IO IO IO VCCINT TMS TRST NSTATUS

6

220nF

C217

frc1_blue7 frc1_blue6 frc1_blue5 frc1_blue4 frc1_blue3 frc1_blue2 frc1_blue1 frc1_blue0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

gnd

220nF

C216

3v3

osd_ram_data0 osd_ram_data1 osd_ram_data2 osd_ram_data3 osd_ram_data4 osd_ram_data5 osd_ram_data6 osd_ram_data7 osd_ram_data8 osd_ram_data9 osd_ram_data10 osd_ram_data11

6

osd_ram_addr0 osd_ram_addr1 osd_ram_addr2

osd_ram_addr[0..11]

5

TP83 TEST

osd_ram_addr3 osd_ram_addr4 osd_ram_addr5 osd_ram_addr6 osd_ram_addr7 osd_ram_addr8 osd_ram_addr9 osd_ram_addr10 osd_ram_addr11

4

240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 IC22 EPF10K30AQC240-3 Altera

NCS/IO CS/IO NWS/IO IO NRS/IO IO IO IO GNDINT IO IO IO IO IO IO IO VCCINT IO IO IO IO IO IO IO GNDINT IO IO DEV_OE/IO DED_IN DED_CLK DED_IN DEV_CLRN/IO IO IO IO VCCINT IO IO IO IO IO IO IO GNDINT IO IO IO IO IO IO DATA7/IO VCCINT DATA6/IO IO DATA5/IO DATA4/IO IO DATA3/IO DATA2/IO DATA1/IO

IO IO IO IO IO IO IO IO GNDINT IO IO IO IO IO IO IO VCCINT IO IO IO IO IO IO IO GNDINT IO IO IO VCCINT DED_IN DED_CLK DED_IN GNDINT IO IO VCCINT IO IO IO IO IO IO IO GNDINT IO IO IO IO IO IO IO VCCINT IO IO IO IO IO IO IO IO 220nF

C218

frc1_red7 frc1_red6 frc1_red5 frc1_red4 frc1_red3 frc1_red2 frc1_red1 frc1_red0

220nF

C219

220nF

C223

dice1_dv dice1_hblank dice1_vblank dice1_cref dice1_clk

5

220nF

C224

220nF

C225

220nF

C226

220nF

C227

220nF

C228

4

/cs_frc2 /cs_dice2 /cs_frc1 /cs_dice1 gen1_sclk gen1_sdata /clock_bypass

/pc_oe /dice2_oe

frc2_clk

3v3 4K7 4K7 4K7 4K7

R180 R179 R178 R177

dice2_dv dice2_hblank dice2_vblank dice2/pc_cref dice2/pc_hs dice2/pc_vs dice2/pc_clk

61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120

R86 R87 R88

gnd

3v3

180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121

frc2_green7 frc2_green6 frc2_green5 frc2_green4 frc2_green3 frc2_green2 frc2_green1 frc2_green0

DATA0 DCLK NCE TDI GNDINT IO IO IO IO IO VCCINT IO IO IO IO GNDINT IO IO IO IO VCCINT IO IO IO IO GNDINT IO IO IO IO VCCINT IO IO IO IO GNDINT IO IO IO IO VCCINT IO IO IO IO GNDINT IO IO IO IO VCCINT IO IO IO IO GNDINT MSEL0 MSEL1 VCCINT NCONFIG

330R 330R 330R

220nF

C222

3

3

gnd

220nF

C229

nconfig

frc2_blue6 frc2_blue7 gen2_sclk gen2_sdata

frc2_blue2 frc2_blue3 frc2_blue4 frc2_blue5

frc2_red6 frc2_red7 frc2_blue0 frc2_blue1

frc2_red2 frc2_red3 frc2_red4 frc2_red5

/frc2_lreq /frc2_sync frc2_red0 frc2_red1

/frc2_lock frc2_dreq

/pld_cs

cpu_data2 cpu_data1 cpu_data0 /cpu_ready

cpu_data6 cpu_data5 cpu_data4 cpu_data3

cpu_addr3 cpu_addr2 cpu_addr1 cpu_addr0 cpu_data7

pld_data dclk

cpu_addr4 cpu_addr5 cpu_addr6 cpu_addr7 cpu_addr8 cpu_addr9 cpu_addr10 cpu_addr11 cpu_addr12 cpu_addr13 cpu_addr14 cpu_addr15 cpu_addr16 cpu_addr17 cpu_addr18 /cs_dis dis_sclk /scs sclk s_mosi s_miso

220nF

C230

R93 100R

100pF

C242

220nF

C231

TP62 TEST

TP85 TEST

220nF

C232

2

TP63 TEST

/scs s_miso s_mosi sclk

pld_data

nstatus

nconfi g

conf_done

dclk

dclk pld_data nconfig

22R

22R

2

Date:

Size C

Title

AMITEK

0R 0R 0R 0R

TP87 TEST

scl sda sda_1 /debug_plug

R85 R84 R83 R82

1 2 3 5 6 7

R81 R80 R79 R78

R89 4K7

Thursday, December 30, 1999

Document Number PLD.SCH

PDE: PLD

R145

1K 1K 1K 1K

330R

330R

R144

R90

R91

scl sda

gnd

AMB01 AMITEK

P0 P1 P2 P3 P4 P5

IC24

4

8

Sheet 1

10

/cs_frc2 /cs_dice2 /cs_frc1 /cs_dice1 gen1_sclk gen1_sdata /clock_bypass

/pc_oe /dice2_oe

frc2_clk

dice2_dv dice2_hblank dice2_vblank dice2/pc_cref dice2/pc_hs dice2/pc_vs dice2/pc_clk

frc2_green[0..7]

gen2_sclk gen2_sdata

sda_1 /debug_plug

DEBUG

1 2 3 4 5 6 7 8 9 10 11 12 13 14

J7

5v

/frc2_lreq /frc2_sync frc2_red[0..7] frc2_blue[0..7]

/frc2_lock frc2_dreq

GND

VCC

bolt_power

scl sda

cpu_data[0..7] /cpu_ready /pld_cs

/cs_dis dis_sclk /scs sclk s_mosi s_miso

cpu_addr[0..18]

1

of

gnd

11

100nF

C275

Rev B

A

B

C

D

8

7

6

5

4

3

2

1

ANALOG 3v3 ir_out

ir_out

R146 12v

5v

txd rxd

3v3 sda scl

75R 12v C256

C1

C257

C2

C3

470uF 16V

100nF

470uF 16V

100nF

100nF

5v

3v3 12v 5v gnd gnda

D12 LTL-907PK

12v 5v 3v3 gnd

txd rxd

sda scl 12v 5v gnd gnda

D

D

ANA gnd

gnd

gnd

gnd

gnd CPU

MUX/GAMMA/OSD/HOST

/sdi_oe sdi_error pc_hsync pc_vsync pc_h_pol pc_v_pol /scs sclk s_mosi s_miso

J4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

C

txd rxd com_l com_16/9

12v

vid1_uv0 vid1_uv1 vid1_uv2 vid1_uv3 vid1_uv4 vid1_uv5 vid1_uv6 vid1_uv7

5v gnd

gen1_sclk gen1_sdata gen2_sclk gen2_sdata

pdp_hqen

dis_blue5 dis_red5

22RX4 1 3 5 7

R118 2 4 6 8

22RX4 1 3 5 7

R119 2 4 6 8

22RX4 1 3 5 7

R120 2 4 6 8

22RX4 1 3 5 7

R121 2 4 6 8

22RX4 1 3 5 7

R122 2 4 6 8

22RX4 1 3 5 7

R123 2 4 6 8

J1 1 35 2 36 3 37 4 38 5 39 6 40 7 41 8 42 9 43 10 44 11 45 12 46 13 47 14 48 15 49 16 50 17 51 18 52 19 53 20 54 21 55 22 56 23 57 24 58 25 59 26 60 27 61 28 62 29 63 30 64 31 65 32 66 33 67 34 68

power_good /cs_frc2 /cs_dice2 /cs_frc1 /cs_dice1

d_miso d_mosi d_sclk d_reset

dis_red4

dis_clk dis_hs dis_vs dis_en dis_red[0..7] dis_green[0..7] dis_blue[0..7]

/cs_frc2 /cs_dice2 /cs_frc1 /cs_dice1

/scs sclk s_mosi s_miso

5v gnd

dis_blue4

gen1_sclk gen1_sdata gen2_sclk gen2_sdata

dis_clk dis_hs dis_vs dis_en dis_red[0..7] dis_green[0..7] dis_blue[0..7]

dis_blue3 dis_red3

dis_blue2 dis_red2

/scs sclk s_mosi s_miso

dis_blue1 dis_red1

dis_blue0 dis_red0 dice1_dv dice1_hblank dice1_vblank dice1_cref dice1_clk

vid1_y0 vid1_y1 vid1_y2 vid1_y3 vid1_y4 vid1_y5 vid1_y6 vid1_y7 vid1_clk

dice1_dv dice1_hblank dice1_vblank dice1_cref dice1_clk

dis_vs dis_green7

dis_hs dis_green6

DICE 1 vid1_clk

vid1_hs vid1_vs vid1_href vid1_odd

FRAME RATE CONVERTER 1

vid1_clk

vid1_hs vid1_vs vid1_href vid1_odd vid1_y[0..7] vid1_uv[0..7]

vid1_hs vid1_vs vid1_href vid1_odd vid1_y[0..7] vid1_uv[0..7]

gnd

3v3 gnd

a_miso/ir a_mosi a_sclk/off a_reset

dice1_ref_clk dice1_clk dice1_hs dice1_vs dice1_dv dice1_hblank dice1_vblank dice1_red[0..7] dice1_green[0..7] dice1_blue[0..7] /cs_dice1 sclk s_mosi s_miso

J3 3v3 gnd

/vid_reset

dice1_ref_clk dice1_clk dice1_hs dice1_vs dice1_dv dice1_hblank dice1_vblank dice1_red[0..7] dice1_green[0..7] dice1_blue[0..7]

dis_en dis_green5

dice1_clk dice1_hs dice1_vs dice1_cref

frc1_ref_clk frc1_clk frc1_red[0..7] frc1_green[0..7] frc1_blue[0..7]

dice1_red[0..7] dice1_green[0..7] dice1_blue[0..7]

/frc1_lock /frc1_lreq frc1_dreq /frc1_sync

/cs_dice1 sclk s_mosi s_miso

/cs_frc1 sclk s_mosi s_miso

/vid_reset 5v 3v3 gnd

DICE1

scl sda sda_1

5v 3v3 gnd

frc1_ref_clk frc1_clk frc1_red[0..7] frc1_green[0..7] frc1_blue[0..7]

frc1_red[0..7] frc1_green[0..7] frc1_blue[0..7]

/frc1_lock /frc1_lreq frc1_dreq /frc1_sync

/frc1_lock /frc1_lreq frc1_dreq /frc1_sync

dis_clk

frc1_red[0..7] frc1_green[0..7] frc1_blue[0..7]

dis_green4

dis_green3

/frc1_lock /frc1_lreq frc1_dreq /frc1_sync

power_good dis_green2

/cs_frc1 sclk s_mosi s_miso

dis_green1

/vid_reset

/vid_reset

fs1_ref_clk

fs1_ref_clk

dis_green0 pdp_cnt

FRC1 pdp_hqen

ir_out com_l com_16/9

5v

C

CON_PDP gnd

vid2_uv0 vid2_uv1 vid2_uv2 vid2_uv3 vid2_uv4 vid2_uv5 vid2_uv6 vid2_uv7

R1 3K3 dice2_dv dice2_hblank dice2_vblank dice2/pc_cref dice2/pc_clk dice2/pc_hs dice2/pc_vs

vid2_y0 vid2_y1 vid2_y2 vid2_y3 vid2_y4 vid2_y5 vid2_y6 vid2_y7 vid2_clk

dice2_dv dice2_hblank dice2_vblank dice2/pc_cref dice2/pc_clk dice2/pc_hs dice2/pc_vs

R2 6K8

gnd

DICE 2 vid2_clk

vid2_hs vid2_vs vid2_href vid2_odd

FRAME RATE CONVERTER 2

vid2_clk

vid2_hs vid2_vs vid2_href vid2_odd vid2_y[0..7] vid2_uv[0..7]

CON40

vid2_hs vid2_vs vid2_href vid2_odd vid2_y[0..7] vid2_uv[0..7]

gnd

SDI

3v3 gnd vid2_clk vid2_y[0..7]

5v 3v3 gnd

5v 3v3 gnd

3v3 gnd

dice2_ref_clk dice2/pc_clk dice2/pc_hs dice2/pc_vs dice2_dv dice2_hblank dice2_vblank dice2/pc_red[0..7] dice2/pc_green[0..7] dice2/pc_blue[0..7] /dice2_oe /cs_dice2 sclk s_mosi s_miso /vid_reset

dice2_ref_clk dice2/pc_clk dice2/pc_hs dice2/pc_vs dice2_dv dice2_hblank dice2_vblank dice2/pc_red[0..7] dice2/pc_green[0..7] dice2/pc_blue[0..7] /dice2_oe /cs_dice2 sclk s_mosi s_miso

dice2/pc_clk dice2/pc_hs dice2/pc_vs dice2/pc_cref

frc2_ref_clk frc2_clk frc2_red[0..7] frc2_green[0..7] frc2_blue[0..7]

dice2/pc_red[0..7] dice2/pc_green[0..7] dice2/pc_blue[0..7]

/frc2_lock /frc2_lreq frc2_dreq /frc2_sync

pc_clamp pc_hsync

/cs_frc2 sclk s_mosi s_miso

/vid_reset 5v 3v3 gnd

DICE2

/sdi_oe

5v 3v3 gnd

/vid_reset fs2_ref_clk

frc2_clk frc2_red[0..7] frc2_green[0..7] frc2_blue[0..7]

frc2_clk frc2_red[0..7] frc2_green[0..7] frc2_blue[0..7]

/frc2_lock /frc2_lreq frc2_dreq /frc2_sync

/frc2_lock /frc2_lreq frc2_dreq /frc2_sync

frc2_clk frc2_red[0..7] frc2_green[0..7] frc2_blue[0..7]

B

/frc2_lock /frc2_lreq frc2_dreq /frc2_sync

/cs_frc2 sclk s_mosi s_miso

/cs_dis dis_sclk

/cs_dis dis_sclk

3v3

sdi_error FRC2

pc_hsync_in pc_vsync_in pc_r_in pc_g_in pc_b_in

pc_hsync_in pc_vsync_in pc_r_in pc_g_in pc_b_in

/dice2_oe /pc_oe

16

sda scl gnda

6 1 7 2 8 3 9 4 10 5

pc_g_in pc_b_in

11

gnd

12v 5v 3v3 gnd gnda

dice2/pc_clk dice2/pc_hs dice2/pc_vs dice2/pc_red[0..7] dice2/pc_green[0..7] dice2/pc_blue[0..7] /pc_oe pc_clamp

pc_hsync_in

14

pc_vsync_in

/clock_bypass

CON_DIS 5v 3v3 gnd

gnd

5v 3v3 gnd

PLD

pc_hsync pc_vsync pc_h_pol pc_v_pol

CLOCK dice1_ref_clk dice2_ref_clk

PC_ADC 13

/dice2_oe /pc_oe

/clock_bypass

12

dice1_ref_clk dice2_ref_clk

gen1_sclk gen1_sdata

gen1_sclk gen1_sdata

15

17

pc_r_in

sda scl 12v 5v 3v3 gnd gnda

J2

gnda

dice2/pc_clk dice2/pc_hs dice2/pc_vs dice2/pc_red[0..7] dice2/pc_green[0..7] dice2/pc_blue[0..7] /pc_oe pc_clamp

1 2 3 4 5 6 7 8 9 10 11 12

d_miso d_mosi d_sclk d_reset /cs_dis dis_sclk s_mosi sda scl

fs2_ref_clk

PC ADC

5v J10

/vid_reset

SDI

A

R117 2 4 6 8

dis_red6

sda_1 sda scl

/debug_plug

d_miso d_mosi d_sclk d_reset

22RX4 1 3 5 7

dis_blue6

CPU

CON40

B

dis_blue7 dis_red7

pld_data nconfig dclk

sda_1 sda scl

power_good

txd rxd com_l com_16/9

bolt_power /debug_plug

/vid_reset

pdp_hqen scl sda sda_1

/pld_cs /cpu_ready cpu_addr[0..18] cpu_data[0..7]

pld_data nconfig dclk

pld_data nconfig dclk /vid_reset

a_miso/ir a_mosi a_sclk/off a_reset

scl sda sda_1

3v3

/pld_cs /cpu_ready cpu_addr[0..18] cpu_data[0..7]

cpu_addr[0..18] cpu_data[0..7]

bolt_power

a_miso/ir a_mosi a_sclk/off a_reset

5v

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

/scs sclk s_mosi s_miso

/pld_cs /cpu_ready cpu_addr[0..18] cpu_data[0..7]

5v 3v3 gnd

DB15-PC-F

frc2_clk frc1_clk frc1_ref_clk /clock_bypass fs1_ref_clk fs2_ref_clk frc2_ref_clk

5v 3v3 gnd

gen2_sclk gen2_sdata

frc2_clk frc1_clk frc1_ref_clk /clock_bypass fs1_ref_clk fs2_ref_clk frc2_ref_clk A

gen2_sclk gen2_sdata

gnda CLOCK

BL1 110200C gnd gnd gnd gnd gnd

A B C D E

J I H G F

gnd gnd gnd gnd gnd

208080B SIGLE AMITEK

Title PDE top level

8

7

6

5

4

3

2

Size D

Document Number 208080B.SCH

Date:

Thursday, December 30, 1999

Rev B Sheet 1

11

of

1

8

7

6

5

4

3

2

1

D

D

L5 12uH

L6 12uH

VCC1

VCC2

VCC3

VCC4

5v

5v_sdi C285 10uF

C286 47uF 16V

gnd

C287 10uF

C288

C289

C290

C291

10nF

10nF

10nF

10nF

gnd_sdi

gnd_sdi TP91 TEST gnd_sdi

5v_sdi 10uF

sdi_error

5v_sdi C284

27

28

1

26 VSS

PD8

PD9

2 VSS

HSYNC

3

4 VSS

26 VCC4

23

SDI

SC0

22

8

SC1

PD4

22

9

SS1

PD3

21

10

SS0

PD2

20

11

SSC

PD1

19

R171 150R

C293 100nF

18

VDD

VCC3

C282

18

17

16

15

R165 10K

PD0

19

17

CD

R170 100R

16

VEE3

R169 100R

15

11

5v_sdi

14

20

RVCO3

SS0

OEM

F/2 EN RVCO2

SS1

10

RVCO1

SDI

21

13

9

12

C277

VDD

PD5

PCLK

SC1

SWC

7

SCE

23

VDD

SC0

47pF

75R

27

VCC2

R158

75R

28

24

7

75R

22nH

VEE4

25

PD6

8

R154

1

PD7

SD1

C276

R155

SSI

SD1

6

47pF

L4

2

5

24

R157

75R

A/D

3

25

SD0

12

BLIND

R156

SD0

75R

IC33 74LVC162244ADGG Philips

gnd

DDI

14

2

R168 100R

DDI

RVCO0

1

R167 100R

6

LOFILT

BL2

IC34 GS9000S

gnd_sdi

5

13

SDI input

AGC

4 VCC1

VEE1

IC35 GS9005A

gnd_sdi

SWF

C292 100nF

C283 100nF

C

R166 150R

1nF gnd_sdi C278 12pF

gnd_sdi R159 1K TP93 TEST

C279 12pF

gnd_sdi

TP95 TEST R161

C281 100nF

B

P1

4 10 15 21 28 34 39 45

GND GND GND GND GND GND GND GND

R163

R164

100R

100R

C294 10nF

C295 10nF

2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23

vid2_y7 vid2_y6 vid2_y5 vid2_y4 vid2_y3 vid2_y2 vid2_y1 vid2_y0 vid2_clk

1OE 2OE 3OE 4OE

1 48 25 24

/sdi_oe

VCC VCC VCC VCC

7 18 31 42

C

vid2_y[0..7]

vid2_clk

TP92 TEST

/sdi_oe

3v3

C299 100nF

R160 1K

1OUT1 1OUT2 1OUT3 1OUT4 2OUT1 2OUT2 2OUT3 2OUT4 3OUT1 3OUT2 3OUT3 3OUT4 4OUT1 4OUT2 4OUT3 4OUT4

3v3

R162 5K6

1K

1IN1 1IN2 1IN3 1IN4 2IN1 2IN2 2IN3 2IN4 3IN1 3IN2 3IN3 3IN4 4IN1 4IN2 4IN3 4IN4

gnd

5v_sdi

C280 10nF

R172 330K

47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26

B

D13 BAV70

5K

gnd

5v

TP94 TEST

Multitours

gnd

L7 12uH

C296 10uF

C297

C298

10nF

10nF

S5 gnd gnd_sdi gnd_sdi

5v

gnd

3v3

5v 3v3 gnd gnd

A

A

AMITEK Title PDE: SDI interface

8

7

6

5

4

3

2

Size C

Document Number SDI.SCH

Date:

Thursday, December 30, 1999

Rev B Sheet

11 1

of

11

8

7

6

5

4

3

2

1

WARNING: The pinout of this connector is the same than the FUJITSU panel. i.e. the pinout is different from the digital board display connector. Pins 1-34 are exchanged with pins 35-68.

D

D

dis_red[0..7] dis_green[0..7] dis_blue[0..7] dis_vs dis_hs dis_clk To NEC plasma display From digital board

C7 10nF

J1

C

B

J2

dis_red7

1 35 2 36 3 37 4 38 5 39 6 40 7 41 8 42 9 43 10 44 11 45 12 46 13 47 14 48 15 49 16 50 17 51 18 52 19 53 20 54 21 55 22 56 23 57 24 58 25 59 26 60 27 61 28 62 29 63 30 64 31 65 32 66 33 67 34 68

dis_red7

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

dis_blue7 gnd

5v

dis_red6

dis_red6

dis_red5

dis_blue6

C2

dis_red4

100nF

dis_red5

dis_red3

dis_blue5 dis_red2 gnd dis_red4

dis_red1

dis_blue4 dis_red0 5v

dis_red3

5v

dis_green7

dis_blue3 5v

dis_green6

5v IC2

R15

dis_red2

R5

1 2 3 4 5 6 7 8

dis_blue2 4K7

4K7

dis_red1

ms fulh fs

dis_blue1 dis_red0

R6

dis_blue0

A0 A1 A2 P0 P1 P2 P3 GND

R12

16 15 14 13 12 11 10 9

VCC SDA SCL INT P7 P6 P5 P4

330R 330R

R4 R3

R13

R14

R16

dis_green5 dis_green4

4K7

4K7

4K7

4K7

m2 m1 m0 400h

dis_green3 dis_green2 dis_green1

PCF8574T Philips

gnd 4K7

dis_green0

dis_green7

dis_blue7

dis_vs gnd

dis_blue6 dis_blue5

dis_green6 dis_hs

dis_blue4

5v dis_green5

dis_blue3 C1

5v

dis_blue2

5v

100nF

dis_green4 dis_clk

dis_blue1

R7

R8 dis_blue0 gnd

4K7

dis_green3

4K7

5v

dis_clk

IC1 d_reset dis_vs blkh

dis_green2

1 2 3 4 5 6 7 8 9 10

R17 dis_green1 4K7

dis_green0

psl ps0 ps1 ps2

gnd gnd

RESET PD0 PD1 XTAL2 XTAL1 PD2/INT0 PD3 PD4/T0 PD5 GND

VCC SCK/PB7 MISO/PB6 MOSI/PB5 PB4 PB3 PB2 AIN1/PB1 AIN0/PB0 PD6

20 19 18 17 16 15 14 13 12 11

dis_hs 330R 330R 330R psc3 psc2 psc1 psc0 pscl ps3

R9 R10 R11

d_sclk d_miso d_mosi

dis_vs psl m2 m1 m0 400h fs fulh

AT90S1200A-4SC Atmel ps3 ps2 ps1 ps0 ms psc3 psc2 psc1 psc0

CON_PDP gnd 5v 5v

pscl From digital board C3 100uF 16V

J3 1 2 3 4 5 6 7 8 9 10 11 12 CON_DIS JST

blkh

R18 /cs_dis dis_sclk s_mosi

4K7

330R 330R

R2 R1

gnd d_miso d_mosi d_sclk d_reset /cs_dis dis_sclk s_mosi sda scl

C

B

CON_NEC gnd

A

gnd

A

A

AMITEK

Tél 01 64 73 95 70 Fax 01 64 73 95 58 e_mail :[email protected]

21, Rue Galilée 77420 CHAMPS SUR MARNE Title

INTERFACE_NEC

8

7

6

5

4

3

Size C

Document Number

Date:

Thursday, December 30, 1999

2

Rev

208140 Sheet

B 1

of

1

2

D

5

70V

1 3 5 7 9 11 13 15 17 19 21

180V J11 2 4 6 8 10 12 14 16 18 20 22

g

HIROSE

g

JST B9P-VH

g

g

g

g

5V

J13

g

g

JST B9P-VH

g

g

A

4

180V

70V

g g

g

g

J15

20 18 16 14 12 10 8 6 4 2

180V J12 19 17 15 13 11 9 7 5 3 1 HIROSE

JST B10P-VH

g

g

g g

g

J7 Stocko MKS 1651-6-0-202

JST B10P-VH

g

1 2

4

J9 Stocko MKS 1651-6-0-202

J5

1 2 3 4 5 6 7 8 9 10

g

g

J14

gnd

1 2 3 4 5 6 7 8 9 10

1 2

1

C

J8 gnd

1

R19 12V 10R 1 W

1

1 2 Stocko MKS 1651-6-0-202

gnd

208140B UNIVERSAL

1

B

A

5

1 2 3 4 5 6 7 8 9 1

1 2 3 4 5 6 7 8 9

3

C5 100nF 50V NC

3

g

R25 47K NC

g

C4 10uF 250V NC

R28 27K

5V1

D2 BZV85C NC R27 47K NC

R30 27K

g

12V

R26 100K NC

g

D4 1N4007

R24 10K T2 BC847B

D3 BAS16 NC

2

g

AMITEK

2

g

D1 1N4007

C6 220uF 16V

g

R21 68R 5W

R29 33K

Thursday, December 30, 1999

Document Number

CONNECTIQUE

21, Rue Galilée 77420 CHAMPS SUR MARNE Title Size A4 Date:

g

R20 68R 5W Strapée

R22 68R 5W Strapée

R23 68R 5W

T1 BUZ76A

208140

Sheet

1

1

of

2

B

Rev

Tél 01 64 73 95 70 Fax 01 64 73 95 58 e_mail :[email protected]

2

D

C

B

A