PCI_GEN02 Card 14, rue Soleillet - 75 971 PARIS Cedex 20 E-mail: [email protected]

Tel: Fax:

March 1998

+33 (0) 1 40 33 79 98 +33 (0) 1 43 58 14 15

User’s Guide

Table of contents 1. OVERVIEW

2

2. USER APPLICATION DESIGN

2

3. PCI_GEN02 CARD TESTING

4

3.1 PCI_GEN02 CONFIGURATION 3.2 TESTING FUNCTIONALITIES

4 5

4. MECHANICAL DESCRIPTION

7

5. INTERFACE DESCRIPTION

8

5.1 QFP240 AND QFP208 DEVICE PIN-OUT 5.2 J3, J5 AND J6 I/O CONNECTOR PIN-OUT 5.3 BIT/BYTE BLASTER CONNECTOR 5.4 EXTERNAL POWER SUPPLY CONNECTOR 5.5 REAR PANEL CONNECTOR

© PLD Applications, 1997-1998

8 12 13 13 13

Product File Reference: PCI_GEN02 V1 Default PCI interface device: Reference % IO % Lcell EPF10K10QC208-3 50/134 56 % Design files: GDF: Graphic Design File TDF: Text Design File ACF: Assignment & Configuration File SCF: Simulator Channel Files DOS device drivers Development tool: Altera Max+PlusII Support : PLD Applications provides technical support for the integration of user applications on the PCI_GEN02 card. PLD Applications guarantees the product performances before integration and provides examples of back-end applications to illustrate the design of 100% PCI compliant projects.

Ref: ugPCI21a

PCI_GEN02 Card User’s Guide

1.

OVERVIEW

The PCI_GEN02 card is a 5-volt PCI-based evaluation board. The PCI_GEN02 card and the associated PCI Target or Master/Target megafunction are suitable for rapid prototyping of any PCIbased application. • The PCI Target megafunction is fully described in its associated user's guide, referenced: ugTARxxa • The PCI Master/Target megafunction is fully described in its associated user's guide, referenced: ugMTAxxa The PCI target or master/target megafunction provided with the PCI_GEN02 card is a noncustomizable, encrypted version (ConstCore). The designer cannot access the PCI Core parameters. If any parameter needs to be modified to validate the prototype, PLD Applications will send a new version with the required settings. To allow infinite re-utilization of its megafunctions (in any design), PLD Applications delivers a licensed version. This license (linked to a singled operating site) allows its owner to use the PCI megafunctions with no constraints.

PCI_GEN02 card features: • • • • •

Compliance with the PCI electrical specification and EMC constraints, Wide interface device choice: 2 possible device implantation, QFP208 and QFP240, Free I/O pins access through three 50-pin connector prints, Two workspaces to implement custom applications, PCI interface device programming using: ⇒ a serial PROM (EPC1/EPC1441) mounted on socket, ⇒ or the dedicated BitBlaster/ByteBlaster connector, • External power supply connector to allow stand-alone utilization.

Fig 1.1 - PCI_GEN02 card schematic

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PCI_GEN02 Card User’s Guide

2.

USER APPLICATION DESIGN

The user application is divided into: • The internal user application • The external user application

Fig 2.1 - Internal & External user application

The internal user application is implemented in the same device that hosts the PCI interface. This application communicates with the PCI core through a "generic interface". This interface allows a easy access to the application resources. The PCI core handles all the PCI protocol (parity, configuration space accesses...). The size of the internal user application is limited by the PCI interface device available resources. Table 2.1. shows the available resources for different type of devices: PCI master/target core

EPF Device 10K20RC2XX-3 10K30RC2XX-3 10K40RC2XX-3

PCI master/target core + internal SRAM support

I/O used

EABs used

LCELL used

% used

N/A N/A N/A

0/6 0/6 0/8

812 807 807

67 46 34

I/O used

EABs used

LCELL used

% used

N/A N/A N/A N/A

0/3 0/6 0/6 0/8

337 337 338 338

56 29 19 14

10K20RC2XX-3 10K30RC2XX-3 10K40RC2XX-3

PCI target core

EPF Device 10K10QC2XX-3 10K20RC2XX-3 10K30RC2XX-3 10K40RC2XX-3

EPF Device

I/O used

EABs used

LCELL used

% used

103/147 103/147 103/147

4/6 4/6 4/8

982 980 980

82 56 41

PCI target core + internal SRAM support

EPF Device 10K10QC2XX-3 10K20RC2XX-3 10K30RC2XX-3 10K40RC2XX-3

I/O used

EABs used

LCELL used

% used

98/134 98/147 98/147 98/147

3/3 4/6 4/6 4/8

439 445 449 449

76 42 25 19

Tab 2.1. - Available resources

The external user application can be implemented on two workspaces (as shown on fig 1.1). J3, J5 and J6 are three 50-pin connector prints that allow connection between the internal and external user applications. The connectors pin-out is detailed in section 5.2.

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PCI_GEN02 Card User’s Guide

3.

PCI_GEN02 CARD TESTING

PLD Applications provides a test application that allows designers to verify the PCI_GEN02 card functionality in a PCI-based PC system. This test application includes two parts: • A DOS C++ application "GOPCE.gxe": This application, described in section 4, provides an access to the following resources: ⇒ Configuration space of every PCI agent in the system, ⇒ PCI_GEN02 card memory space • An example of internal back-end application: This application is used to test memory accesses on the PCI_GEN02 card without any hardware adjunction. This application uses the FLEX10K EABs (Embedded Array Blocks) to implement an internal memory buffer.

3.1

PCI_GEN02 CONFIGURATION

There are two ways for configuring a PCI_GEN02 card: • EPC1 or EPC1441 PROM configuration, • BitBlaster or ByteBlaster configuration.

3.1.1 PROM-based configuration The EPC1 or EPC1441 are the only PROM suitable for configuring FLEX10K devices1. These PROM can be programmed with ALTERA programming hardware or with a standard programmer2. The PnP (Plug and Play) initialization process is started several seconds after system power-up. The FLEX10K device is already in user mode3, ready to respond to configuration accesses initiated by the host system.

3.1.2 BitBlaster/ByteBlaster-based configuration The PCI interface device can also be configured from a BitBlaster or ByteBlaster. In this case, the user must follow these steps: • • • • •

Install the card in the system (power down), Power-up the system, Install the BitBlaster or ByteBlaster respectively on a serial or parallel port. Execute MAXPLUSII, Open MAX+PLUSII Programmer window, initialized with x_10Kxxx.sof serial output file.

After these steps, the FLEX10K device is in user mode. However, its configuration space must be initialized by the system’s PnP sequence. Therefore, when programming is done, the user must exit Max+PlusII and hardware RESET the computer to force a new hardware detection.

1

These PROM include an internal oscillator to clock the configuration data. DataIO 3900, software version 5.3 min. 3 Configuration time takes about 100ms for the FLEX10K100 device. 2

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PCI_GEN02 Card User’s Guide

3.2

TESTING FUNCTIONALITIES

The "GOPCE.gxe" DOS application is a software interface that provides an access to the PCI system resources. The application C++ source code is available and provided with every PCI_GEN02 card. The main functions of this application are: • PCI_GEN02 detection, • PCI_GEN02 configuration space check, • PCI agents configuration space display, • PCI_GEN02 memory space display , • PCI_GEN02 memory space initialization (read and write), • PCI_GEN02 Interrupt management. The PCI_GEN02 configuration space registers are mapped to internal PCI core registers. The application can't modify any configuration register. • WARNING #1: The FLEX10K10 device can only provide a 24 bits x 256 buffer because it contains only three EABs. To implement a larger buffer, the designer must use a larger device or an external buffer. • WARNING #2: EMM386.exe (PC config.sys file) must be disabled (AUTO mode) to prevent protected mode conflicts.

3.2.1 PCI_GEN02 card detection The GOPCE.gxe application performs the following tests: • PCI BIOS detection, • If PCI BIOS detected, - PCI_GEN02 card(s) detection, • for each card detected - Configuration space check and validation, - Display, - Memory space check and validation, - Display.

NOTE: Resource allocation mechanism. During the boot/PnP process, the system scans the PCI bus to identify every agent's needs (I/O space, memory space, interrupts,...). The system then allocates the resources making sure there are no conflicts. Now on the detailed memory base address allocation: first, the system writes FFFFFFFFh into the device's Base Address Register. It immediately reads back this register. The value returned indicates the size of the memory space requested by the device, as some bits of this register are hardwired to GND. To give an example, if the read value is FFFFF0000h, it means that the 12 LSBs are hardwired to GND. The system then writes the allocated address. Continuing the example, the allocated address (under 1 MB) could be 000C8000h (see section 6.2.5.1 of the PCI specification). The software driver should use PCI BIOS INTerrupt 1Ah to retrieve information from the device's configuration space (under DOS).

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PCI_GEN02 Card User’s Guide

3.2.2 Configuration space display From the main menu, the "F1: PCI CONFIG " key displays the detailed configuration space header for each PCI agent found on the bus. This option menu uses the PCI BIOS functions to access the configuration data. The "n" key displays the following PCI agent's configuration space. The "m" key displays the detailed status and command register for the current PCI agent.

3.2.3 Memory space display From the main menu, the "F2: PCI_GEN02" key displays the PCI_GEN02 memory space content. This option menu uses a C++ function to access memory data. It then displays the memory content. Each page displays 64 DWORDS (32 bits). The "p" and "m" keys respectively increment and decrement the page number. The "a", "b" and "c" keys allow the user to write patterns in the entire memory area.

• "a" fills the PCI_GEN02 memory space with zeroes • "b" fills the PCI_GEN02 memory space with a ramp: 0,1,2,...FFh. • "c" fills the PCI_GEN02 memory space with a user-defined pattern: Pattern, ~Pattern4, Pattern...

4

~Pattern = NOT(Pattern).

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PCI_GEN02 Card User’s Guide

4.

5

MECHANICAL DESCRIPTION5

Measurements are in millimeters.

7

PCI_GEN02 Card User’s Guide

5.

INTERFACE DESCRIPTION

5.1

QFP240 AND QFP208 PROGRAMMABLE DEVICE PIN-OUT QFP 240

Type

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

NC CONF_DONE nCE0 NC VCC IO IO IO IO GND IO IO IO IO IO VCC IO IO IO IO IO GND IO IO IO IO VCC IO IO IO IO GND IO IO IO IO VCC IO IO IO IO GND IO IO IO IO VCC IO IO IO IO GND IO IO IO IO VCC NC NC nSTATUS

Signal NC CONF_DONE nCE0 NC VCC NC NC NC NC GND NC NC NC AD_pci19 AD_pci18 VCC AD_pci17 AD_pci16 NC CBE_pci2 NC GND NC NC NC NC VCC TRDY_pci DEVSEL_pci STOP_pci LOCK_pci GND PERR_pci SERR_pci PAR_pci NC VCC NC NC NC NC GND CBE_pci1 AD_pci15 AD_pci14 NC VCC AD_pci13 AD_pci12 AD_pci11 AD_pci10 GND NC NC NC NC VCC NC NC nSTATUS

QFP 208

Type

Signal

I/O Connector J3 - 8 J3 - 3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

NC CONF_DONE nCE0 NC VCC VCC NC NC NC IO IO IO IO NC NC IO IO IO IO GND GND VCC VCC IO IO IO IO IO IO IO IO GND GND VCC VCC NC NC IO IO IO IO VCC VCC IO IO IO IO GND GND NC NC nSTATUS

NC CONF_DONE nCE0 NC VCC VCC NC NC NC AD_pci19 AD_pci18 AD_pci17 AD_pci16 NC NC CBE_pci2 NC NC NC GND GND VCC VCC TRDY_pci DEVSEL_pci STOP_pci LOCK_pci NC PERR_pci SERR_pci PAR_pci GND GND VCC VCC NC NC NC CBE_pci1 AD_pci15 AD_pci14 VCC VCC AD_pci13 AD_pci12 AD_pci11 AD_pci10 GND GND NC NC nSTATUS

J3 - 8 J3 - 3

J3 - 7

J3 - 7

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PCI_GEN02 Card User’s Guide

QFP 240 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120

Type IO IO IO IO IO IO IO IO GND IO IO IO IO IO IO IO VCC IO IO IO IO IO IO IO GND IO IO IO VCC DI1 CLK1 DI2 GND IO IO VCC IO IO IO IO IO IO IO GND IO IO IO IO IO IO IO VCC IO IO IO IO IO IO IO IO

Signal bIO0 bIO1 bIO2 bIO3 AD_pci9 AD_pci8 CBE_pci0 AD_pci7 GND AD_pci6 bIO4 AD_pci5 AD_pci4 AD_pci3 AD_pci2 AD_pci1 VCC bIO5 AD_pci0 bIO6 bIO7 bIO8 bIO9 bIO10 GND bIO11 bIO12 bIO13 VCC IRDY_PCI bIO15 bIO16 GND bIO17 bIO18 VCC bIO19 bIO20 bIO21 bIO22 bIO23 bIO24 bIO25 GND bIO26 bIO27 bIO28 bIO29 bIO30 bIO31 bIO32 VCC bIO33 bIO34 bIO35 bIO36 bIO37 bIO38 bIO39 bIO40

QFP 208

Type

Signal

I/O Connector J6 - 48 J6 - 47 J6 - 46 J6 - 45

53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104

IO IO IO IO IO IO GND IO IO IO IO IO IO VCC IO IO IO IO IO GND IO IO IO VCC VCC DI1 CLK1 DI2 GND GND IO VCC IO IO IO IO IO IO GND IO IO IO IO IO IO VCC IO IO IO IO IO IO

9

AD_pci9 AD_pci8 CBE_pci0 AD_pci7 NC AD_pci6 GND AD_pci5 AD_pci4 AD_pci3 AD_pci2 AD_pci1 NC VCC AD_pci0 bIO6 bIO7 bIO8 bIO9 GND NC bIO11 bIO12 VCC VCC IRDY_PCI bIO15 bIO16 GND GND bIO18 VCC bIO19 bIO20 bIO21 bIO22 bIO23 bIO24 GND NC bIO26 bIO27 bIO28 bIO29 bIO30 VCC bIO32 NC bIO33 bIO34 bIO35 bIO36

J6-44

J6-43 J6 - 42 J6 - 41 J6 - 40 J6 - 39 J6 - 36 J6 - 35 J6 - 34 J6 - 33 J6 - 32 J6 - 31 J6 - 30 J6 - 29 J6 - 28 J6 - 27 J6 - 24 J6 - 23 J6 - 22 J6 - 21 J6 - 20 J6 - 19 j6 - 18 J6 - 17 J6 - 16 J6 - 15 J6 - 12 J6 - 11 J6 - 10 J6 - 9 J6 - 8 J6 - 7 J6 - 6 J6 - 5 J6 - 4 J6 - 3 J3 - 48

PCI_GEN02 Card User’s Guide

QFP 240 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180

Type nCONFIG VCC MSEL1 MSEL0 GND IO IO IO IO VCC IO IO IO IO GND IO IO IO IO VCC IO IO IO IO GND IO IO IO IO VCC IO IO IO IO GND IO IO IO IO VCC IO IO IO IO GND IO IO IO IO VCC IO IO IO IO IO GND NC nCE DCLK DATA0

Signal nCONFIG VCC GND GND GND bIO41 bIO42 bIO43 bIO44 VCC bIO45 bIO46 bIO47 bIO48 GND bIO49 bIO50 bIO51 bIO52 VCC bIO53 bIO54 bIO55 bIO56 GND bIO57 bIO58 bIO59 bIO60 VCC bIO61 bIO62 bIO63 bIO64 GND bIO65 bIO66 bIO67 bIO68 VCC bIO69 bIO70 bIO71 bIO72 GND bIO73 bIO74 bIO75 bIO76 VCC bIO77 bIO78 bIO79 bIO80 bIO81 GND NC GND DCLK DATA0

QFP 208

Type

Signal

I/O Connector J3 - 4

105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156

nCONFIG VCC MSEL1 MSEL0 VCC VCC IO IO NC NC IO IO VCC VCC IO IO IO IO GND GND NC NC IO IO GND GND IO IO IO IO IO IO VCC VCC NC NC IO IO IO IO VCC VCC IO IO IO IO GND GND NC nCE DCLK DATA0

nCONFIG VCC GND GND VCC VCC bIO45 bIO46 NC NC NC bIO49 VCC VCC bIO52 NC bIO53 bIO54 GND GND NC NC bIO58 bIO59 GND GND bIO61 bIO62 bIO63 bIO64 NC bIO65 VCC VCC NC NC bIO69 bIO70 bIO71 bIO72 VCC VCC bIO74 bIO75 bIO76 NC GND GND NC GND DCLK DATA0

J3 - 4 J3 - 47 J3 - 46 J3 - 45 J3 - 44 J3 - 43 J3 - 42 J3 - 41 J3 - 40 J3 - 39 J3 - 36 J3 - 35 J3 - 34 J3 - 33 J3 - 32 J3 - 31 J3 - 30 J3 - 29 J3 - 28 J3 - 27 J3 - 24 J3 - 23 J3 - 22 J3 - 21 J3 - 20 J3 - 19 J3 - 18 J3 - 17 J3 - 16 J3 - 15 J3 - 12 J3 - 11 J3 - 10 J3 - 9 J5 - 48 J5 - 47 J5 - 46 J5 - 45 J5 - 44 J5 - 43 J5 - 42 J5 - 41 J3 - 5

J3 - 6 J3 - 5

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PCI_GEN02 Card User’s Guide

QFP 240 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 240

Type IO IO IO IO IO IO IO IO VCC IO IO IO IO IO IO IO GND IO IO IO IO IO IO IO VCC IO IO IO IO DI3 CLK2 DI4 IO IO IO GND IO IO IO IO IO IO IO VCC IO IO IO IO IO IO IO GND IO IO IO IO IO IO IO IO

Signal bIO82 bIO83 bIO84 bIO85 bIO86 bIO87 bIO88 bIO89 VCC bIO90 bIO91 bIO92 bIO93 bIO94 bIO95 bIO96 GND bIO97 bIO98 bIO99 bIO100 bIO101 bIO102 bIO103 VCC bIO104 INTA_pci bIO105 bIO106 RST CLK Frame_PCI bIO108 bIO109 bIO110 GND GNT_pci REQ_pci AD_pci31 AD_pci30 AD_pci29 bIO111 AD_pci28 VCC AD_pci27 AD_pci26 AD_pci25 AD_pci24 bIO112 CBE_pci3 IDSEL_pci GND AD_pci23 AD_pci22 AD_pci21 AD_pci20 bIO113 NC NC NC

240

240

QFP 208

157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208

Type

IO IO IO IO IO IO IO IO VCC IO IO IO IO IO GND IO IO IO IO IO IO VCC IO IO VCC DI3 CLK2 DI4 GND IO IO GND IO IO IO IO IO VCC IO IO IO IO IO IO GND IO IO IO IO IO IO IO

Signal

bIO86 bIO87 bIO88 bIO89 NC bIO90 bIO91 bIO92 VCC bIO94 bIO95 bIO96 NC bIO97 GND bIO99 bIO100 bIO101 bIO102 bIO103 NC VCC INTA_pci bIO105 VCC RST CLK Frame_PCI GND bIO109 bIO110 GND GNT_pci REQ_pci AD_pci31 AD_pci30 AD_pci29 VCC AD_pci28 NC AD_pci27 AD_pci26 AD_pci25 AD_pci24 GND CBE_pci3 IDSEL_pci NC AD_pci23 AD_pci22 AD_pci21 AD_pci20

I/O Connector J5 - 40 J5 - 39 J5 - 36 J5 - 35 J5 - 34 J5 - 33 J5 - 32 J5 - 31 J5 - 30 J5 -29 J5 - 28 J5 - 27 J5 - 24 J5 - 23 J5 - 22 J5 - 21 J5 - 20 J5 - 19 J5 - 18 J5 - 17 J5 - 16 J5 - 15 J5 - 12 J5 - 11 J5 - 10

J5 - 9 J5 - 8 J5 - 7 J5 - 6

J5 - 5

J5 - 4

J5 - 3

208

208

11

208

120

PCI_GEN02 Card User’s Guide

5.2

J3, J5 AND J6 I/O CONNECTOR PIN-OUT Pin #

J5

1 2 3 4 5 6 7 8 9

GND GND bio113 bio112 bio111 bio110 bio109 bio108 bio1076

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

J3

J6

GND GND

GND GND

nCE0 nCONFIG DATA0 DCLK nSTATUS CONF_DONE bio73

bio39 bio38 bio37 bio36 bio35 bio34 bio33

bio106 bio105 bio104 VCC VCC bio103 bio102 bio101 bio100 bio99 bio98 bio97 bio96 bio95 bio94 GND GND bio93 bio92 bio91 bio90

bio72 bio71 bio70

bio32 bio31 bio30

bio59 bio58 bio57 bio56

bio19 bio18 bio17 bio167

31 32

bio89 bio88

bio55 bio54

bio15

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

bio87 bio86 bio85 bio84

bio53 bio52 bio51 bio50

VCC VCC bio69 bio68 bio67 bio66 bio65 bio64 bio63 bio62 bio61 bio60

VCC VCC bio83 bio82 bio81 bio80 bio79 bio78 bio77 bio76 bio75 bio74

VCC VCC

GND GND

to

Soldered connectors are useful for the installation of a daughterboard.

bio29 bio28 bio27 bio26 bio25 bio24 bio23 bio22 bio21 bio20

bio49 bio48 bio47 bio46 bio45 bio44 bio43 bio42 bio41 bio40 GND GND

Wrapped connectors are useful interface with the two workspaces.

VCC VCC

GND GND

The three connectors I/O prints allow installation of soldered or wrapped connectors.

The connector labeled J5 contains the six dedicated signals (bold-italic) used to configure the FLEX10K device. With those six dedicated signals, the designer can use the “configuration chaining feature” available with FLEX10K devices and thus, program several devices from the same PROM or BitBlaster/ByteBlaster.

GND GND

bio148 bio13 bio12 bio11 bio10 VCC VCC bio9 bio8 bio7 bio6 bio5 bio4 bio3 bio2 bio1 bio0 GND GND

6

Each connector contains 4 pins connected to the 5V plane (to provide power to a daughterboard), and 6 pins connected to the GND plane.

A QFP 240 package allows access to 112 I/Os via J3, J5 and J6. A QFP 208 package allows access to 64 I/Os via J3, J5 et J6. T HE

SHADED REGIONS REPRESENT PINS

THAT ARE NOT AVAILABLE ON THE

208-PINS

PACKAGES.

T HE

HATCHED REGIONS REPRESENT PINS

THAT ARE NOT AVAILABLE REGARDLESS OF THE TYPE OF PACKAGE.

Warning! I/O bIO107, connected to a FLEX10K dedicated input, is used by a PCI signal. This I/O is not available to the designer. 7 Warning! The designer must install the ST1 jumper in order tu use J6 pin 30. This pin is not available on a PCI_GEN02 configured to operate as a PCI master device. 8 Warning! I/O bIO14, connected to a FLEX10K dedicated input, is used by a PCI signal. This I/O is not available to the designer.

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PCI_GEN02 Card User’s Guide

5.3

BIT/BYTE BLASTER CONNECTOR Pin # 1 2 3 4 5 6 7 8 9 10

5.4

Name DCLK GND CONF_DONE VCC nCONFIG NC nSTATUS NC DATA0 GND

Description Serial configuration clock GND plane Configuration done 5 Volts plane Configuration Reset & Start Not connected Configuration error Not connected Serial configuration data GND plane

The J1 HE10-type connector is dedicated to the FLEX10K device configuration. The BitBlaster or ByteBlaster can be used to configure the FLEX10K device. When using this configuration interface, the PROM socket (IC1) must be empty. The PCI_GEN02 card needs to be powered to support FLEX10K configuration.

EXTERNAL POWER SUPPLY CONNECTOR Pin # 1 2

3 4 5 6

Name GND POS

VCC GND GND NEG

Description GND plane External power supply connected to the POS1 and POS2 rails. 5 Volts plane GND plane GND plane External power supply connected to the NEG1 and NEG2 rails.

The J2 external connector provides power supply to: • the 5 volts plane, from an external source, • the (NEG1, NEG2) and (POS1, POS2) rails from two external sources.

The designer may install the following components using three SMC prints in correspondence with each external power supply entry point: • 1 ceramic capacitance 100nF • 1 tantalum capacitance 33µF • 1 tranzil diode

5.5

Tantalum C9 C3 C5

VCC POS NEG

Ceramic C10 C4 C6

Diode D3 D1 D2

REAR PANEL CONNECTOR

The PCI_GEN02 card provides a 50-pin J4 print that can be used to install a 50-pin rear panel connector. If not installed, this 50-pin print extends workspace area #2.

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