OV511+ Advanced Camera to USB Bridge OmniVision Technologies, Inc. May 13, 2000

Data Sheet Rev. 1.2

OmniVision Technologies, Inc. reserves the right to make changes without further notice to any product herein to improve reliability, function or design. OmniVision does not assume any liability arising out of the application or use of any project, circuit described herein; neither does it convey any license under its patent nor the right of others.

This document contains information of a proprietary nature. None of this information shall be divulged to persons other than OmniVision Technologies, Inc. employee authorized by the nature of their duties to receive such information, or individuals or organizations authorized by OmniVision Technologies, Inc.

Content 1 2

3

4 5

6

7 8

Features...........................................................................................................................................4 Architecture.....................................................................................................................................5 2.1 General Description .................................................................................................................5 2.2 Functional Description.............................................................................................................6 2.2.1 Camera Interface ..............................................................................................................6 2.2.2 DRAM Interface...............................................................................................................7 2.2.3 OmniCE...........................................................................................................................8 2.2.4 ISO FIFO .........................................................................................................................9 2.2.5 UDC interface ................................................................................................................10 2.2.6 System Control...............................................................................................................10 2.2.7 USB Device Controller ...................................................................................................11 2.2.8 SCCB (Serial Camera Control Bus)................................................................................11 2.2.9 PIO ................................................................................................................................11 2.2.10 Custom ID......................................................................................................................13 Pin Definition................................................................................................................................14 3.1 Pin Assignments ....................................................................................................................14 3.2 Pin Descriptions.....................................................................................................................15 Electrical Characteristics ...............................................................................................................17 Register Table (Vendor Commands) ..............................................................................................18 5.1 CAMERA INTERFACE ........................................................................................................18 5.2 DRAM INTERFACE.............................................................................................................19 5.3 ISO FIFO...............................................................................................................................19 5.4 PIO ........................................................................................................................................20 5.5 SCCB ....................................................................................................................................20 5.6 SYSTEM CONTROL ............................................................................................................22 5.7 OmniCE ................................................................................................................................23 USB Descriptors ............................................................................................................................24 6.1 Device....................................................................................................................................24 6.2 Configuration.........................................................................................................................24 6.3 Interface & Endpoint .............................................................................................................24 6.3.1 Alternate 0 .....................................................................................................................25 6.3.2 Alternate 1 .....................................................................................................................25 6.3.3 Alternate 2 .....................................................................................................................25 6.3.4 Alternate 3 .....................................................................................................................26 6.3.5 Alternate 4 .....................................................................................................................26 6.3.6 Alternate 5 .....................................................................................................................27 6.3.7 Alternate 6 .....................................................................................................................27 6.3.8 Alternate 7 .....................................................................................................................27 Software Package...........................................................................................................................29 Mechanical Information ................................................................................................................30

1

Illustrations FIGURE 1. FIGURE 2. FIGURE 3. FIGURE 4. FIGURE 5. FIGURE 6. FIGURE 7. FIGURE 8. FIGURE 9. FIGURE 10. FIGURE 11. FIGURE 12. FIGURE 13. FIGURE 14. FIGURE 15.

FUNCTIONAL BLOCK DIAGRAM................................................................................5 CAMERA INTERFACE YUV - 4:2:2 - 16-BIT HORIZONTAL TIMING WAVEFORMS6 CAMERA INTERFACE VERTICAL – INTERLACE TIMING WAVEFORMS..............6 CAMERA INTERFACE VERTICAL – PROGRESSIVE TIMING WAVEFORMS..........7 MEMORY MAP ..............................................................................................................7 DRAM INTERFACE WRITE CYCLE TIMING WAVEFORMS .....................................7 DRAM INTERFACE READ CYCLE TIMING WAVEFORM.........................................8 DRAM INTERFACE REFRESH CYCLE TIMING WAVEFORMS.................................8 STRUCTURE OF OMNICE.............................................................................................9 SOF/EOF FORMATS...................................................................................................9 CLOCK SCHEME OF OV511+ ..................................................................................10 USB COMMUNICATION FLOW..............................................................................11 PIO READ CYCLE TIMING WAVEFORMS ............................................................12 PIO WRITE CYCLE TIMING WAVEFORMS ..........................................................12 100-PIN PQFP PACKAGE.........................................................................................14

2

Tables TABLE 1. TABLE 2. TABLE 3. TABLE 4. TABLE 5. TABLE 6. TABLE 7. TABLE 8. TABLE 9. TABLE 10. TABLE 11. TABLE 12. TABLE 13. TABLE 14. TABLE 15. TABLE 16. TABLE 17. TABLE 18. TABLE 19. TABLE 20. TABLE 21. TABLE 22. TABLE 23. TABLE 24. TABLE 25. TABLE 26. TABLE 27. TABLE 28. TABLE 29. TABLE 30. TABLE 31. TABLE 32. TABLE 33. TABLE 34. TABLE 35.

CAPABILITY OF CAMERA INTERFACE .....................................................................6 MAXIMUM PIXEL COUNT OF ONE 256KX16 DRAM ................................................6 PARAMETERS OF DRAM INTERFACE TIMING.........................................................8 PARAMETERS OF PIO TIMING..................................................................................13 PIN DESCRIPTIONS.....................................................................................................15 DC ELECTRICAL CHARACTERISTICS......................................................................17 ABSOLUTE MAXIMUM RATINGS .............................................................................17 RECOMMENDED OPERATING CONDITIONS ..........................................................17 USB DC ELECTRICAL CHARACTERISTICS .............................................................17 USB FULL SPEED OUTPUT DRIVER ELECTRICAL CHARACTERISTICS ..............17 CAMERA INTERFACE REGISTER LIST ....................................................................18 DRAM INTERFACE REGISTER LIST .........................................................................19 ISO FIFO REGISTER LIST ...........................................................................................19 PIO REGISTER LIST ....................................................................................................20 SCCB REGISTER LIST.................................................................................................20 SYSTEM CONTROL REGISTER LIST.........................................................................22 OMNICE REGISTER LIST ...........................................................................................23 DEVICE DESCRIPTOR LIST .......................................................................................24 CONFIGURATION DESCRIPTOR LIST ......................................................................24 INTERFACE DESCRIPTOR LIST OF ALTERNATE 0 ................................................25 ENDPOINT DESCRIPTOR LIST OF ALTERNATE 0, PACKET SIZE 0......................25 INTERFACE DESCRIPTOR LIST OF ALTERNATE 1 ................................................25 ENDPOINT DESCRIPTOR LIST OF ALTERNATE 1, PACKET SIZE 33....................25 INTERFACE DESCRIPTOR LIST OF ALTERNATE 2 ................................................25 ENDPOINT DESCRIPTOR LIST OF ALTERNATE 2, PACKET SIZE 129..................26 INTERFACE DESCRIPTOR LIST OF ALTERNATE 3 ................................................26 ENDPOINT DESCRIPTOR LIST OF ALTERNATE 3, PACKET SIZE 257..................26 INTERFACE DESCRIPTOR LIST OF ALTERNATE 4 ................................................26 ENDPOINT DESCRIPTOR LIST OF ALTERNATE 4, PACKET SIZE 385..................26 INTERFACE DESCRIPTOR LIST OF ALTERNATE 5 ................................................27 ENDPOINT DESCRIPTOR LIST OF ALTERNATE 5, PACKET SIZE 513..................27 INTERFACE DESCRIPTOR LIST OF ALTERNATE 6 ................................................27 ENDPOINT DESCRIPTOR LIST OF ALTERNATE 6, PACKET SIZE 769..................27 INTERFACE DESCRIPTOR LIST OF ALTERNATE 7 ................................................27 ENDPOINT DESCRIPTOR LIST OF ALTERNATE 7, PACKET SIZE 961..................28

3

1 1 § § § § § § § § § § § § § § §

Features Low cost, integrated solution for USB PC camera applications Built-in USB transceiver with selectable external USB transceiver interface USB compliance current consumption in unconfigured, configured, suspend & operating modes USB full speed signaling bit rate USB high powered, bus powered device Supports USB control and isochronous pipes Supports 8 isochronous interface alternates of up to 7.5Mbps USB transfer rate 256Kx16, 5V, EDO, CAS-BEFORE-RAS refresh, 60ns DRAM required Camera Interface: 16-bit YUV 4:2:2/RGB raw data formats (two channels) or 8-bit Y 4:0:0/RGB raw data formats (one channel only) Supports clamping, down-scaling & filtering circuits for different video formats (VGA/SIF/QSIF or CIF/SIF/QCIF/QSIF) Supports proprietary real-time compression engine of up to 8:1 (10~15fps at VGA) VGA resolution uncompressed still image with snapshot button Supports SCCB (Serial Camera Control Bus) master function running at 100KHz (normal mode) Supports programmable LED control Supports programmable switching power clock with frequencies of 24K/48K/96K/192KHz

4

2 2

Architecture

2.1 General Description OV511+ based on OV511, is a low cost and highly integrated solution for USB PC camera applications. It remains OV511’s performance unchanged or is improved, while some new features were implemented. New features include built-in USB transceiver with selectable external USB transceiver interface, more effective packet size of the isochronous pipe, programmable LED control, programmable switching power clock with frequencies of 24K/48K/96K/192KHz, etc. OV511+ is a USB PC camera controller that includes a proprietary compression engine supporting real time image transfer through USB bus. A complete USB camera system consists of OV511+, a 256Kx16 EDO DRAM, and a digital camera such as OV7620 for VGA resolution or OV6620 for CIF resolution. Camera Interface generates different image formats by taking either 16-bit YUV 4:2:2/RGB raw data or 8-bit Y 4:0:0/RGB raw data inputs. OmniCE is the proprietary compression engine. It not only performs 10~15fps for VGA and 30fps for CIF, but also allows very fast decompression with low CPU utilization. Depending on the camera device that is built with the system, either SCCB or Parallel IO bus can be chosen. The SCCB bus master uses two dedicated pins “SIO-0” & “SIO-1”, while the PIO shares with Y & UV buses. Snapshot button allows users to take a high quality, VGA resolution uncompressed still image The functional blocks of OV511+, as shown in the following figure, consist of Camera Interface, DRAM Interface, OmniCE, UDC interface, ISO FIFO, System Control, SCCB and PIO. Figure 1.

Functional Block Diagram

16

256Kx16 DRAM

OV7610 OV6620

HREF VSYNC PCLK Camera Interface

16

DRAM Interface

16

OmniCE

UDC Interface

8

ISO FIFO

8

8/16 bit bus

48MHz

USB

Control

USB Xver

USB Device Controller

5

2.2

Functional Description

2.2.1 Camera Interface OV511+ digital video inputs are either 16-bit YUV 4:2:2/RGB raw data formats (two channels) or 8-bit Y 4:0:0/RGB raw data formats (one channel only). Clamping, downscaling & filtering functions are also supported by Camera Interface. However, it doesn’t guarantee that all input formats can be compressed by OmniCE. Table 1. Capability of Camera Interface Channels Input Clamping Formats 2, 16-bit (Y & UV) 1, 8-bit (Y only)

YUV 4:2:2 16-bit RGB raw Y 4:0:0 8-bit RGB raw

Down-Scaling

Filtering

Compression (OmniCE)

Available Available Available Available

Available Available Available Not available

Available Not available Available Not available

Available Available Available Available

If the camera input format is 16-bit YUV 4:2:2 mode, the output of the camera interface can be configured as YUV 4:2:0 or 4:0:0, as well as YUV 4:2:2. The maximum clamped image size is 1024 pixels wide and 1024 lines height in increment of 8, depending on the camera input format. The actual image size is limited by the capability of DRAM. Table 2. Maximum Pixel Count of one 256KX16 DRAM Output Formats of Camera Interface

Pixel Count

YUV 4:2:2 YUV 4:2:0 Y 4:0:0

256K 344K 512K

The downscaling function sub-samples the image in both horizontal & vertical directions by choosing scaling factor 1, 2, 4 or 8. No up-scaling feature is implemented. The anti-aliasing filter decimates downscaling images to get rid of alias and improve image quality. Figure 2.

Camera Interface YUV - 4:2:2 - 16-bit Horizontal Timing Waveforms

CCLK PCLK triggers data at rising edge

HREF beginning of an active line

end of an active line

Y

10H

Y0

Y1

Y2

Y3

Y636

Y637

Y638

Y639

10H

UV

80H

U0

V0

U2

V2

U636

V636

U638

V638

80H

Figure 3.

Camera Interface Vertical – Interlace Timing Waveforms

VSYNC FODD HREF

479

480

1

2

239

6

240

241

242

Figure 4.

Camera Interface Vertical – Progressive Timing Waveforms

VSYNC FODD HREF

2

1

479

480

2.2.2 DRAM Interface DRAM interface generates DRAM addresses for Write and Read cycles based on the configured image size and data format. External DRAM is partitioned according to the data formats such as 4:2:2, 4:2:0 or 4:0:0. DRAM interface also arbitrates the DRAM access between write request from the camera interface and read request from OmniCE. It also performs the flow control to avoid image overflow and underflow conditions occurred. OV511+ supports 5V EDO, CAS-BEFORE-RAS refresh, 60ns DRAM. Figure 5.

Memory Map

4:2:2

4:2:0

4:0:0

00000

00000

00000

Y

Y

1FFFF 20000 U 2FFFF 30000 V 3FFFF

Figure 6.

RAW

2AFFF 2B000 U 357FF 35800 U 3FFFF

3FFFF

DRAM Interface Write Cycle Timing Waveforms tRASP

tRAH

Ras_ tCAS

Cas_

tRCD

We_

Addr

tPC

Row

tASC

Col tDS

tDH

Data

7

tCAH

Figure 7.

DRAM Interface Read Cycle Timing Waveform tRASP

tRAH

Ras_ tCAS

Cas_

tRCD tASC

Oe_

tOFF

tPC

tCAH

tCAC

Row

Addr

tOEZ

Col tRAC

Data Figure 8.

DRAM Interface Refresh Cycle Timing Waveforms tRC tRAS

Ras_

tRP tRPC

Cas_ Table 3. Symbol tRASP tRAH tCAS tRCD tASC tCAH tDS tDH tRAC tCAC tOEZ tRPC tCHR tCSR tRC tRAS tRP

tCSR

tCHR

Parameters of DRAM Interface Timing Parameter Min RAS_ pulse width Row address hold time CAS_ pulse width RAS_ to CAS_ delay time Column address setup time Column address hold time Data-in setup time Data-in hold time Access time from RAS_ Access time from CAS_ Output buffer turnoff delay form OE_ RAS_ precharge to CAS_ hold time CAS_ hold time CAS_ setup time Random read or write cycle time RAS_ pulse width RAS_ precharge time

Max

Unit

185 18.5 18.5 39 18.5 11.5 18.5 11.5  

   44     60 15

18.5 55.5 55.5 185 111 74

     

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

2.2.3 OmniCE OmniCE is a proprietary compression engine, constructed by the predictor, the quantizer, as well as encoder along with look-up tables. The predictor predicts image pixels horizontally and vertically. The look-up table can be programmed by the software driver according to calculation of probability.

8

The compression ratio of OmniCE varies from 4 to 8, depending on image complexity. Parameters can be modified dynamically by the software driver to achieve the desired frame rate. It can also be disabled and bypass uncompressed data. Figure 9.

Structure of OmniCE

Input

Predictor

Quantizer

Encoder

Programmed by Host

Output

Look-up Table

2.2.4 ISO FIFO OV511+ implements one isochronous endpoint for video data transfer. The available alternates include packet size of 0, 33, 129, 257, 385, 513, 769 & 961. The corresponding ISO FIFO size has to be set by the software driver right before the current alternate is set. The size of ISO FIFO is configurable from 32 to 960 in increment of 32. Moreover, in order to assist packet reordering in the host, a packet number inserted at the end of each packet can be turned on. An image frame starts with the SOF packet (Start Of an image Frame), while ends with the EOF packet (End Of an image Frame). The packet number counts up from 01 to 255 and back to 01. Only the SOF packet uses the packet number 00. SOF/EOF packets are indicated by the unique combination which the 1st to the 8th byte are all “0”s and the 9th byte contains a non-zero header. This header contains image information, such as the operating mode, snapshot flag & even/odd field. In the case of the EOF packet, the 10th and 11th bytes also contain the image width and height information. Figure 10. SOF/EOF Formats 0,33,129,257,385,513,769,961 Packet

SOF/EOF

1

11

...

9

Video data ......

1

Only available for EOF

10~11

Packet number

Tag 8"0"s

SOF/EOF

EOF 10th, 11th bytes

Frame header byte, the 9th byte Bit

7

6

5

4

3

2

1

7 - EOF 6 - compression enabled 5 - 422/420/400 modes 4 - 422/420/400 modes 3-1 2 - snapshot bottom on 1 - snapshot frame 0 - even/odd field

9

0

Hor. width

Ver. width

2.2.5 UDC interface UDC interface performs hand-shaking protocols with USB Device Controller. Its function includes isochronous transfer, responding vendor commands & descriptors, and generating read/write cycles to internal registers. 2.2.6 System Control System control unit performs functions of system clock generation, Power On Reset, software reset scheme, USB Reset command, system initialization, snapshot and USB suspend. OV511+ takes 48MHz crystal input for USB bus. “CLK_48M” is also divided by 2 and provides clock of core logic and camera clock. Pin “EN_OSC27” has to be pulled down. Figure 11. Clock Scheme of OV511+ OV511+ 48 MHz

% 2

core logic

camera

USB Device Controller

There are three kinds of reset scheme supported by OV511+. The Power-On Reset (pin “RESETB”) and USB Reset command initialize OV511+ & camera circuits. The Camera Reset (pin “RESET”) toggles as soon as either Power-On Reset or USB Reset is asserted. The software reset allows individual functional blocks to be reset without altering the register contents. Software reset is necessary when changing camera formats, ISO packet size, compression parameters, etc. According to USB specification, a high-power (> 100mA) function requires staged switching of power. It must first come up in a reduced power state of less than one unit load, which is 100mA. System initialization function stops system clocks as well as sets camera into power down mode by using pin “PWDN” before bus enumeration. If sufficient power exists in the power budget, the remainder of the function will be powered on by setting register bit “EN_SYS” (register 53h). Pin “SPWDN” has to be pulled up for the current power management scheme. The snapshot function can be achieved by either setting register bit “SNAP[2]” (register 52h) or pushing a button(pin “SNAPB”) on the system. Hardware snapshot function is initiated by setting register bit “SNAP[0]” (register 52h). Once pushing the button, the internal snapshot signal is latched, registers of the camera interface & camera itself are automatically modified to desired formats as well. As soon as OV511+ captures one single frame of image and sends to the host, the software driver clears the internal snapshot signal for next snapshot operation by writing a sequence 0-1-0 to register bit “SNAP[1]” (register 52h). When USB bus idles for more than 3 msec, OV511+ goes into suspend mode and all clocks are stopped by pin “OSC_EN”, while all internal registers are remained the same values. The system wakes up when the USB resume condition occurs. LED control pin “LEDCTL” is accessible by register bit “LEDCTL” (register 55h). It can also be a programmable I/O pin. Switching power clock pin “PWCK” is programmable by register bit “PWCK[1:0]” (register 54h). It can be programmed to frequencies of 24K/48K/96K/192KHz.

10

2.2.7 USB Device Controller The camera system constructed by OV511+ is defined as a “high-power, bus-powered” USB device. It means that the camera system draws over one and a maximum of five unit loads from the USB cable. Two endpoints are implemented for communication flows between the USB camera device and the USB host. Endpoint 0 is an In-Out type CONTROL endpoint which is the pipe of Descriptors, Configurations and Vendor Commands (internal registers). Endpoint 1 is an In type Isochronous endpoint which is the pipe of video streams. Figure 12. USB Communication Flow

Host

OVT software driver

Buffers

Pipes

Comm. Flows

USB Logic Device Endpoint 0

Interface

Endpoint 1

The USB Descriptors are configured as one configuration, one interface and eight alternates. The packet sizes of eight alternates are 0, 33, 129, 257, 385, 513, 769 & 961. Build-in USB transceiver (pull-down) and external transceiver interface (pull-up) can be switched by selecting pin “TXRSEL”. The camera system is defined as a full speed device and needs to be terminated with the pull-up resistor on the D+ line. 2.2.8 SCCB (Serial Camera Control Bus) The data rate of the SCCB bus master is programmable and the maximum data rate is 100K.

2.2.9 PIO PIO is a parallel I/O port for accessing external SRAM based devices. It has a standard memory like interface that requires address, data and read/write control signals. These signals share the same buses with the Y and UV video channels. When PIO is enabled, Y channel becomes the PIO data bus for both input and output modes, and UV channel becomes address bus and read/write control signals. In this case, video data inputs will be interrupted. The pin assignment of PIO control signals is as following, § UV [5:0] share with ADDR [5:0], any arbitrary address can be defined by users as CSB § UV [6] shares with WEB § UV [7] shares with OEB

11

Figure 13. PIO Read Cycle Timing Waveforms

OEB/UV[7] WEB/UV[6] tRC

ADDR[5:0]/UV[5:0] tCSA

DATA[7:0]/Y[7:0]

ADD0

ADDn

tCSX

tAA

DATA0

tOEZ

DATAn tAx

Figure 14. PIO Write Cycle Timing Waveforms

OEB/UV[7] tWE

WEB/UV[6] tWC

ADDR[5:0]/UV[5:0]

tAS

ADD0

tAH ADDn

tDS

DATA[7:0]/Y[7:0]

DATA0

DATAn tDH

12

tOE

Table 4. Symbol

Parameters of PIO Timing Parameter

TOE TOEZ TRC TCSA TCSX TAA TAX TWC TWE TAS TAH TDS TDH

Output enable access time Output enable to z delay Register read cycle time Chip select access time Chip select to data invalid time Address access time Address data invalid time Register write cycle time Write enable pulse width Write cycle address set up time Write cycle address hold time Write cycle data set up time Write cycle data hold time

Min

Max

Unit

15 15  30 15 30 15      

  100     100 50 0 0 20 0

ns ns ns ns ns ns ns ns ns ns ns ns ns

2.2.10 Custom ID Custom ID is a specific 8-bit input port that can be pulled up/down to identify company names of manufacturers. The Custom ID is checked by the software driver and may be requested directly from OVT. If no Custom ID is applied, pull-down resistors are also required to avoid bus floating. Pin “IDESL [1:0]” have to be set as “01”.

13

3 3

Pin Definition

3.1

Pin Assignments

Figure 15. 100-Pin PQFP Package

L E D U C V T 7 L

P W C K

S P W V D S N S

D A V T D A D 8

D D A A T T A A 1 9 0

D D D A A A T T T A A A 1 1 1 1 2 3

D A T A 1 4

D A T A V 1 S 5 S

D A V T D A D 0

D D D D D D D A A A A A A A T T T T T T T V A A A A A A A S 1 2 3 4 5 6 7 S

A A R D D V W A D D D E S R R D B B 0 1

8 0

7 8

7 7

7 5

7 3

7 1

6 8

6 7

6 5

6 3

5 5

7 9

7 6

7 4

7 2

7 0

6 9

6 6

6 4

6 2

6 1

6 0

5 9

5 8

5 7

5 6

5 4

5 3

5 2

5 1

81

50 ADDR2

UV5 82

49 ADDR3

UV4 83

48 ADDR4

UV3 84

47 ADDR5

UV2 85

46 VSS

UV1 86

45 VDD

UV0 87

44 ADDR6

CCLK 88

43 ADDR7

PCLK 89

42 ADDR8

UV6

VDD 90

41 OEB

VSS 91

40 VSS

OV

VSYNC 92 HREF 93 SIO1 94

511+

39 VDD 38 CASB 37 DPLS 36 TXENL

FODD 95

35 XVERDATA

SIO0 96 RESET 97

34 DP

PWDN 98

33 DM

Y7 99

32 TXDPLS

Y6 100

31 TXDMNS

2 9

3 0

2

3

4

5

6

7

8

9

1 1

1 2

1 3

1 5

1 6

1 7

1 8

1 9

2 0

2 1

2 2

2 3

2 4

2 5

2 6

2 7

2 8

V V D S D S

Y 5

Y 4

Y 3

Y 2

Y 1

Y 0

I I S D D N S S A E E P L L B 1 0

E N O S C 2 7

C V V U D S S D S T O M I D 7

C U S T O M I D 6

C U S T O M I D 5

C U S T O M I D 4

C U S T O M I D 3

C U S T O M I D 2

C U S T O M I D 1

C U S T O M I D 0

C L K 2 7 M 1

C L K 2 7 M 2

R E S E T B

D M N S

O S C E N

T C C X L L R K K S 4 4 E 8 8 L M M 1 2

1

1 0

1 4

14

3.2 Pin Descriptions Table 5. Pin Descriptions Items/Pin # Name Camera Interface 99, 100, 3~8

Y[7:0]

I/O Function IT/OT Camera Y data input

mA 8

PIO data input/output 80~87

UV[7:0]

IT/OT Camera UV data input

8

PIO address, read/write control output 89

PCLK

IT

Camera pixel clock input

93

HREF

IT

Camera horizontal window reference input

92

VSYNC

IT

Camera vertical sync. Input

95

FODD

IT

Camera even/odd field flag input

88

CCLK

O

Camera clock output. Software programmable

8

97

RESET

O

Camera hardware reset output

4

98

PWDN

O

Camera power switch control output

4

SCCB Interface 96

SIO-0

IS/OD SCCB serial data. Pull-up resistor (4.7K Ohm) is required

4

Bi-directional 94

SIO-1

OD

SCCB serial clock output. Pull-up resistor (4.7K Ohm) is required

4

DRAM Interface 67~74, 57~64

DATA[15:0]

IT/OT DRAM 16-bit data

8

41

OEB

O

DRAM OE_ output

8

54

WEB

O

DRAM WE_ output

8

42~44, 47~52

ADDR[8:0]

O

DRAM address output

8

38

CASB

O

DRAM CAS_ output

8

53

RASB

O

DRAM RAS_ output

8

35

XVER_DATA

IT

USB differential receiver data input (external transceiver)

26

DMNS

IT

D- input (external transceiver)

37

DPLS

IT

D+ input (external transceiver)

36

TXENL

O

Output enable for differential driver (external transceiver)

4

31

TXDMNS

O

NRZI formatted D- output (external transceiver)

4

32

TXDPLS

O

NRZI formatted D+ output (external transceiver)

4

33

DM

UI/O D- input/output (internal transceiver)

34

DP

UI/O D+ input/output (internal transceiver)

USB Interface

Clock & Misc. 25

RESETB

IS

Power-On Reset input. Low-active

29

CLK_48M1

OSCI 48MHz oscillator/crystal input

30

CLK_48M2

OSCO 48MHz crystal output

23

CLK_27M1

OSCI 27MHz oscillator/crystal input

24

CLK_27M2

OSCO 27MHz crystal output

27

OSC_EN

O

Power control for oscillator. 1 for power enabled

28

TXRSEL

IS

Internal/external transceiver control. 0 for internal

11

SNAPB

IS

Snapshot button input. Cleared by the software driver

9~10

IDSEL[1:0]

IS

VID & PID select. 01 is required

77

SPWDN

IS

Power down mode select. 1 is required

13, 16~22

CUSTOM_ID[7:0]

IS

Custom ID inputs

15

4

Pin Descriptions (continued) Items/Pin # Name

I/O Function

mA

12

EN_OSC27

IS

27MHz clock input select. 1 for enabled

78

PWCK

O

Switching power clock output

8

79

LEDCTL

O

LED control

4

VDD

I

Power

VSS

I

Ground

Power & Ground 1, 14, 39, 45, 55, 65 75, 90 2, 15, 40, 46, 56, 66 76, 91 I IS IT O OSCI OD OT OSCO UI/O

: Input : CMOS Schmitt Trigger Level Input : TTL Level Input : Normal Output : Oscillator Input : Open Drain Output : Tri-state Buffer Output : Oscillator Output : USB Transceiver Input / Output

16

4 4

Electrical Characteristics

Table 6. DC Electrical Characteristics VDD = 5V + 5%, TA = 0 to 70oC Symbol Parameter

Condition

VIH

High level input voltage

VIL

Low level input voltage

VT+

Schmitt trigger, positive-going threshold

VT-

Schmitt trigger, negative-going threshold

IIH

High level input current

VIN = VDD

IIL

Low level input current

VIN = VSS

VOH

High level output voltage

Min

Low level output voltage Tri-state output leakage current

VOUT = VSS or VDD

IDD

Quiescent supply current

VIN = VSS or VDD

CIN COUT

ICCS ILO VDI VCM VSE VOL VOH CIN

Table 10. Symbol TR Tf Trim VCrs Zdrv

-10

10

uA

-10

10

uA

V V

V V

10

uA

100

uA

Input capacitance

4

pF

Output capacitance

4

pF

V V mA o C

Rating

Unit

4.75 to 5.25 0 to 70

USB DC Electrical Characteristics Parameter

Condition 0V