Display Interface Board EVAL-AD988xEB GENERAL DESCRIPTION

BOARD FUNCTIONS

The purpose of the display interface board is to aid in the evaluation of the AD9882, AD9883A, AD9884A, AD9887, or AD9888. It is designed to be used in conjunction with any of the evaluation boards for these parts, and is included as part of the evaluation board kits. It is a conduit for displaying images on any flat panel monitor, CRT, LCD projector, or TFT panel. (Note that in order for the TFT panel to be used, it must have an LVDS interface.)

A block diagram of the display interface board is shown below. The following sections describe the functional blocks of the display interface board.

REQUIREMENTS

All that is needed to use this board with an evaluation board for the AD9882, AD9883A, AD9884A, AD9887, or AD9888 (included), is a 5 V to 12 V dc power supply (included), a Centronix printer cable or USB A to B cable for serial bus programming (included), and a computer and any flat panel monitor, CRT, or LCD projector. LIMITATIONS

This board is designed to help demonstrate the performance of the AD9882, AD9883A, AD9884A, AD9887, or AD9888 interface chips only. In order to accurately evaluate the interfaces on these parts, it is recommended to use the DVI output (J8) of the display interface board. It is also recommended to use the native resolution of the display device to avoid scaling artifacts. If a display device with DVI input is not available, the analog output (J6) should also be able to supply a high quality image as long as the display device uses high quality ADCs and a graphics controller. POWER

This board is designed to receive 5 V to 12 V dc through connector J4. The power supply that is included in the kit plugs into that connector.

Data Demultiplexing

The Altera EP1K10QC208 (U6) performs most of the logic functions on the display interface board. Among these functions is the demultiplexing of the digital RGB data output from the AD988x when the AD988x is in single-port data output (24-bit) mode (the AD9882 and AD9883A are 24-bit only). The DVI and LVDS transmitters, as well as the digital-to-analog converters (DACs), require 48-bit RGB data. Therefore, demultiplexing is required when in single-port mode. DE Generation

The DVI and LVDS interfaces require a data enable (DE) signal that indicates when there is active image data. Since the analog graphics signal does not contain DE, the FPGA on the display interface board is required to generate it. The duration of DE is programmable via the display interface board configuration software to support the following video resolutions: VGA, SVGA, XGA, SXGA, UXGA, 480p, and 720p. Color Space Conversion

The FPGA also contains circuitry to perform color space conversion for 24-bit YPbPr data, which can be enabled via the display interface board configuration software. This can be used in conjunction with the midscale clamp feature on the analog interface of the AD988x devices to provide the proper colors for a YPbPr video signal. The color space conversion also works with YPbPr signals transmitted over the DVI interface. Note that this feature is not supported on revision 0.0 of the FPGA firmware.

FUNCTIONAL BLOCK DIAGRAM LVDS XMIT WITH CONNECTOR

BLU A 8

8

BLU B 8

8 FPGA 8 [DATA DEMUX (SINGLE-PORT MODE), 8 DE, GEN, AND 8 DE CONTROL] 8

GRN A 8 GRN B 8 RED A 8 DIGITAL RGB AND SYNCS FROM AD988x

RED B 8

8

8

8

TMDS XMIT

8

TO FLAT PANEL MONITOR OR LCD PROJECTOR

TO CRT OR FLAT PANEL MONITOR

8 8

8 SERIAL INTERFACE

B

DAC

G

8 8

PARALLEL INTFC CONN

DAC

8

SYNCS

REV. 0

8

DVI CONNECTOR

8

VGA CONN

POWER

DAC

R

USB INTFC

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.

EVAL-AD988xEB DVI Output

To implement the controls, the Write button at the top, righthand side of the window must be clicked. This is true unless the Load Register on Change box below the Write button is checked. In this case, the registers are updated as soon as any change is made in the window.

The display interface board provides a DVI output via SiI160 transmitter (U15) and DVI-I connector (J8). This can be connected via DVI cable to any display device (flat panel monitor or LCD projector) to display any image from VGA to UXGA-60 (the SiI160 is limited to 25 MHz to 165 MHz operation). LVDS Output

The display interface board provides an LVDS output via DS90C387 transmitter (U5) and LVDS data connector (J9). This can be connected via a user provided cable to any board flat panel with LVDS interface (such as Samsung’s 21.3" UXGA panel, LTM213U3-L01-0 or Sharp’s 18" SXGA panel, LQ181E1LW31) to display an image using that panel’s native resolution. This interface is capable of operating up to UXGA-75 (202.5 MHz). Note that this feature has not been tested on boards with revisions 0.0 and 0.1 of the FPGA firmware. Also note that, in order to use the LVDS outputs, the user must provide the data cable, panel power, and backlight power. Analog Output

The display interface board provides an analog output via high performance AD9751 DACs (U11–U13) and 15-pin VGA connector (J6). This can be connected via VGA cable to any display device (flat panel monitor, CRT, or LCD projector) to display any image from VGA to UXGA-75.

Figure 1. Display Interface Board Configuration Window Hsync Delay

The first box in the window controls the number of data clock cycles that occur between Hsync and the beginning of DE. This is a decimal number that is written to an 8-bit register. For ease of use, a sliding bar is also included as an alternative method for controlling the Hsync delay. Moving the bar to the right increases the delay and is reflected in the box to the right. Moving the bar left decreases the delay.

Serial Bus to Computer Interface (USB or Printer Port)

Some circuitry is needed to interface the AD988x’s and the display interface board’s serial register with a computer. The display interface board provides both a USB and a parallel (printer) port interface. The USB interface consists of a USB-B connector (J2), USB controller (U14), and an EEPROM (U16) that contains board ID information. The circuitry for the printer port’s serial interface uses U1 and U9 along with the Centronix connector, J1.

If using the DVI output of the display interface board, note that an image may not be visible until the Hsync delay is near the appropriate amount of delay from Hsync to active video.

Panel Power

Vsync Delay

The display interface board has three voltage regulators that generate 2.5 V and 3.3 V for its own logic and 5 V for the AD988x evaluation board. These voltages are regulated off of the 5 V to 12 V input at J4.

The next box in the window controls the number of Hsync periods that occur between Vsync and the beginning of DE. This is a decimal number that is written to a 6-bit register. A sliding bar is also included for Vsync delay control.

Panel Protection Circuitry

Applying power to a panel without the appropriate signals can damage a panel. Therefore, for users using the LVDS interface, a panel enable signal is provided as an optional control mechanism for the user provided panel power circuitry. This signal is routed to the header at W2. The logic to control this function is contained in the FPGA.

Hsync Polarity

AD988x Evaluation Board Power

Since the timing logic that generates DE relies on the leading edge of Vsync, it is required to know the polarity of the Vsync signal. Clicking on the appropriate box sets the Vsync polarity.

Since the timing logic that generates DE relies on the leading edge of Hsync, it is required to know the polarity of the Hsync signal. Clicking on the appropriate box within the Display Interface Board Configuration window sets the polarity. Vsync Polarity

This board provides regulated 5 V power to the AD988x evaluation boards as well, though the J3 connector.

Display Resolution

SOFTWARE

The Display Resolution pull-down menu allows the user to select the video resolution to be displayed. The options are VGA, SVGA, XGA, SXGA, UXGA, 480p, and 720p.

The display interface board configuration software is a Visual Basic program requiring a Windows 95®, or newer, operating system. It is on a self-installing CD package included with the evaluation board (in the \DEPL evaluation software subdirectory). The display interface board configuration software should be loaded into the \Program Files\ADI Software directory upon completing installation. Clicking the Display Interface Board Configuration icon displays the Display Interface Board Configuration window shown in Figure 1. Using this screen, the user can control the features of the display interface board.

Swap AB Ports

The Swap AB Ports check box allows the user to route the first pixel of demultiplexed 24-bit data to the even output port of the FPGA rather than to the odd output port. The timing relationship between data and the data clock (PANEL_CLK_OUT) remains the same.

–2–

REV. 0

EVAL-AD988xEB Enable Color Conversion

Hsync and Vsync are selected. If the jumpers are placed between Pins 2 and 3, the sync outputs (HSOUT and VSOUT) of the AD988x are selected. Either configuration will work. (Note that if using the AD9884A evaluation board, raw Vsync must be used since the AD9884A does not supply a VSOUT signal.) However, the user should verify that the polarities of these signals match the setting in the display interface setup software.

The Enable Color Conversion check box allows the user to turn on the 24-bit color space converter in the FPGA. Note that this feature is not supported on revision 0.0 of the FPGA firmware. Output DAC Frequency Range

The Output DAC Frequency Range pull-down menu allows the user to select the operating range of the analog output. The 50 MHz to 150 MHz range should be adequate to display all resolutions XGA and above (including 720p). For lower speed resolutions, the appropriate range should be selected.

PC Port Selection

The jumpers at W17 to W21 must be configured appropriately to use the desired PC port for software control. To select USB, the jumpers must be placed between Pins 2 and 3. To select the printer port, the jumpers should be placed between Pins 1 and 2.

PC Port Selection

Just below the Load Register on Change check box is the pulldown menu that allows the user to select between the USB and parallel ports for the software interface. Refer to the PC Port Selection paragraph in the Configuring the Board section for further setup instructions.

USB Driver Installation

Follow these steps to install the USB drivers on your PC: 1. Connect the board to the power supply. 2. Connect the USB cable from the PC to the board. Windows will see the new device and ask to install drivers for it.

Digital Output Select

This allows the user to select between the LVDS and DVI outputs. Only one of these interfaces can be used at a time. If the DVI interface is selected then the LVDS interface is powered down, and vice versa.

4. Choose Search for Drivers and click Next. 5. Choose Specify a Location and browse on the CD-ROM to the USB Drivers\win2k directory.

DE Select

6. Choose Next and follow any remaining instructions.

This allows the user to select the source for data enable generation. If the analog interface of the AD988x is being used, then Generated DE must be selected since the analog interface does not include a DE signal. If the DVI interface of the AD988x is being used, either Generated DE or Digital DE can be used. However, it is recommended that the Digital DE be selected in this case.

7. If asked for any files, always browse to the same USB Drivers\win2k (or \win98) folder to find them. DCLK Selection

The SXGA panel drive board is configured so that the DCLK output of the AD988x drives the generation of PANEL_DCLK and PANEL_DE. This is accomplished by placing a strap between Pins 1 and 2 of Header W3. The PANEL_DCLK and PANEL_DE signals could also possibly be derived from an external clock source. This would require removing the strap from W3, installing R9, an SMB connector at J5, and a jumper wire from W13 to W3-2. Contact the Flat Panel Applications team at [email protected].

Port Mode

This allows the user to select the operating mode of the AD988x. If the AD988x is operating in single-channel (24-bit) output mode (the AD9882 and the AD9883 have single-channel output only), then Single Port (24-bit) must be selected. If the AD988x is operating in dual-channel (48-bit) output mode, then Dual Port (48-bit) must be selected.

SCHEMATICS AND LAYOUT

The schematics and layout for this board are included in separate files. They can be found on the CD.

CONFIGURING THE BOARD DE Generation

The VS_SEL (W15 in Figure 3) and HS_SEL (W16) jumpers allow the user to choose raw Vsync and Hsync or the VSOUT and HSOUT outputs of the AD988x to generate DE. If the jumpers are placed between Pins 1 and 2 (closer to U2), the raw

EVALUATION BOARD CONNECTIONS

Figure 2 illustrates how the display interface board interfaces with the AD9882 evaluation board. It also indicates the various connections needed to evaluate an image.

PRINTER PORT INTERFACE USB INTERFACE

DVI INPUT DVI OUTPUT

ANALOG INPUT DC INPUT ANALOG OUTPUT

Figure 2. Display Interface Board with the AD9882 Evaluation Board

REV. 0

–3–

51

52

53

54

55

56

BLUB_IN2

BLUB_IN3

BLUB_IN4

BLUB_IN5

BLUB_IN6

BLUB_IN7

59

60

61

62

63

64

65

GRNB_IN1

GRNB_IN2

GRNB_IN3

GRNB_IN4

GRNB_IN5

GRNB_IN6

GRNB_IN7

69

70

71

72

73

74

REDB_IN2

REDB_IN3

REDB_IN4

REDB_IN5

REDB_IN6

REDB_IN7

W10

W9

80

CLK_INV

J3

79

78

77

76

CLAMP

COAST

68

REDB_IN1

75

67

REDB_IN0

66

58

GRNB_IN0

57

50

BLUB_IN1

48

47

49

SOGOUT

BLUB_IN0

W8

W11

45

VSOUT

46

44

43

HSOUT

P40

P39

P38

P37

P36

P35

P34

P33

P32

P31

P30

P29

P28

P27

P26

P25

P24

P23

P22

P21

P20

P19

P18

P17

P16

P15

P14

P13

P12

P11

P10

P9

P8

P7

P6

P5

P4

P3

P2

CON_80P50F

P80

P79

P78

P77

P76

P75

P74

P73

P72

P71

P70

P69

P68

P67

P66

P65

P64

P63

P62

P61

P60

P59

P58

P57

P56

P55

P54

P53

P52

P51

P50

P49

P48

P47

P46

P45

P44

P43

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

W3

PWR_DN

SCL

SDA

VSYNC

HSYNC

W7

BLUA_IN[0:7]

BLUB_IN[0:7]

GRNB_IN[0:7]

REDB_IN[0:7]

REDA_IN7

REDA_IN6

REDA_IN5

REDA_IN4

REDA_IN3

REDA_IN2

REDA_IN1

REDA_IN0

GRNA_IN7

GRNA_IN6

GRNA_IN5

GRNA_IN4

GRNA_IN3

GRNA_IN2

GRNA_IN1

GRNA_IN0

BLUA_IN7

BLUA_IN6

BLUA_IN5

BLUA_IN4

BLUA_IN3

BLUA_IN2

BLUA_IN1

BLUA_IN0

DCLK

DCLK

DCLK_IN

ALT_CFG_DN

ALT_STATUS

ALT_DCLK

10

9

3.3V

8

J7

6

5 7

BLUB_IN[0:7]

P42

4

3

ALT_DCLK

GRNB_IN[0:7]

2

ALT_DATA 8 OE

4 DCLK

REDB_IN2 REDB_IN3 REDB_IN4 REDB_IN5 REDB_IN6 REDB_IN7

REDA_IN4 REDA_IN5 REDA_IN6 REDA_IN7 REDB_IN0 REDB_IN1

GRNB_IN6 GRNB_IN7 REDA_IN0 REDA_IN1 REDA_IN2 REDA_IN3

GRNB_IN5

GRNB_IN2 GRNB_IN3 GRNB_IN4

GRNA_IN7 GRNB_IN0 GRNB_IN1

GRNA_IN2 GRNA_IN3 GRNA_IN4 GRNA_IN5 GRNA_IN6

BLUB_IN4 BLUB_IN5 BLUB_IN6 BLUB_IN7 GRNA_IN0 GRNA_IN1

BLUA_IN6 BLUA_IN7 BLUB_IN0 BLUB_IN1 BLUB_IN2 BLUB_IN3

PGM_EN

R12 1k

2.5V

GND10 GRNB_IN5 VCC_IO6 GRNB_IN6 GRNB_IN7 REDA_IN0 REDA_IN1 REDA_IN2 REDA_IN3 2_5VCC11 REDA_IN4 REDA_IN5 REDA_IN6 REDA_IN7 REDB_IN0 REDB_IN1 VCC_IO7 REDB_IN2 REDB_IN3 REDB_IN4 REDB_IN5 REDB_IN6 REDB_IN7

GRNB_IN2 GRNB_IN3 GRNB_IN4 GND_CKLK

BLUA_IN6 BLUA_IN7 BLUB_IN0 BLUB_IN1 BLUB_IN2 BLUB_IN3 GND8 BLUB_IN4 BLUB_IN5 BLUB_IN6 BLUB_IN7 GRNA_IN0 GRNA_IN1 VCC_IO5 GRNA_IN2 GRNA_IN3 GRNA_IN4 GRNA_IN5 GRNA_IN6 2_5VCC9 GRNA_IN7 GRNB_IN0 GRNB_IN1 GND9 VCC_CKLK

18 PGM_EN

U2

READY 15

SER_EN

AT17LV512A

3.3V

53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104

RST

P1

HSYNC HSOUT

FSEN

P41

HS_SEL

2

42

W16

EP1K10QC208

DISPLAY_INTFC_FPGA

VS_SEL

2

3.3V

W15

REGEN_VS

2

VSOUT VSYNC

LATCH_DE

R13 1k

FSCL HSYNC_IN 1

RAW

FSDA 3

HSOUT

VSYNC_IN 3

VSOUT

W12REGEN_HS 1

U6

RAW

W14

1

LATCH_DE

ALT_DATA

DE_DETECT1 DE_DETECT2

–4–

ADD THIS TEXT TO SILK SCREEN

W2

DE_OUT PANEL_EN DE_DIG DVI_LVDS~_SEL

DE_DIG ALT_STATUS DAC_DIV0

5V

BLUA_IN4 BLUA_IN5 GRN_EVEN3 GRN_EVEN4 GRN_EVEN5 GRN_EVEN6 GRN_EVEN7 RED_EVEN0 RED_EVEN1 2_5VCC25 RED_EVEN2 RED_EVEN3 RED_EVEN4 RED_EVEN5 RED_EVEN6 RED_EVEN7 VCC_IO14 P193 BLU_ODD0 BLU_ODD1 BLU_ODD2 P189 GND21 PNL_CLK_OUT RST 2_5VCC23 PNL_CLK_IN DCLK GND20 GND19 BLU_ODD3 BLU_ODD4 VCC_IO13 BLU_ODD5 BLU_ODD6 BLU_ODD7 GRN_ODD0 GRN_ODD1 GRN_ODD2 GND18 GRN_ODD3 GRN_ODD4 GRN_ODD5 GRN_ODD6 GRN_ODD7 VCC_IO12 RED_ODD0 RED_ODD1 RED_ODD2 RED_ODD3 RED_ODD4 RED_ODD5 RED_ODD6 RED_ODD7

156 ^DATA0 155 ^DCLK 154 ^NCE 153 TDI 152 2_5VCC20 151 GND17 150 DAC_DIV1 149 NC27 148 DAC_DIV0 147 NC26 146 VCC_IO11 145 GND16 144 DVI_LVDS~_SEL 143 DE_DIG 142 PANEL_EN~ 141 DE_OUT 140 NC25 139 NC24 138 VCC_IO10 137 GND15 136 DETECT2 135 DETECT1 134 NC23 133 LATCH_DE 132 NC22 131 LATCH_DE~ 130 2_5VCC17 129 GND14 128 REGEN_VS 127 REGEN_HS 126 NC21 125 NC20 124 2_5VCC16 123 GND13 122 VSYNC 121 NC19 120 HSYNC 119 SCL 118 VCC_IO9 117 GND12 116 SDA 115 NC18 114 NC17 113 NC16 112 SEN 111 NC15 110 VCC_IO8 109 GND11 108 ^MSEL0 107 ^MSEL1 106 2_5VCC13 ^NCONFIG 105

DAC_DIV1

1 BLUA_IN3

REDA_IN[0:7]

BLUA_IN2

R10 1k

BLUA_IN0 BLUA_IN1

R6 1k

BLU_EVEN0

R11 1k

BLU_EVEN1

TDO VCC_IO1 GND1 NC1 NC2 NC3 GRN_EVEN2 GRN_EVEN1 GRN_EVEN0 NC4 NC5 NC6 BLU_EVEN7 NC7 BLU_EVEN6 BLU_EVEN5 GND2 2_5VCC2 VCC_IO2 GND3 BLU_EVEN4 BLU_EVEN3 BLU_EVEN2 NC8 BLU_EVEN1 NC9 BLU_EVEN0 NC10 GND4 2_5VCC4 VCC_IO3 GND5 NC11 NC12 BLUA_IN0 BLUA_IN1 NC13 BLUA_IN2 VCC_IO4 GND6 BLUA_IN3 NC14 BLUA_IN4 BLUA_IN5 2_5VCC7 GND7 TMS TRST ^NSTATUS

VCC 20

BLU_EVEN4 BLU_EVEN3 BLU_EVEN2 TCK ^CONF_DONE ^NCEO

DATA 2

BLU_EVEN6 BLU_EVEN5 SPARE5 BLU_ODD0 BLU_ODD1 BLU_ODD2 SPARE4

RED_EVEN2 RED_EVEN3 RED_EVEN4 RED_EVEN5 RED_EVEN6 RED_EVEN7

GRN_EVEN3 GRN_EVEN4 GRN_EVEN5 GRN_EVEN6 GRN_EVEN7 RED_EVEN0 RED_EVEN1

RED_ODD0 RED_ODD1 RED_ODD2 RED_ODD3 RED_ODD4 RED_ODD5 RED_ODD6 RED_ODD7

GRN_ODD3 GRN_ODD4 GRN_ODD5 GRN_ODD6 GRN_ODD7

BLU_ODD5 BLU_ODD6 BLU_ODD7 GRN_ODD0 GRN_ODD1 GRN_ODD2

BLU_ODD3 BLU_ODD4

RED_ODD[0:7]

GRN_ODD[0:7]

BLU_ODD[0:7]

PANEL_CLK_IN DCLK_IN

PANEL_CLK_OUT RST

W5

W6

RED_EVEN[0:7]

GRN_EVEN[0:7]

BLU_EVEN[0:7]

NOTE: PANEL_EN IS PROVIDED FOR LVDS INTERFACE USERS AS A PANEL POWER-DOWN SIGNAL (LOW-TRUE)

184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157

208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185

3.3V

1

9 NCS

BLU_EVEN7 TP7

10 GND

GRN_EVEN2 GRN_EVEN1 GRN_EVEN0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 1

12 NCASC

ALT_CFG_DN TP2

ALT_DCLK ALT_DATA

41

EVAL-AD988xEB

Figure 3. Schematics—1

REV. 0

GRNA_IN[0:7]

3

GRN_EVEN2

–5–

1

2

3

4

5

6

7

8

RED_EVEN0

RED_EVEN1

RED_EVEN2

RED_EVEN3

RED_EVEN4

RED_EVEN5

RED_EVEN6

RED_EVEN7

8

2

GRN_EVEN1

GRN_EVEN7

1

GRN_EVEN0

7

8

BLU_EVEN7

6

7

BLU_EVEN6

GRN_EVEN6

6

BLU_EVEN5

GRN_EVEN5

5

BLU_EVEN4

5

4

BLU_EVEN3

GRN_EVEN4

3

BLU_EVEN2

4

2

BLU_EVEN1

GRN_EVEN3

1

RA4

Figure 4. Schematics—2

22

9

10

11

12

13

14

15

16

H3

H2

RED_ODD7

RED_B7

H4

RED_ODD6

RED_B6

H1

RED_ODD5

RED_ODD4

RED_B5

RED_B4

RED_ODD3

RED_ODD2

RED_B2

RED_B3

RED_ODD1

RED_ODD0

RED_B1

RED_B0

8

7

6

5

4

3

2

1

9

10

11

12

13

14

15

16

9

10

11

12

13

14

15

16

9

10

11

12

13

14

15

16

RED_A7

RED_A6

RED_A5

RED_A4

RED_A3

RED_A2

RED_A1

RED_A0

GRN_A7

GRN_A6

GRN_A5

GRN_A4

GRN_A3

GRN_A2

GRN_A1

GRN_A0

BLU_A7

BLU_A6

BLU_A5

BLU_A4

BLU_A3

BLU_A2

BLU_A1

BLU_A0

EACH CORNER OF THE PCB

PLACE MOUNTING HOLES IN

22

RA6

8

7

6

5

4

3

2

1

RA3

GRN_ODD7

GRN_ODD6

GRN_ODD5

GRN_ODD4

GRN_ODD3

GRN_ODD2

GRN_ODD1

GRN_ODD0

22

GRN_B7

GRN_B6

GRN_B5

GRN_B4

GRN_B3

GRN_B2

GRN_B1

GRN_B0

22

9

10

11

12

13

14

15

16

RA5

8

7

BLU_ODD6 BLU_ODD7

6

5

BLU_ODD4 BLU_ODD5

4

BLU_ODD3

3

2

BLU_ODD1 BLU_ODD2

1

BLU_ODD0

RA2

BLU_B7

BLU_B6

BLU_B5

BLU_B4

BLU_B3

BLU_B2

BLU_B1

BLU_B0

22

9

10

11

12

13

14

15

16

22

RA1 PLACE U10 AS CLOSE AS POSSIBLE TO U6

PANEL_CLK_OUT

PLACE NEAR W23 R20 0⍀ PANEL_CLK_OUT2

KEEP THESE TRACES AS SHORT AS POSSIBLE

1 IN

U10

OUT9

OUT8

OUT7

OUT6

OUT5

OUT4

OUT3

OUT2

OUT1

OUT10

3D7110

3.3V: 14

REV. 0

BLU_EVEN0

OUT6

5

8

9

6

W22 OUT789

W25 OUT456

W24 OUT123

PANEL_CLK_IN

PLACE NEAR U6-187

PLACE NEAR TP1

OUT10

OUT9

OUT8

OUT7

OUT5

11

10

OUT3 OUT4

4

OUT2

3 12

OUT1

13

R14 22⍀

R22 0⍀

PANEL_CLK_IN_DLY2

PANEL_CLK

R15 22⍀

PANEL_CLK_IN_DLY

PLACE NEAR W23

W23

HERE IS A STUFFING OPTION.

THE CLOCK DELAY CIRCUIT SHOWN

EVAL-AD988xEB

PANEL_CLK

DE_OUT

REGEN_VS

REGEN_HS

3.3V

AVDD

DVI_LVDS~_SEL

80

78

77

76

[9:16]

[90:97]

RED_A[7:0]

BLU_A[7:0]

[68:75]

BLU_B[7:0]

[99:100],[1:6]

[58:65]

GRN_B[7:0]

GRN_A[7:0]

[48:55]

RED_B[7:0]

R8 510

R7 4.75k

R3 4.75k

IDCK

DE

VSYNC

HSYNC

BE[7:0]

GE[7:0]

RE[7:0]

BO[7:0]

GO[7:0]

RO[7:0]

IVCC2

IVCC3

98 IVCC4

81 EDGE 24

GND:47,57,67,79,86,89

GND:7,19,31,33,37,41

3.3V:8,30,56,88

U15

SiI160

AVDD

IVCC1

44 AVCC3

38 AVCC2

66 PIXS 25

AVCC1

17 PD 26

EXT_SWING 32

5

6 74VHC14

U9

CTL1

85 PVCC2

18 PVCC1

36 CTL3 82

CTL2 83

–6– 84

3.3V

20

21

22

23

27

28

29

87

34

3.3V

DVI_TXC–

DVI_TXC+

DVI_TX0–

35

DVI_TX0+

39

DVI_TX1–

42 40

DVI_TX1+

DVI_TX2–

DVI_TX2+

43

45

46

LVDS_EN

RES1

RES2

RES3

RES4

RES5

RES6

RES7

RES8

TXC–

TXC+

TX0–

TX0+

TX1–

TX1+

TX2–

TX2+

DVI_PVCC

GND:3,11,15,19,22 (VIEW FROM THE BOTTOM)

23 RXC+ 24 RXC–

18 RX0+ 17 RX0–

10 RX1+ 9 RX1–

2 RX2+ 1 RX2–

7 DDCSDA 6 DDCSCL

25 HSYC 8 VSYC

26 RED 27 GREEN 28 BLUE

DVI_AD J8

EVAL-AD988xEB

Figure 5. Schematics—3

REV. 0

GRN_A0

GRN_A1

GRN_A2 100

GRN_A3 99

GRN_A4 96

GRN_A5 95

GRN_A6 94

GRN_A7 93

BLU_A0 92

BLU_A1 91

BLU_A2 90

BLU_A3 89

BLU_A4 88

BLU_A5 87

BLU_A6 86

BLU_A7 85

RED_B0 84

RED_B1 81

RED_B2 80

RED_B3 79

G12

G13

G14

G15

G16

G17

B10

B11

B12

B13

B14

B15

B16

B17

R20

R21

R22

R23

R24

R25

3.3V:53,67,82,97 LVPLL_VCC:12,18 LVDS_VCC:30,40,48

G20

R27 LVDS_EN

PANEL_CLK

DE_OUT

REGEN_VS

GND:13,16,17,19,25,35,51,52,43,68,83,98

DS90C387

U5

3 RED_A7

RED_B4 78

4 RED_A6

R15 5 RED_A5

R14 6 RED_A4

R13 7

R12

–7– RED_A3

Figure 6. Schematics—4 8

75 G21 RED_A2

74 R11

GRN_B0 G22 9

73 RED_A1

GRN_B1 G23 10

GRN_B2 G24 RED_A0

72 R10

GRN_B3 CLKIN

71 G25 11

GRN_B4 G26 PRE

70 G27 14

R26

GRN_B5

RED_B5 77

69

RED_B6 76

GRN_B6 B20 PRE

RED_B7 66 B21 15

FROM FPGA GRN_B7

G11

65 B22

1

BLU_B0

G10

64 B23

2

BLU_B1

R17

63

R16

BLU_B2 PLLSEL

62 R_FB

BLU_B3 B24 20

61 B25 R_FB

BLU_B4 R_FDE

60 21

BLU_B5 B26 R_FDE

59 PD

BLU_B6 B27 22

58 A7P

A7M

A6P

A6M

A5P

A5M

A4P

A4M

A3P

A3M

CLK1P

CLK1M

A2P

A2M

A1P

A1M

AOP

AOM

CLK2P/NC

CLK2M/NC

23

BLU_B7 DE DUAL

REV. 0 57 VSYNC 24

56 HSYNC BAL

55 DUAL

54 BAL

REGEN_HS

TXOUT5– TXOUT5+ TXOUT6– TXOUT6+ TXOUT7– TXOUT7+

34 33 32 31 29 28

R27 4.75k⍀

R23 4.75k⍀

R24 4.75k⍀

R25 4.75k⍀

R26 4.75k⍀

26

27

TXOUT4+

TXOUT4–

TXOUT3+

TXOUT3–

TXOUTCLK+

TXOUTCLK–

TXOUT2+

TXOUT2–

TXOUT1+

TXOUT1–

TXOUT0+

TXOUT0–

36

37

38

39

41

42

44

45

46

47

49

50

3.3V

9

7

5

3

1

31

29

27

TXOUT7– 25

23

TXOUT6– 21

TXOUT5– 19

TXOUT4– 17

15

TXOUT3– 13

TXOUTCLK– 11

TXOUT2–

TXOUT1–

TXOUT0–

8

6

4

2

30

28

26

24

22

20

18

16

14

12

10

FI-WE31P-HF J9

31

29

27

25

23

21

19

17

15

13

11

9

7

5

3

1

30

28

26

24

22

20

18

16

14

12

10

8

6

4

2

LVDS OUTPUT CONNECTOR

TXOUT7+

TXOUT6+

TXOUT5+

TXOUT4+

TXOUT3+

TXOUTCLK+

TXOUT2+

TXOUT1+

TXOUT0+

EVAL-AD988xEB

PLLVDD

PLLVDD

46

38

R34 392⍀

PORT2B[9:2]

LPF

DIV1

DIV0

31 32 PORT2B1 PORT2B0

DAC_DIV1

C8 1␮F

PORT1B[9:2]

CLK–

CLK+

RST

15 16 PORT1B1 PORT1B0

3

2

1

37

[23:30]

GRN_B[7:0]

LPF

DIV1

DIV0

R45 4.75k⍀

DAC_DIV0

[7:14]

GRN_A[7:0]

PANEL_CLK

R44 4.75k⍀

46

38

R28 392⍀

37

C9 1␮F

PORT2B[9:2]

31 32 PORT2B1 PORT2B0

DAC_DIV1

[23:30]

RED_B[7:0]

PORT1B[9:2]

CLK–

CLK+

15 16 PORT1B1 PORT1B0

3

2

DAC_DIV0

[7:14]

RED_A[7:0]

PANEL_CLK

RST

48

1

48 CLKVDD CLKVDD

R29 4.75k⍀

U11

AD9751

PLLVDD

CLKVDD

GND:4,22,44,45

U12

AD9751

GND:4,22,44,45

47

AVDD

AVDD

DVDD2

R30 4.75k⍀

41

REFIO

FSADJ

IOUTB

IOUTA

PLLLOCK

3.3V

REFIO

FSADJ

IOUTB

IOUTA

PLLLOCK

3.3V

R31 2k⍀

GFSADJ

GOUT–

C6 0.1␮F

R35 2k⍀

GPLL_LOCK

C5 0.1␮F

RREF

RFSADJ

ROUT–

RPLL_LOCK

39 GREF

40

42

43

6

39

40

42

43

6

1

1

R36 37.4⍀

TP3

R32 37.4⍀

TP1

PLLVDD

R37 75⍀

AGRN_OUT

R33 75⍀

ARED_OUT

PORT2B[9:2]

REGEN_HS

REGEN_VS

15

14

13

12

11

10

9

8

7

6

5

4 ARED_OUT

3

2

1

J6

GND:4,22,44,45

U13

AD9751

AGRN_OUT

LPF

DIV1

PLLVDD

CLKVDD

ABLU_OUT

46

38

DIV0

31 PORT2B1 32 PORT2B0

DAC_DIV1 C10 1␮F

PORT1B[9:2]

CLK–

CLK+

RST

15 PORT1B1 16 PORT1B0

37

R38 392⍀

[23:30]

[7:14]

3

2

1

R43 4.75k⍀

DAC_DIV0

BLU_B[7:0]

BLU_A[7:0]

PANEL_CLK

R42 4.75k⍀

48 CLKVDD

47 PLLVDD PLLVDD

47 PLLVDD

41 AVDD AVDD

41 AVDD

5 5

AVDD

5 DVDD2

21 21

DVDD1 DVDD1

–8– DVDD2

21 DVDD1 CON-HD-15HM

PLLVDD

39

40

42

43

6

C7 0.1␮F

BREF

BFSADJ

R39 2k⍀

BPLL_LOCK

BOUT–

ANALOG OUTPUT

REFIO

FSADJ

IOUTB

IOUTA

PLLLOCK

3.3V

1

R40 37.4⍀

TP4

R41 75⍀

ABLU_OUT

EVAL-AD988xEB

Figure 7. Schematics—5

REV. 0

SERIAL INTERFACE CIRCUIT

[10:18]

G19

3 W17

2

P1

G21

1

2

3

4

5

6

31

32

FSDA_USB

3 W18

2

R46 2k⍀

3

4

1

1

3 W19

2

2 74VHC14

U9

1

STROBE FROM PC

74VHC14

U9

SER_CLK

SER_DAT

SER_EN

3 W20

SELECT PARALLEL: STRAPS BETWEEN PINS 1 AND 2

SELECT USB: STRAPS BETWEEN PINS 2 AND 3

2 1

SCL_USB

4Q

4D

FSEN

FSDA

FSCL

2

U1

EN

1D

2D

3D

4D

5D

6D

7D

8D

C1

SDA

1

LCX16374A

U1

EN

1D

SCL

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

1Q

2Q

5Q

5D

2D

6Q

6D

3Q

7Q

7D

3D

8Q

8D

3 W21

1

47

46

44

43

41

40

38

37

48

24

36

35

33

32

30

29

27

2

3

5

6

8

9

11

12

13

14

16

17

19

20

22

23

R5 2k⍀

SEN_PAR

X2 12MHZ CRYSTAL

SCL_PAR

R19 2k⍀

3.3V

SDA_PAR

NOTE: PLACE W17–W21 IN A ROW AND ADD THIS TEXT TO THE SILKSCREEN

R18 2k⍀

3.3V

XOUT

22pF

J2

22pF

3.3V

4

3

2

1

AVDD

USB_A

GND

+DATA

–DATA

PWR_IN

C102

GND:5,6

XIN

C101

2

SOFTWARE INTERFACE SELECTION USING W17–W21:

1

3.3V

P2

G20

P3

P4

G24

G22

P5

G25

G23

P6

P31

P32

G26

G27

G28

G29

36CRPX J1

19

20

21

22

23

24

25

26

27

28

29

G30

FSEN_USB

26

3.3V:7,18,31,42

30

SEN_PAR

R17 2k⍀

FSCL_USB

C1

SCL_PAR

CENTRONICS 36 PIN PRINTER PORT CONNECTOR [33:36]

SDA_PAR

R21 2k⍀

SCL_PAR

11

10

9

8

7

6

5

4

3

2

1

C11 1
F

R49 10k⍀

VCC

AVCC

XOUT

XIN

AGND

GND4

GND3

GND2

GND1

CLK24

GND

R47 24.3⍀

R51 1.5k⍀

42

SERIAL DATA TO PC

SDA_USB

R48 24.3⍀

40

LCX16374A

39

41

U14

3.3V

R50 4.75k⍀

AN2126SC

FSCL_USB

FSDA_USB

FSEN_USB

USB AND SERIAL INTERFACE

GND5

GND6

D0

D1

D2

D3

D4

D5

D6

D7

BKPT

VCC2

R16 4.75k⍀

34

25

RESET

44 VCC3 12

43 DISCON# 13

3–STATE DATA LINE

XTAL2

USBRST

USBD+ PC0/RXD0 14

USBD– PC1/TXD0 15

PA5/FRD# PC2/INT0# 16

PA4/FWR# PC3/INT1# 17

37 WAKEUP# PC5/T1

36 SCL PC6/WR#

35 SDA PC7/RD#

38 GND8 PC4/T0 18

–9–

19

Figure 8. Schematics—6 XTAL1

20

1

21

GND7 VCC1

REV. 0 22

3.3V

23

24

25

26

27

28

29

30

31

32

33

8 VCC 7 WP 6 SCL 5 SDA

SDA_USB

SCL_USB

U16 24LCO4B

1 A0 2 A1 3 A2 4 VSS

EVAL-AD988xEB

SDA_PAR

2

J4

C14 0.1F

+

+

+

–10–

3.3V

C1 10F

C26 10F

C2 10F

3

3

3

VOUT

VOUT

2

2

3

2

1

VCC1

GND

SRT

VCC

RST

U4 LP3470

POWER-ON RESET

1

GND

VOUT

U7 5V LM1085IT

1

GND

VIN

VIN

2

U3 2.5V LM1086CS

1

GND

VIN

U8 LM1085IT 3.3V

4

5

+

+

1

2

C3 10F

5V

C27 10F

R4 10k

C4 10F

2.5V

+

RST

C32 0.1F

C15 0.1F

C23 0.1F

C24 0.1F

C32 0.1F

J5

SMB LM

C20 0.1F

1

2

1

2

C19 0.1F

1

2

R9 50

W13

EXTERNAL CLOCK

LATCH_DE

LATCH_DE

C22 0.1F

CR2

HSMS-2814

CR1

HSMS-2814

C18 0.1F

3

3

C17 0.1F

C32 1F

C33 1F

C25 0.1F

1

2

1

2

R1 10k

DE_DETECT2

R2 10k

DE_DETECT1

DVI TRANSMITTER

FOR DACS AND

ANALOG SUPPLY C61 0.1F

C69 0.1F

C64 0.1F

C56 0.1F

LVDS PLL SUPPLY

LVDS SUPPLY

DVI PLL SUPPLY

DAC PLL SUPPLY

C62 0.1F

C63 0.1F

C41 0.1F

C100 0.1F

C42 0.1F

C94 0.1F

C12 0.1F

C93 0.1F

C47 0.1F

C92 0.1F

C46 0.1F

C91 0.1F

C45 0.1F

C90 0.1F

C48 0.1F

C89 0.1F

C44 0.1F

C88 0.1F

C37 0.1F

C87 0.1F

C43 0.1F

C86 0.1F

C39 0.1F

C85 0.1F

C40 0.1F

C84 0.1F

C13 0.1F

C83 0.1F

C30 0.1F

C82 0.1F

C29 0.1F

C81 0.1F

C31 0.1F

C80 0.1F

C35 0.1F

C79 0.1F

C36 0.1F

C78 0.1F

C28 0.1F

C77 0.1F

C16 0.1F

C76 0.1F

C34 0.1F

C74 0.1F

C72 0.1F

C66 0.1F

C68 0.1F

C60 0.1F

C57 0.1F

+ C75 0.1F

C71 0.1F

C67 0.1F

C70 0.1F

C65 0.1F

C58 0.1F

C51 10F

DVI_PVCC

C50 10F

PLLVDD

C49 10F

AVDD

C55 0.1F

C52 10F

C53 10F

FB1

C54 0.1F

1

FB3

1

FB2 1

FB5 1

1 100MHz

FB4

100MHz

2

100MHz

2

100MHz

2

100MHz

2

LVPLL_VCC 2

+ C73 0.1F

LVDS_VCC

+

+

+

C59 0.1F

C97 0.1F

C99 0.1F

C98 0.1F

C96 0.1F

C95 0.1F

EVAL-AD988xEB

Figure 9. Schematics—7

REV. 0

EVAL-AD988xEB

Figure 10. Evaluation Board—1

REV. 0

–11–

EVAL-AD988xEB

Figure 11. Evaluation Board—2

–12–

REV. 0

EVAL-AD988xEB

Figure 12. Evaluation Board—3

REV. 0

–13–

EVAL-AD988xEB

Figure 13. Evaluation Board—4

–14–

REV. 0

EVAL-AD988xEB Bill of Materials REV A26 L/I QTY REFERENCE DESIGNATION DESCRIPTION 1 11 C1–C4, C26, C27, C49–C53 10
F, 16 V, TANT CAP ‘C’ 2 84 C5–C7, C12–25, C28–31, 0.1
F 25 V 0805 X7R C34–C48, C54–C100, C103 3 6 C8–C11, C32, C33 1.0
F 16 V 0805 Y5V 4 2 C101, C102 22 pF 50 V 0805 NPO 5 2 CR1, CR2 Dual Schottky Diode SOT-23 6 5 FB1-5 Bead Core SMD 45  7 1 J1 36-pin Conn, Centronix 8 1 J2 USB Connector Type B 9 1 J3 80-pin Dual-Row Recept SMD 10 1 J4 Power Supply Terminal 11 1 J5 NOT INSTALLED 12 1 J6 15-pin D-SUB Connector 13 1 J7 Header 2"  5.1" Space 14 1 J8 DVI (TMDS) Connector 15 1 J9 LVDS Connector 16 3 R1, R2, R49 10.0 k 0805 1% 17 12 R3, R7, R23–R25, R27, R29, R30, 4.75 k 0805 1% R42–R45 18 9 R5, R17–R19, R21, R31, R35, R39, 2.00 k 0805 1% R46 19 6 R4, R6, R10–R13 1.00 k 0805 1% 20 1 R8 511  0805 1% 21 1 R9 NOT INSTALLED 22 1 R15 NOT INSTALLED 23 1 R14 22.1  0805 1% 24 2 R16, R50 2.21 k 0805 1% 25 2 R20, R22 NOT INSTALLED 26 3 R28, R34, R38 392  0805 1% 27 3 R32, R36, R40 37.4  0805 1% 28 3 R33, R37, R41 75.0  0805 1% 29 2 R47, R48 24.3  0805 1% 30 1 R51 1.50 k 0805 1% 31 6 RA1-6 22  RPAK 8RES 32 1 U1 IC, BUFFER 33 1 U2 IC, EEPROM 34 1 U3 IC, V REG 35 1 U4 IC, PUR 36 1 U5 IC, LVDS XMITTER 37 1 U6 IC, FPLD 38 1 U7 IC, V REG 39 1 U8 IC, V REG 40 1 U9 IC, INVERTER 41 1 U10 NOT INSTALLED 42 3 U11–U13 IC, DAC 43 1 U14 IC, USB CONTROLLER 44 1 U15 IC, DVI XMITTER 45 1 U16 IC, EEPROM 46 8 W3, W15–W21 3-PIN HEADER 47 2 W12, W14 NOT INSTALLED 48 11 W2, W7–W11, W13, W22–W25 NOT INSTALLED 49 1 X2 12 MHz Crystal SMD 50 1 N/A PC BOARD 51 4 N/A (for corners of board) 1/2" STANDOFF 4-40 52 4 N/A 4-40 NUT FOR ABOVE 53 1 N/A (for slotted hole in board) 3/8" NYLON POST 54 1 N/A 6-32  3/8" SCREW 55 4 N/A #6 WASHER (Stacked) 56 2 N/A (for J1) #4 SELF-TAPPING SCREW 57 2 N/A (for J6) 4-40  3/8" SCREW 58 2 N/A 4-40 NUT FOR ABOVE 59 2 N/A (for U7 and U8) 6-32  3/8" SCREW 60 2 N/A 6-32 NUT FOR ABOVE NOTES 1. Install bare wire jumper between TP2 and TP7 on the TOP side of the board. 2. Rev A24 to A25: do not populate R24 and R26 3. Rev A25 to A26: populate R24 and change 4. L/I 1 PN to Digikey PCT3106CT-ND

REV. 0

PART # ECS-T1CX106R ECJ-2VB1E104K

MFR PANASONIC PANASONIC

VENDOR DIGIKEY DIGIKEY

VENDOR PART # PCT3106CT-ND PCC1828CT-ND

SUB Y Y

ECJ-2VF1C105Z ECJ-2VC1H220J HSMS-2814 EXC-CL3225U1 552742-1 897-30-004-90-000000 147378-7 RAPC722

PANASONIC PANASONIC AGILENT PANASONIC AMP MILL-MAX AMP SWITCHCRAFT

DIGIKEY DIGIKEY NEWARK DIGIKEY ARROW DIGIKEY TIGER DIGIKEY

PCC1849CT-ND PCC220CNCT-ND 83F8840 P9811CT-ND 552742-1 ED90003-ND 147378-7 SC1153-ND

Y Y N N Y N N N

181-015-212-171 2310-6121TG 74320-1004 FI-WE31P-HF ERJ-6ENF1002V ERJ-6ENF4751V

NORCOMP 3M MOLEX JAE PANASONIC PANASONIC

DIGIKEY POWELL ARROW REPTRON DIGIKEY DIGIKEY

815RF-ND 2310-6121TG 74320-1004 FI-WE31P-HF P10.0KCCT-ND P4.75KCCT-ND

N Y N N Y Y

ERJ-6ENF2001V

PANASONIC

DIGIKEY

P2.00KCCT-ND

Y

ERJ-6ENF1001V ERJ-6ENF5110V ERJ-6ENF49R9V ERJ-6ENF22R1V ERJ-6ENF22R1V ERJ-6ENF2211V RM73Z2A000 ERJ-6ENF3920V ERJ-6ENF37R4V ERJ-6ENF75R0V ERJ-6ENF24R3V ERJ-6ENF1501V 742C163220J 74LCX16374MTD AT17LV512A-10JC LM1086CS-2.5 LP3470IM5-2.63 DS90C387VJD EP1K10QC208-1 LM1085IT-5.0 LM1085IT-3.3 74VHC14 3D7110D-1 AD9751AST AN2136SC SiI160CT100 24LC04B/SN 3/40 X 2340-6111TN 1-PIN HEADER

PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC KOA PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC CTS FAIRCHILD ATMEL NATIONAL NATIONAL NATIONAL ALTERA NATIONAL NATIONAL FAIRCHILD DATA DELAY DEV ADI CYPRESS SILICON IMAGE MICROCHIP TECH 3M 3M

DIGIKEY DIGIKEY DIGIKEY DIGIKEY DIGIKEY DIGIKEY GARRETT DIGIKEY DIGIKEY DIGIKEY DIGIKEY DIGIKEY DIGIKEY ARROW ARROW ARROW ARROW DIGIKEY ARROW ARROW ARROW DIGIKEY TIGER ADI ARROW ALL AMER DIGIKEY MOUSER MOUSER

P1.00KCCT-ND P511CCT-ND P49.9CCT-ND P22.1CCT-ND P22.1CCT-ND P2.21KCCT-ND RM73Z2A000 P392CCT-ND P37.4CCT-ND P75.0CCT-ND P24.3CCT-ND P1.50KCCT-ND 742C163220JCT-ND 74LCX16374MTD AT17LV512A-10JC LM1086CS -2.5 LP3470IM5-2.63 DS90C387VJD-ND EP1K10QC208-1 LM1085IT-5.0 LM1085IT-3.3 74VHC14-ND 3D7110D-1 AD9751AST AN2136SC SiI160CT100 24LC04B/SN-ND 2340-6111TN 2340-6111TN

Y Y

Y Y Y Y Y Y Y N N N N N N N Y

MA-505-12.000M-C0 GSO4477

EPSON ADI SPC SPC RICHCO SPC SPC SPC

DIGIKEY PCSM NEWARK NEWARK ALLIED NEWARK NEWARK NEWARK JAMECO NEWARK NEWARK NEWARK

SE2507CT-ND GSO4477 93N2192 31F2106 911-3058 31F2198 31F2139 30F092 40969 31F2106 31F2198 31F2107

N N Y Y Y Y Y Y Y Y Y Y

TCBS-6-01

SPC SPC SPC

–15–

Y Y

N N N N Y

EVAL-AD988xEB PART # ECS-T1CX106R ECJ-2VB1E104K

MFR PANASONIC PANASONIC

VENDOR DIGIKEY DIGIKEY

VENDOR PART # PCT3106CT-ND PCC1828CT-ND

SUB Y Y

ECJ-2VF1C105Z ECJ-2VC1H220J HSMS-2814 LN1371SGTR EXC-CL3225U1 552742-1 897-30-004-90-000000 147378-7 RAPC722

PANASONIC PANASONIC AGILENT PANASONIC PANASONIC AMP MILL-MAX AMP SWITCHCRAFT

DIGIKEY DIGIKEY NEWARK DIGIKEY DIGIKEY ARROW DIGIKEY TIGER DIGIKEY

PCC1849CT-ND PCC220CNCT-ND 83F8840 P516CT-ND P9811CT-ND 552742-1 ED90003-ND 147378-7 SC1153-ND

Y Y N Y N Y N N N

181-015-212-171 87215-7 74320-1004 FI-WE31P-HF ERJ-6ENF1002V ERJ-6ENF4751V ERJ-6ENF2001V

NORCOMP AMP MOLEX JAE PANASONIC PANASONIC PANASONIC

DIGIKEY DIGIKEY ARROW TIGER DIGIKEY DIGIKEY DIGIKEY

815RF-ND A26580-ND 74320-1004 FI-WE31P-HF P10.0KCCT-ND P4.75KCCT-ND P2.00KCCT-ND

N Y N N Y Y Y

ERJ-6ENF1001V ERJ-6ENF5110V ERJ-6ENF49R9V ERJ-6ENF22R1V ERJ-6ENF22R1V ERJ-6ENF2211V RM73Z2A000 ERJ-6ENF3920V ERJ-6ENF37R4V ERJ-6ENF75R0V ERJ-6ENF24R3V ERJ-6ENF1501V 742C163220J 74LCX16374MTD AT17LV512A-10JC LM1086CS-2.5 LP3470IM5-2.63 DS90C387VJD EP1K10QC208-1 LM1085IT-5.0 LM1085IT-3.3 74VHC14 3D7110D-1 AD9751AST AN2136SC SIL160CT100 24LC04B/SN 3/40 X 2340-6111TN

PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC KOA PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC CTS FAIRCHILD ATMEL NATIONAL NATIONAL NATIONAL ALTERA NATIONAL NATIONAL FAIRCHILD DATA DELAY DEV ADI CYPRESS SILICON IMAGE MICROCHIP TECH 3M

DIGIKEY DIGIKEY DIGIKEY DIGIKEY DIGIKEY DIGIKEY GARRETT DIGIKEY DIGIKEY DIGIKEY DIGIKEY DIGIKEY DIGIKEY ARROW ARROW ARROW ARROW DIGIKEY ARROW ARROW ARROW DIGIKEY TIGER ADI ARROW ALL AMER DIGIKEY MOUSER

P1.00KCCT-ND P511CCT-ND P49.9CCT-ND P22.1CCT-ND P22.1CCT-ND P2.21KCCT-ND RM73Z2A000 P392CCT-ND P37.4CCT-ND P75.0CCT-ND P24.3CCT-ND P1.50KCCT-ND 742C163220JCT-ND 74LCX16374MTD AT17LV512A-10JC LM1086CS -2.5 LP3470IM5-2.63 DS90C387VJD-ND EP1K10QC208-1 LM1085IT-5.0 LM1085IT-3.3 74VHC14-ND 3D7110D-1 AD9751AST AN2136SC SIL160CT100 24LC04B/SN-ND 2340-6111TN

Y Y

MA-505-12.000M-C0 GSO4477B

EPSON ADI SPC SPC EAGLE EAGLE KEYSTONE SPC

DIGIKEY PCSM NEWARK NEWARK MOUSER MOUSER MOUSER NEWARK JAMECO NEWARK NEWARK NEWARK

SE2507CT-ND GSO4477Rev B 93N2192 31F2106 561-FTP500 561-T0832037 534-3372 30F092 40969 31F2106 31F2198 31F2107

SPC SPC SPC

–16–

Y Y Y Y Y Y Y Y Y N N N N N N N Y N N N N Y N N Y Y Y Y Y Y Y Y Y Y

REV. 0

C03646–0–5/03(0)

Bill of Materials REV A3 L/I QTY REFERENCE DESIGNATION DESCRIPTION 1 11 C1–C4, C26, C27, C49–C53 10
F, 16 V, TANT CAP ‘C’ 2 83 C5–C7, C12–C25, C28–C31, 0.1
F 25 V 0805 X7R C34–C48, C54–C100 3 6 C8–C11, C32, C33 1.0
F 16 V 0805 Y5V 4 2 C101, C102 22 pF 50 V 0805 NPO 5 2 CR1, CR2 Dual Schottky Diode SOT-23 6 2 D1, D2 Green LED 0603 7 5 FB1-5 Bead Core SMD 45  8 1 J1 36-pin Conn, Centronix 9 1 J2 USB Connector Type B 10 1 J3 80-pin Dual-Row Recept SMD 11 1 J4 Power Supply Terminal 12 1 J5 NOT INSTALLED 13 1 J6 15-pin D-SUB Connector 14 1 J7 1/4 Dual-Row Header (5) .1" 15 1 J8 DVI (TMDS) Connector 16 1 J9 LVDS Connector 17 3 R1, R2, R49 10.0 k 0805 1% 18 13 R3, R7, R23–R27, R29, R30, R42–R45 4.75 k 0805 1% 19 9 R5, R17–R19, R21, R31, R35, R39, 2.00 k 0805 1% R46 20 8 R4, R6, R10–R13, R52, R53 1.00 k 0805 1% 21 1 R8 511  0805 1% 22 1 R9 NOT INSTALLED 23 1 R15 NOT INSTALLED 24 1 R14 22.1  0805 1% 25 2 R16, R50 2.21 k 0805 1% 26 2 R20, R22 NOT INSTALLED 27 3 R28, R34, R38 392  0805 1% 28 3 R32, R36, R40 37.4  0805 1% 29 3 R33, R37, R41 75.0  0805 1% 30 2 R47, R48 24.3  0805 1% 31 1 R51 1.50 k 0805 1% 32 6 RA1-6 22  RPAK 8RES 33 1 U1 IC, BUFFER 34 1 U2 IC, EEPROM 35 1 U3 IC, V REG 36 1 U4 IC, PUR 37 1 U5 IC, LVDS XMITTER 38 1 U6 IC, FPLD 39 1 U7 IC, V REG 40 1 U8 IC, V REG 41 1 U9 IC, INVERTER 42 1 U10 NOT INSTALLED 43 3 U11–U13 IC, DAC 44 1 U14 IC, USB CONTROLLER 45 1 U15 IC, DVI XMITTER 46 1 U16 IC, EEPROM 47 8 W3, W15–W21 3-PIN HEADER 48 13 W2, W7–W14, W22–W25 NOT INSTALLED 49 1 X2 12 MHz Crystal SMD 50 1 N/A PC BOARD 51 4 N/A (for corners of board) 1/2" STANDOFF 4-40 52 4 N/A 4-40 NUT FOR ABOVE 53 1 N/A (for slotted hole in board) 1/2 THREADED NYLON POST 54 1 N/A 8-32  3/8" THUMBSCREW 55 1 N/A #8 FIBER WASHER 56 2 N/A (for J1) #4 SELF-TAPPING SCREW 57 2 N/A (for J6) 4-40  3/8" SCREW 58 2 N/A 4-40 NUT FOR ABOVE 59 2 N/A (for U7 and U8) 6-32  3/8" SCREW 60 2 N/A 6-32 NUT FOR ABOVE NOTES 1. Install bare wire jumper between TP2 and TP7 on the TOP side of the board. 2. Header Jumpers - Jameco #152670