Nano probing case studies and ‚advanced' transistor ... - eufanet

Jun 19, 2013 - Standard (SRAM) transistor characterization (case study) ... Samples with high topography (different layers) can easily be measured. ▫ Shorts ...
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Nano probing case studies and ‚advanced’ transistor characterization Peter Egger, Markus Grützner, Christian Hollerith, Sebastien Meziere Infineon AG, Failure Analysis Munich

Outline  Motivation and introduction  Atomic force probing versus SEM based nano probing  Case study SEM based nano probing  Standard (SRAM) transistor characterization (case study)  Advanced transistor characterization  Tunneling current  2nd. order transistor effects  Outlook and conclusion

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SEM-based Probing Strengths:  Samples with high topography (different layers) can easily be measured  Shorts between probes can be excluded by optical inspection  Electrical measurements at high or low temp (-20°…+120°C)  Probing on fast oxidizing metal lines (Cu, Al)  Active voltage contrast Applications:  Test structures (drawback: beam shift limitation!)  Characterization of complex logic gates  Measurements of metal interconnects (open Via?) But:  risk of e-beam radiation damage!

19.06.2013

Atomic Force Probing Strengths:  No influence of electron beam on transistor characteristics  Current imaging gives more detailed information than passive voltage contrast

Applications:  Preferred method for measurements on contact level  Transistor characterization  Inspection for leaky gates / diodes  2nd order transistor parameters  Characterization of gate oxides (tunneling current)

19.06.2013

Nano probing using SEM based systems – risk of ebeam radiation damage 1,0E-03

1E-4

1,0E-04 1E-5

0min 10min 20min 5min

1E-6

1,0E-05

SRAM NMOS transitor

I/A

1E-7

1E-8

1,0E-06 1,0E-07 1,0E-08 1,0E-09

1E-9

1,0E-10

1E-10

1,0E-11 1E-11 -0,6

-0,4

-0,2

0,0

0,2

0,4

0,6

0,8

1,0

1,2

1,0E-12

1,4

-0,6 -0,4 -0,2 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6

U/V

SEM based system 1kV acceleration voltage

AFM based system

-6

2,0x10

0,0E+00

0,0 -6

-2,0x10

0min 3min 10min 15min

-6

-4,0x10

I/A

-6

-6,0x10

-5,0E-06 -1,0E-05

-6

-8,0x10

SRAM PMOS transitor

-5

-1,0x10

-5

-1,2x10

-5

-1,4x10

-1,5E-05 -2,0E-05

-5

-1,6x10

-1,2

-1,0

-0,8

-0,6

Ugate / V

-0,4

-0,2

0,0

-2,5E-05 -1,40

-1,20

-1,00

-0,80

-0,60

-0,40

-0,20

0,00

Influence of ebeam on device characteristic: increase of I_off on NMOS and decrease I_on on PMOS devices Set date

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2,5E-05

1E-08

2,0E-05

1E-09

1,5E-05 1,0E-05

I/A

I/A

Nano probing using SEM based systems – risk of ebeam damage

Ebeam=500eV

5,0E-06

Ebeam=500eV

1E-10 1E-11

0,0E+00

1E-12 0

20

40 t / min

60

80

0

20

40

60

80

100

t/min

2,5E-05 1E-08

Ebeam=1000eV

1E-09

1,5E-05

I/A

I/A

2,0E-05

1,0E-05

Ebeam=1000eV

5,0E-06

1E-10 1E-11 1E-12 0

0,0E+00 0

20

40 t / min

60

20

40

60

80

100

t / min

80

2,5E-05

1E-08 1E-09

1,5E-05

I/A

I/A

2,0E-05

1,0E-05

1E-11

Ebeam=1500eV

5,0E-06 0,0E+00 0

20

40 t / min

60

Ebeam=1500eV

1E-12 80

0

20

40

60

80

100

t / min

Ion vs. time of PMOS with different beam energies Set date

1E-10

Ioff vs. time of NMOS with different beam energies

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Nano probing using SEM based systems – risk of ebeam radiation damage

2,5E-05

2,5E-05

2,0E-05

2,0E-05

1,5E-05

1,5E-05

Thin oxide

e

I/A

 PMOS at 1.5kV with different oxide thicknesses

1,0E-05

1,0E-05

Thick oxide

5,0E-06

5,0E-06 0,0E+00

0,0E+00 0

10

20

30 t / min

40

50

60

0

20

40

60

t / min

 Ebeam radiation damage due to electrons unlikely (depth of penetration too low)  X-ray might damage transistor (depth of penetration approx. 1µm) but does not perfectly fit to measurement (no damage due to x-ray at 500V assumed) Set date

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Outline  Motivation and introduction  Atomic force probing versus SEM based nano probing  Case study SEM based nano probing  Standard (SRAM) transistor characterization (case study)  Advanced transistor characterization  Tunneling current  2nd. order transistor effects  Outlook and conclusion

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Case study SEM based probing - Analogue simulation of failing flip-flop  Analogue simulation lead to 3 different hypotheses:  Resistive drain contact at Ptrans118 (1)  Resistive source contact at Ptrans118 (2)  Resistive gate at Ptrans122 (3) (1) TRE

Simulation

9

(3)

Case study SEM based probing – verification of failure hypothesis  Sample preparation:  Deprocessing to Via1  Isolation of transistors with FIB

Results: – No confirmation of high resistance in drain or source contacts – No irregular transistor characteristics – No other defect

High resistive gate in PMOS is the only possible solution

TEM analysis 10

Outline  Motivation and introduction  Atomic force probing versus SEM based nano probing  Case study SEM based nano probing  Standard (SRAM) transistor characterization (case study)  Advanced transistor characterization  Tunneling current  2nd. order transistor effects  Outlook and conclusion

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Standard (SRAM) transistor characterization  Fixed analysis flow for transistor characterization available Nano probing: check for leakages Transfer characteristic of all cell transistors Output characteristic of all cell transistors Additional measurements? Generate physical failure hypothesis? Physical preparation Set date

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Standard (SRAM) transistor characterization  Typical (standard) measurement conditions  Check for leakages: ‘current imaging’ using +/- 1V and +/0.5V bias  NMOS: Vdrain = Vnom, Vgate = -0.5V … Vnom; Vsource = 0V; Vbulk = 0V  PMOS: Vdrain = 0V, Vgate = -0.5V … Vnom; Vsource = Vnom; Vbulk = Vnom  To avoid artifacts due to contact resistance: measure transistors in both directions (swap definition of source and drain)

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Standard (SRAM) transistor characterization – case study  Voltage dependent SRAM single cell fail (fail at Vmin only)  Characterization of all 6 SRAM transistors:  NMOS access

 PMOS pull-up

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Standard (SRAM) transistor characterization – case study  NMOS pull down

-> Significant mismatch NMOS pull down But:  Can this explain the electrical fail behavior of the SRAM @ Vmin only?  How can we generate a reliable physical failure hypothesis (and visualization of the root cause)? Set date

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Standard (SRAM) transistor characterization – root causes for Vt shift  GOX – thickness  measure tunneling current (if possible)  TEM  Gate depletion (looks electrically like too thick GOX)  surface parallel TEM – check poly grains

 Masking implantation (diffusion / Ldd)  measure diffusion – well diodes  TEM  Ionic contamination  try anneal Set date

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Masking due to Particle (asymmetric)

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Standard (SRAM) transistor characterization – case study One approach to get answers to the two open questions is simulation and specific nano probing measurements:  Explain the fail behavior of the SRAM macro using circuit simulation  Requires additional and more precise nano probing results for model generation  Reliable failure hypothesis  Additional nano probing to exclude possible failure root causes (measure tunneling current and calculate GOX thickness)  Parameter extraction for device simulation

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Outline  Motivation and introduction  Atomic force probing versus SEM based nano probing  Case study SEM based nano probing  Standard (SRAM) transistor characterization (case study)  Advanced transistor characterization  2nd. order transistor effects  tunneling current  Outlook and conclusion

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Advanced transistor characterization – add. measurements for model generation  Output characteristic with different bulk biasing

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Advanced transistor characterization – add. measurements for model generation  Transfer characteristic using different bulk biasing

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Add. measurements for reliable physical failure hypothesis – GOX characterization  Electrical characterization of the gate oxide thickness of a single transistor  Measurement of tunneling current of the MOS capacitor by nano probing (AFP or SEM-based prober)  One probe needle on gate contact, one on bulk  Measurement in accumulation mode (positive bias for pfet, negative for nfet)  Increase voltage from 0V until current is measurable (pA range)  Calculate current density for a given voltage (Itunnel / Achannel)  Calculate GOX thickness using a device simulation model (e.g. TCAD), roughly "1nm/Vbreak"  Good correlation with physical measurement on TEM cross sections Set date

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Add. measurements for reliable physical failure hypothesis – GOX characterization  Typical IV-curves (log scale): thin GOX, 2 different channel areas

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Add. measurements for reliable physical failure hypothesis – GOX characterization  Pfets with different GOX thickness (green curve = thin)

linear scale

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log scale

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Outlook and conclusion  Nano probing is an indispensable tool for probing