Lecture 16 6.976 Flat Panel Display Devices
Poly-Silicon Thin Film Transistors Outline • • • • •
a-Si TFT Device Models (contd from last time) p-Si Deposition Structural and Electrical Properties of p-Si p-Si Thin Film Transistor Device Structures p-Si Device Models
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References • • • • •
•
• • •
Amorphous and Microcrystalline Semmiconductor Devices—Optoelectronic Devices, Editor Jerzy Kanicki, Artech House, 1990 Polycrystalline Silicon for Integrated Circuits and Displays, Ted Kamims, Kluwer Academic Publishers, Second Edition, 1998 M. Shur and M. Hack, “Physics of amorphous silicon based alloy field effect transistors,” J. Appl. Phys. 55 (10), 15 May 1984, p. 3831. M. Shur, M. Hack and J. G. Shaw, “A new analytical model for amorphous silicon thin-film transistors,” J. Appl. Phys. 66 (7), 15 May 1989, p. 3371. Mark D. Jacunski et al., “Threshold voltage, field effect mobility, and gate-tochannel capacitance in polysilicon TFTs,” IEEE Transactions on Electron Devices, Vol. 43, No. 9, Sepetember 1996, p. 1433. J. Levinson, et al., “ Conductivity behavior in polycrystalline semiconductor thin film transistors, “ Journal of Applied Physics, Feb 1982, Vol. 53, No. 2, pp. 1193-1202 MRS Symposium Proceedings – several of them in the last few years ECS Proceedings of Symposia on Thin Film Transistor Technologies SPIE Proceedings on Display Technologies
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Why poly-silicon? • To integrate the row and data scanners on the display, higher performance transistors are required
Scan Line Scanners
Data Line Scanners
Integrated Driver AMLCD 6.976 Flat Panel Display Devices - Spring 2001
• A-Si TFTs have low performance because the field effect mobilities are low due to defects and grain boundaries • P-Si TFTs attain higher performance by reducing the number of defects and hence the number of grain boundaries through Grain Engineering!
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Electrical Properties of Amorphous Silicon • Basic crystal structure is absent in a-Si. • No well defined bandgap but a range of energies with few allowed states. • High densities of localized states near the edges of the bandagap • Effective bandgap ≈1.7 eV • Carriers do not readily move through the material in these localized states • Conduction occurs primarily by hopping conduction 6.976 Flat Panel Display Devices - Spring 2001
é æ To ö1 4 ù σ T = σ o exp ê− ç ÷ ú êë è T ø úû Lecture 16
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a:Si TFT Structure Glass Source/Drain Silicon Nitride Gate a-Si n+ a-Si Passivation Gate
n+ a-Si
(i) BCE
A. Top Gate
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(ii) CHP
B. Bottom Gate
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I-V Characteristics of a MOS Transistor Vds2 ù C ⋅ µ FET ⋅ W é I ds = ê(Vgs − Vt ) Vds − ú 2 L ë û
for Vds < (Vgs − Vt ) I ds =
Cµ FET ⋅ W (Vgs − Vt ) 2 2L
for Vds > (Vgs − Vt ) Where: C = Capacitance per unit area µFET = Mobility W= Channel Width L = Channel length
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Transfer Characteristics of an a-Si TFT 10-3 10-4 10-5
W / L = 12 Vd = 10 V µ = 1 Cm2/V.s Vt =1V
Drain Current (A)
10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 -20
-10
10
0
20
Gate Voltage (V) 6.976 Flat Panel Display Devices - Spring 2001
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Effect of “Localized” States
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Effect of Localized States
∞
Q gate = Cox VGS = Q induced = Q loc + Q mobile = q ò N locdx + qn s 0
Q loc = Q deep + Q tail 6.976 Flat Panel Display Devices - Spring 2001
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Field Effect Mobility
qn s µ FET = Q ind. µ0
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Field Effect Mobility and Charge Density
µ FET µn
é Vg − VT − αVDS ù =ê ú V AA û ë
Induced charge trapped in localized states 6.976 Flat Panel Display Devices - Spring 2001
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γ
Regimes of Operation 10-3 10-4 10-5
W / L = 12 Vd = 10 V µ = 1 Cm2/V.s Vt =1V
Above Threshold
Drain Current (A)
10-6 10-7 10-8
Below Threshold
10-9 10-10 10-11 10-12 10-13 10-14 -20
-10
0
10
20
Hole Induced Leakage Current
Gate Voltage (V) 6.976 Flat Panel Display Devices - Spring 2001
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a-Si TFT Technology Features • • • • • • •
Low temperature ( 650 ºC
• Deposition of a-Si at low temperature followed by solid phase re-crystallization at moderate temperatures – 500 ºC < T < 650 ºC
• Deposition of a-Si at low temperature followed by excimer laser re-crystallization
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a-Si and p-Si Deposition Reaction
Silane :
SiH 4 (g ) → Si(s) + 2H 2
Disilane : Si 2 H 6 (g ) → 2Si(s) + 3H 2 6.976 Flat Panel Display Devices - Spring 2001
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Surface Adsorption
Adsorbtion
Decomposition
SiH 4 + ∗ → SiH ∗4
SiH ∗4 + 4∗ → Si + 4H ∗
SiH 2 + ∗ → SiH ∗2
SiH ∗2 + 2∗ → Si + 2H ∗
∗ represents a free surface site SiH ∗4 and SiH ∗2 are adsorbed species 6.976 Flat Panel Display Devices - Spring 2001
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Deposition Rate
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Nucleation on Amorphous Surfaces n s æ n1 ö ~ çç ÷÷ no è no ø
(i +1) / 2
é E + Em − Ed ù exp ê i ú kT û ë
ns = number of stable nuclei n1 = is adsorbed atom conc. no = total number of surface sites/ unit area Ei = energy of formation of cluster with i atoms Em = activation energy of migration of cluster Ed = activation energy of diffusion of single atom
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a-Si and p-Si Deposition • Amorphous silicon is deposited at lower temperatures which typically have lower deposition rates • Clusters of Si atoms form from adsorbed Si depending on – Surface diffusion length – Arrival rate of silicon atoms – Desorbtion rate
• Density of clusters decreases with substrate temperature • p-Si deposited at higher temperatures and higher deposition rates 6.976 Flat Panel Display Devices - Spring 2001
L ≈ Dt =
1 æ E ö expç − a ÷ RD è kT ø
D = surface diffusion coefficient Ea = activation energy of surface diffusion RD = deposition rate L = diffusion length Lecture 16
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Low Temperature a-Si Deposition
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Recrystallization • Recrystallization converts a-Si to p-Si by thermal processing. – Thermal anneals – Excimer Laser
• Recrystallization proceeds in three stages – Nucleation – Primary recrystallization – Secondary recrystallization
• Grain growth infleunced by – Strain induced growth d = d o + k 1t – Grain-boundary / interface induced growth – Impurity drag 3 d 3 + k 3t o
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d = d o2 + k 22 t
3
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Solid Phase Epitaxy (SPE) Amorphous Silicon Regrowth
• • •
Crystalline Silicon
a-Si is a “supercooled” liquid state Raise the substrate temperature to 600 °C and small atom motions at the “L-S” or “a-X” interface allow a plane of perfect crystal to form The “a-X” front moves to the surface
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Annealling p-Si X-ray diffraction observation of structural changes
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Annealling p-Si Dependence of mean grain size on annealing temperature
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Annealling a-Si X-ray diffraction observation of development of crystal structure
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TEM of 600 nm Si films on SiO2 LPCVD @ 550 ºC & 625 ºC
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Excimer Laser Crystallization • UV Laser pulse is absorbed in top 100 Å of a-Si • 35 ns laser pulse melts aSi, re-growing poly-Si • High hydrogen concentration in PECVD a-Si:H requires several laser energy fluences
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Grain Engineering
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Grain Engineering
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Grain Engineered TFTs
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Conduction in undoped p-Si é EA ù σ = σ o exp ê− ú kT ë û
é æ To ö1 4 ù σo σ= exp ê− ç ÷ ú T êë è T ø úû
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-25 ºC < T < 200 ºC EA = 0.55 eV
-25 ºC > T ºC Hopping conduction at low T
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Conduction in doped p-Si
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Carrier Trapping
Free carriers immobilized by grain boundary traps
Shallow tail states are associated with strained bonds and deep states near mid-gap are caused by broken bonds 6.976 Flat Panel Display Devices - Spring 2001
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Potential Barrier N d2V = q ε dx 2 qN 2 VB = xd 2ε when grains are completely depleted 2
qN æ L ö qNL2 VB = ç ÷ = 2ε è 2 ø 8ε where L is grain size
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Potential Barrier
2
qN æ N T ö qN T2 VB = ç ÷ = 2ε è 2N ø 8εN
• The trap energy is deep enough such that the traps are completely filled when the dopant concentration exceeds the critical doping N* = NT/L • As N increase above N*, the number of trapped carriers remains at N* leaving the rest to form the quasi-neutral region 6.976 Flat Panel Display Devices - Spring 2001
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Carrier Transport in p-Si é q (VB − V )ùú J = qv cn exp ê− ë kT û v c = kT / 2πm*
Assuming VG=V/Ngrain æ qV ö é qV ù J = 2qv cn exp ê− B ú sinh ç G ÷ è 2kT ø ë kT û For VG < kT/q, then q2 vc é qV ù exp ê− B ú VG J= kT ë kT û q 2 vcL é qV ù σ= exp ê− B ú kT ë kT û µ eff =
Effective Mobility
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qv c L é qV ù exp ê− B ú kT ë kT û
é qV ù µ eff = µ 0 exp ê− B ú ë kT û Lecture 16
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Poly-Silicon TFT • High-temp Poly-Si TFT – – – – –
>600°C process temperature Processing similar to bulk Si CMOS Thermally grown SiO2 gate dielectric High temperature quartz substrate Small high resolution light valves
• Low-temp Poly-Si TFT – – – –
