ABA ABX ABY ADCA (opr)
Operation
Add Accumulators Add B to X Add B to Y Add with Carry to A
ADCB (opr) Add with Carry to B
ADDA (opr) Add Memory to A
ADDB (opr) Add Memory to B
ADDD (opr) Add 16-Bit to D
ANDA (opr) AND A with Memory
ANDB (opr) AND B with Memory
ASL (opr)
Boolean Expression
A+B→A IX + 00:B → IX IY + 00:B → IY A+M+C→A
Addressing Mode for Operand INH INH INH A IMM A DIR A EXT A IND,X A IND,Y
B+M+C→B
A+M→A
B+M→B
D + M:M + 1 → D
A•M → A
B•M → B
Arithmetic Shift Left C
ASLD
b7
C9 ii D9 dd F9 hh E9 ff 18 E9 ff
A IMM A DIR A EXT A IND,X A IND,Y
8B ii 9B dd BB hh AB ff 18 AB ff
B IMM B DIR B EXT B IND,X B IND,Y
CB ii DB dd FB hh EB ff 18 EB ff
IMM DIR EXT IND,X IND,Y
C3 jj D3 dd F3 hh E3 ff 18 E3 ff
A IMM A DIR A EXT A IND,X A IND,Y
84 ii 94 dd B4 hh A4 ff 18 A4 ff
B IMM B DIR B EXT B IND,X B IND,Y
C4 ii D4 dd F4 hh E4 ff 18 E4 ff
EXT
78 hh 68 ff 18 68 ff 48 58
IND,Y A INH B INH
b0
Arithmetic Shift Left Double
89 ii 99 dd B9 hh A9 ff 18 A9 ff
B IMM B DIR B EXT B IND,X B IND,Y
0 IND,X
ASLA ASLB
Machine Coding (Hexadecimal) Opcode Operand(s) 1B 1 3A 1 18 3A 2
Bytes
Source Form(s)
INH
05
EXT IND,X C IND,Y A INH B INH
77 hh 67 ff 18 67 ff 47 57
REL DIR IND,X IND,Y REL REL REL REL REL REL
24 rr 15 dd 1D ff 18 1D ff 25 rr 27 rr 2C rr 2E rr 22 rr 24 rr
Cycle
Jeu d'instructions du 68HC11
2 3 4
Cycle Condition Codes by Cycle* S X H I N Z V C 2-1 - - ↕ - ↕ ↕ ↕ ↕ 2-2 - - - - - - - 2-4 - - - - - - - -
2 3 4 4 5
3-1 4-1 5-2 6-2 7-2
--↕-↕↕↕↕
ll
2 2 3 2 3
2 3 4 4 5
3-1 4-1 5-2 6-2 7-2
--↕-↕↕↕↕
ll
2 2 3 2 3
2 3 4 4 5
3-1 4-1 5-2 6-2 7-2
--↕-↕↕↕↕
ll
2 2 3 2 3
2 3 4 4 5
3-1 4-1 5-2 6-2 7-2
--↕-↕↕↕↕
ll
2 2 3 2 3
4 5 6 6 7
3-3 4-7 5-10 6-10 7-8
----↕↕↕↕
ll
3 2 3 2 3
2 3 4 4 5
3-1 4-1 5-2 6-2 7-2
----↕↕0-
ll
2 2 3 2 3
2 3 4 4 5
3-1 4-1 5-2 6-2 7-2
----↕↕0-
ll
2 2 3 2 3 3 2 3 1 1
6 6 7 2 2
5-8 6-3 7-3 2-1 2-1
----↕↕↕↕
1
3
2-2
----↕↕↕↕
3 2 3 1 1
6 6 7 2 2
5-8 6-3 7-3 2-1 2-1
----↕↕↕↕
2 3 3 4 2 2 2 2 2 2
3 6 7 8 3 3 3 3 3 3
8-1 4-10 6-13 7-10 8-1 8-1 8-1 8-1 8-1 8-1
-----------↕↕0-
kk
ll
0 C
ASR (opr)
b15
b0
Arithmetic Shift Right b7
ASRA ASRB
b0
BCC (rel) Branch if Carry Clear BCLR (opr) Clear Bit(s) (msk)
?C=0
BCS (rel) BEQ (rel) BGE (rel) BGT (rel) BHI (rel) BHS (rel)
?C=1 ?Z=1 ?N⊕V=0 ? Z + (N ⊕ V) = 0 ?C+Z=0 ?C=0
Branch if Carry Set Branch if = Zero Branch if ≥ Zero Branch if > Zero Branch if Higher Branch if Higher or Same
M•(mm) → M
ll
mm mm mm
-------------------------------------------
*Cycle-by-cycle number provides a reference to Tables 10-2 through 10-8 which detail cycle-by-cycle operation. Example: Table 10-1 Cycle-by-Cycle column reference number 2-4 equals Table 10-2 line item 2-4.
Page 1
Boolean Expression
Addressing Mode for Operand
Machine Coding (Hexadecimal)
2 2 3 2 3
2 3 4 4 5
3-1 4-1 5-2 6-2 7-2
----↕↕0-
2 2 3 2 3
2 3 4 4 5
----↕↕0-
2F rr 25 rr 23 rr 2D rr 2B rr 26 rr 2A rr 20 rr 13 dd mm rr 1F ff mm rr 18 1F ff mm rr 21 rr 12 dd mm rr 1E ff mm rr 18 1E ff mm rr 14 dd mm 1C ff mm 18 1C ff mm 8D rr 28 rr 29 rr 11 0C 0E 7F hh ll 6F ff 18 6F ff 4F 5F 0A
2 2 2 2 2 2 2 2 4 4 5 2 4 4 5 3 3 4 2 2 2 1 1 1 3 2 3 1 1 1
3 3 3 3 3 3 3 3 6 7 8 3 6 7 8 6 7 8 6 3 3 2 2 2 6 6 7 2 2 2
3-1 4-1 5-2 6-2 7-2 8-1 8-1 8-1 8-1 8-1 8-1 8-1 8-1 4-11 6-14 7-11 8-1 4-11 6-14 711 4-10 6-13 7-10 8-2 8-1 8-1 2-1 2-1 2-1 5-8 6-3 7-3 2-1 2-1 2-1
81 ii 91 dd B1 hh A1 ff 18 A1 ff
2 3 4 4 5
3-1 4-1 5-2 6-2 7-2
----↕↕↕↕
ll
2 2 3 2 3
2 3 4 4 5
3 2 3 1 1
6 6 7 2 2
3-1 4-1 5-2 6-2 7-2 5-8 6-3 7-3 2-1 2-1
----↕↕↕↕
ll
2 2 3 2 3
4 3 4 3 3
5 6 7 7 7
3-5 4-9 5-11 6-11 7-8
----↕↕↕↕
Opcode Operand(s) 85 ii 95 dd B5 hh ll A5 ff 18 A5 ff
BITA (opr)
Bit(s) Test A with Memory
A•M
A IMM A DIR A EXT A IND,X A IND,Y
BITB (opr)
Bit(s) Test B with Memory
B•M
B IMM B DIR B EXT B IND,X B IND,Y
C5 ii D5 dd F5 hh E5 ff 18 E5 ff
REL REL REL REL REL REL REL REL DIR IND,X IND,Y REL DIR IND,X IND,Y DIR IND,X IND,Y REL REL REL INH INH INH EXT IND,X IND,Y A INH B INH INH A IMM A DIR A EXT A IND,X A IND,Y B IMM B DIR B EXT B IND,X B IND,Y
C1 ii D1 dd F1 hh E1 ff 18 E1 ff
EXT IND,X IND,Y A INH B INH IMM DIR EXT IND,X IND,Y
73 hh 63 ff 18 63 ff 43 53
BLE (rel) Branch if ≤ Zero BLO (rel) Branch if Lower BLS (rel) Branch if Lower or Same BLT (rel) Branch If < Zero BMI (rel) Branch if Minus BNE (rel) Branch if Not = Zero BPL (rel) Branch if Plus BRA (rel) Branch Always BRCLR(opr) Branch if Bit(s) Clear (msk) (rel) BRN (rel) Branch Never BRSET(opr) Branch if Bit(s) Set (msk) (rel) BSET(opr) Set Bit(s) (msk)
? Z + (N ⊕ V) = 1 ?C=1 ?C+Z=1 ?N⊕V=1 ?N=1 ?Z=0 ?N=0 ?1=1 ? M • mm = 0
BSR (rel) BVC (rel) BVS (rel) CBA CLC CLI CLR (opr)
Branch to Subroutine Branch if Overflow Clear Branch if Overflow Set Compare A to B Clear Carry Bit Clear Interrupt Mask Clear Memory Byte
See Special Ops ?V=0 ?V=1 A–B 0→C 0→l 0→M
CLRA CLRB CLV CMPA (opr)
Clear Accumulator A Clear Accumulator B CIear Overflow Flag Compare A to Memory
0→A 0→B 0→V A–M
CMPB (opr) Compare B to Memory
?1=0 ? (M) • mm = 0 M + mm → M
B–M
COM (opr)
1’s Complement Memory Byte $FF – M → M
COMA COMB CPD (opr)
1’s Complement A 1’s Complement B Compare D to Memory 16-Bit
$FF – A → A $FF – B → B D – M:M + 1
Cycle Condition Codes by Cycle* S X H I N Z V C
Cycle
Operation
Bytes
Source Form(s)
ll
ll
1A 83 jj kk 1A 93 dd 1A B3 hh ll 1A A3 ff CD A3 ff
----------------------------------------------------------------
---------------
----↕↕0-
-------------------------↕↕↕↕ -------0 ---0-------0100
----0100 ----0100 ------0-
----↕↕01
----↕↕01 ----↕↕01
*Cycle-by-cycle number provides a reference to Tables 10-2 through 10-8 which detail cycle-by-cycle operation. Example: Table 10-1 Cycle-by-Cycle column reference number 2-4 equals Table 10-2 line item 2-4.
Page 2
Boolean Expression
Addressing Mode for Operand
4 5 6 6 7
3-3 4-7 5-10 6-10 7-8
----↕↕↕↕
18 8C jj kk 18 9C dd 18 BC hh ll 1A AC ff 18 AC ff
4 3 4 3 3
5 6 7 7 7
----↕↕↕↕
INH EXT IND,X IND,Y
19 7A hh 6A ff 18 6A ff
1 3 2 3
2 6 6 7
A–1→A B–1→B SP – 1 → SP IX – 1 → IX
A INH B INH INH INH
4A 5A 34 09
1 1 1 1
2 2 3 3
3-5 4-9 5-11 6-11 7-8 2-1 5-8 6-3 7-3 2-1 2-1 2-3 2-2
IY – 1 → IY A⊕M→A
INH A IMM A DIR A EXT A IND,X A IND,Y
18 09
2
4
2-4
-----↕ --
88 ii 98 dd 88 hh A8 ff 18 A8 ff
2 3 4 4 5
3-1 4-1 5-2 6-2 7-2
----↕↕0-
ll
2 2 3 2 3
B IMM B DIR B EXT B IND,X B IND,Y
C8 ii D8 dd F8 hh E8 ff 18 E8 ff
2 3 4 4 5
INH INH EXT IND,X IND,Y A INH B INH INH INH INH EXT IND,X IND,Y DIR EXT IND,X IND,Y A IMM A DIR A EXT A IND,X A IND,Y
03 02 7C hh 6C ff 18 6C ff 4C 5C 31 08 18 08 7E hh 6E ff 18 6E ff 9D dd BD hh AD ff 18 AD ff
1 1 3 2 3 1 1 1 1 2 3 2 3 2 3 2 3
41 41 6 6 7 2 2 3 3 4 3 3 4 5 6 6 7
3-1 4-1 5-2 6-2 7-2 2-17 2-17 5-8 6-3 7-3 2-1 2-1 2-3 2-2 2-4 5-1 6-1 7-1 4-8 5-12 6-12 7-9
----↕↕0-
ll
2 2 3 2 3
2 3 4 4 5
3-1 4-1 5-2 6-2 7-2
----↕↕0-
ll
2 2 3 2 3
B IMM B DIR B EXT B IND,X B IND,Y
C6 ii D6 dd F6 hh E6 ff 18 E6 ff
2 3 4 4 5
3-1 4-1 5-2 6-2 7-2
----↕↕0-
ll
2 2 3 2 3
IMM DIR EXT IND,X IND,Y
CC jj DC dd FC hh EC ff 18 EC ff
3 2 3 2 3
3 4 5 5 6
3-2 4-3 5-4 6-6 7-6
----↕↕0-
Compare X to Memory 16-Bit
IX – M:M + 1
IMM DIR EXT IND,X IND,Y
CPY (opr)
Compare Y to Memory 16-Bit
IY – M:M + 1
IMM DIR EXT IND,X IND,Y
DAA DEC (opr)
Decimal Adjust A Decrement Memory Byte
Adjust Sum to BCD M–1→M
DECA DECB DES DEX
Decrement Accumulator A Decrement Accumulator B Decrement Stack Pointer Decrement Index Register X
EORB (opr) Exclusive OR B with Memory
B⊕M→B
FDIV IDIV INC (opr)
Fractional Divide 16 by 16 Integer Divide 16 by 16 Increment Memory Byte
D/IX → IX; r → D D/IX → IX; r → D M+1→M
INCA INCB INS INX INY JMP (opr)
Increment Accumulator A Increment Accumulator B Increment Stack Pointer Increment Index Register X Increment Index Register Y Jump
A+1→A B+1→B SP + 1 → SP IX + 1 → IX IY + 1 → IY See Special Ops
JSR (opr)
Jump to Subroutine
See Special Ops
LDAA (opr) Load Accumulator A
LDAB (opr) Load Accumulator B
LDD (opr)
Load Double Accumulator D
Cycle Condition Codes by Cycle* S X H I N Z V C
3 2 3 2 3
CPX (opr)
DEY Decrement Index Register Y EORA (opr) Exclusive OR A with Memory
Machine Coding (Hexadecimal)
Cycle
Operation
Bytes
Source Form(s)
M→A
M→B
M → A,M + 1 → B
Opcode Operand(s) 8C jj kk 9C dd BC hh ll AC ff CD AC ff
86 ii 96 dd B6 hh A6 ff 18 A6 ff
ll
ll
ll
ll
kk ll
----↕↕↕↕ ----↕↕↕-
----↕↕↕----↕↕↕------------↕ --
-----↕↕↕ -----↕0↕ ----↕↕↕-
----↕↕↕----↕↕↕------------↕ ------↕ ---------
--------
*Cycle-by-cycle number provides a reference to Tables 10-2 through 10-8 which detail cycle-by-cycle operation. Example: Table 10-1 Cycle-by-Cycle column reference number 2-4 equals Table 10-2 line item 2-4.
Page 3
Boolean Expression
Addressing Mode for Operand
3 4 5 5 6
3-2 4-3 5-4 6-6 7-6
----↕↕0-
CE jj kk DE dd FE hh ll EE ff CD EE ff
3 2 3 2 3
3 4 5 5 6
3-2 4-3 5-4 6-6 7-6
----↕↕0-
IMM DIR EXT IND,X IND,Y
18 CE jj 18 DE dd 18 FE hh 1A EE ff 18 EE ff
kk
4 3 4 3 3
4 5 6 6 6
3-4 4-5 5-6 6-7 7-6
----↕↕0-
EXT IND,X 0 IND,Y A INH B INH
78 hh 68 ff 18 68 ff 48 58
ll
3 2 3 1 1
6 6 7 2 2
5-8 6-3 3-7 2-1 2-1
----↕↕↕↕
INH
05
1
3
2-2
----↕↕↕↕
EXT IND,X IND,Y C A INH B INH
74 hh 64 ff 18 64 ff 44 54
3 2 3 1 1
6 6 7 2 2
5-8 6-3 7-3 2-1 2-1
----↕↕↕↕
INH
04
1
3
2-2
----0↕↕↕
INH
3D
1
10
2-13
-------↕ ----↕↕↕↕
Load Stack Pointer
M:M + 1 → SP
IMM DIR EXT IND,X IND,Y
LDX (opr)
Load Index Register X
M:M + 1 → IX
IMM DIR EXT IND,X IND,Y
LDY (opr)
Load Index Register Y
M:M + 1 → IY
Logical Shift Left
LSLA LSLB LSLD
C
b7
b0
Cycle Condition Codes by Cycle* S X H I N Z V C
3 2 3 2 3
LDS (opr)
LSL (opr)
Machine Coding (Hexadecimal)
Cycle
Operation
Bytes
Source Form(s)
Logical Shift Left Double
Opcode Operand(s) 8E jj kk 9E dd BE hh ll AE ff 18 AE ff
ll
0 C
LSR (opr)
b0
Logical Shift Right
LSRA LSRB LSRD
b15
0 b7
b0
Logical Shift Right Double
ll
0 b15
b0
C
AxB → D
MUL
Multiply 8 by 8
NEG (opr)
2’s Complement Memory Byte 0 – M → M
NEGA NEGB NOP ORAA (opr)
2’s Complement A 2’s Complement B No Operation OR Accumulator A (Inclusive)
0–A→A 0–B→B No Operation A+M→A
ORAB (opr) OR Accumulator B (Inclusive) B + M → B
PSHA PSHB PSHX PSHY PULA PULB PULX PULY ROL (opr) ROLA ROLB
Push A onto Stack Push B onto Stack Push X onto Stack (Lo First) Push Y onto Stack (Lo First) Pull A from Stack Pull B from Stack Pull X from Stack (Hi First) Pull Y from Stack (Hi First) Rotate Left
A → Stk, SP = SP–1 B → Stk, SP = SP–1 IX → Stk, SP = SP–2 IY → Stk, SP = SP–2 SP = SP + 1, A←Stk SP = SP + 1, B←Stk SP = SP + 2, IX←Stk SP = SP + 2, IY←Stk
C
b7
b0
EXT IND,X IND,Y A INH B INH INH A IMM A DIR A EXT A IND,X A IND,Y
70 hh ll 60 ff 18 60 ff 40 50 01
3 2 3 1 1 1
6 6 7 2 2 2
5-8 6-3 7-3 2-1 2-1 2-1
8A ii 9A dd BA hh AA ff 18 AA ff
2 3 4 4 5
3-1 4-1 5-2 6-2 7-2
----↕↕0-
ll
2 2 3 2 3
B IMM B DIR B EXT B IND,X B IND,Y
CA ii DA dd FA hh EA ff 18 EA ff
2 3 4 4 5
1 1 1 2 1 1 1 2
3 3 4 5 4 4 5 6
3-1 4-1 5-2 6-2 7-2 2-6 2-6 2-7 2-8 2-9 2-9 2-10 2-11
----↕↕0-
ll
2 2 3 2 3
3 2 3 1 1
6 6 7 2 2
5-8 6-3 7-3 2-1 2-1
A INH B INH INH INH A INH B INH INH INH EXT IND,X IND,Y C A INH B INH
36 37 3C 18 3C 32 33 38 18 38 79 hh 69 ff 18 69 ff 49 59
ll
----↕↕↕↕ ----↕↕↕↕ --------
------------------------------------------------------------↕↕↕↕
*Cycle-by-cycle number provides a reference to Tables 10-2 through 10-8 which detail cycle-by-cycle operation. Example: Table 10-1 Cycle-by-Cycle column reference number 2-4 equals Table 10-2 line item 2-4.
Page 4
Rotate Right
RORA RORB RTI RTS SBA SBCA (opr)
C
Return from Interrupt Return from Subroutine Subtract B from A Subtract with Carry from A
SBCB (opr) Subtract with Carry from B
SEC SEI SEV STAA (opr)
Set Carry Set Interrupt Mask Set Overflow Flag Store Accumulator A
STAB (opr) Store Accumulator B
STD (opr)
STOP STS (opr)
STX (opr)
STY (opr)
Store Accumulator D
Stop Internal Clocks Store Stack Pointer
Store Index Register X
Store Index Register Y
SUBA (opr) Subtract Memory from A
SUBB (opr) Subtract Memory from B
SUBD (opr) Subtract Memory from D
SWI TAB TAP TBA
Boolean Expression
Software Interrupt Transfer A to B Transfer A to CC Register Transfer B to A
b7
b0
See Special Ops See Special Ops A–B→A A–M–C→A
B–M–C→B
1→C 1→I 1→V A→M
B→M
A → M, B → M + 1
SP → M:M + 1
IX → M:M + 1
IY → M:M + 1
A–M→A
B–M→B
D – M:M + 1→ D
See Special Ops A→B A → CCR B→A
Addressing Mode for Operand
EXT IND,X IND,Y C A INH B INH
Machine Coding (Hexadecimal) Opcode Operand(s) 76 hh ll 66 ff 18 66 ff 46 56
Cycle Condition Codes by Cycle* S X H I N Z V C
Cycle
ROR (opr)
Operation
Bytes
Source Form(s)
3 2 3 1 1
6 6 7 2 2
5-8 6-3 7-3 2-1 2-1
----↕↕↕↕
INH INH INH A IMM A DIR A EXT A IND,X A IND,Y
3B 39 10
1 1 1
12 5 2
2-14 2-12 2-1
↕↓↕↕↕↕↕↕ -----------↕↕↕↕
82 ii 92 dd B2 hh A2 ff 18 A2 ff
2 3 4 4 5
3-1 4-1 5-2 6-2 7-2
----↕↕↕↕
ll
2 2 3 2 3
B IMM B DIR B EXT B IND,X B IND,Y
C2 ii D2 dd F2 hh E2 ff 18 E2 ff
2 3 4 4 5
INH INH INH A DIR A EXT A IND,X A IND,Y
OD OF OB
1 1 1
2 2 2
3-1 4-1 5-2 6-2 7-2 2-1 2-1 2-1
----↕↕↕↕
ll
2 2 3 2 3
2 3 2 3 2 3 2 3 2 3 2 3 1 2 3 2 3 2 3 2 3 3 4 3 3
3 4 4 5 3 4 4 5 4 5 5 6 2 4 5 5 6 4 5 5 6 5 6 6 6
4-2 5-3 6-5 7-5 4-2 5-3 6-5 7-5 4-4 5-5 6-8 7-7 2-1 4-4 5-5 6-8 7-7 4-4 5-5 6-8 7-7 4-6 5-7 6-9 7-7
----↕↕0-
2 3 4 4 5
3-1 4-1 5-2 6-2 7-2
----↕↕↕↕
lI
2 2 3 2 3
2 3 4 4 5
3-1 4-1 5-2 6-2 7-2
----↕↕↕↕
ll
2 2 3 2 3 3 2 3 2 3
4 5 6 6 7
----↕↕↕↕
1 1 1 1
14 2 2 2
3-3 4-7 5-10 6-10 7-8 2-15 2-1 2-1 2-1
97 dd B7 hh A7 ff 18 A7 ff
B DIR B EXT B IND,X B IND,Y DIR EXT IND,X IND,Y INH DIR EXT IND,X IND,Y DIR EXT IND,X IND,Y DIR EXT IND,X IND,Y A IMM A DIR A EXT A IND,X A IND,Y
D7 dd F7 hh E7 ff 18 E7 ff DD dd FD hh ED ff 18 ED ff CF 9F dd BF hh AF ff 18 AF ff DF dd FF hh EF ff CD EF ff 18 DF dd 18 FF hh 1A EF ff 18 EF ff
B IMM B DIR B EXT B IND,X B IND,Y
C0 ii D0 dd F0 hh E0 ff 18 E0 ff
IMM DlR EXT IND,X IND,Y
83 jj 93 dd B3 hh A3 ff 18 A3 ff
INH INH INH INH
80 ii 90 dd B0 hh A0 ff 18 A0 ff
3F 16 06 17
ll
ll
ll
ll
ll
ll
kk ll
-------1 ---1---------1-
----↕↕0-
----↕↕0-
-----------↕↕0-
----↕↕0-
----↕↕0-
- - - 1- - - ----↕↕0↕↓↕↕↕↕↕↕ ----↕↕0-
*Cycle-by-cycle number provides a reference to Tables 10-2 through 10-8 which detail cycle-by-cycle operation. Example: Table 10-1 Cycle-by-Cycle column reference number 2-4 equals Table 10-2 line item 2-4.
Page 5
Boolean Expression
Addressing Mode for Operand
TEST (Only in Test Modes) Transfer CC Register to A Test for Zero or Minus
Address Bus Counts CCR → A M–0
TSTA TSTB TSX TSY TXS TYS WAI
Transfer Stack Pointer to X Transfer Stack Pointer to Y Transfer X to Stack Pointer Transfer Y to Stack Pointer Wait for Interrupt
A–0 B–0 SP + 1 → IX SP + 1 → IY IX – 1 → SP IY – 1 → SP Stack Regs & WAlT
INH INH EXT IND,X IND,Y A INH B INH INH INH INH INH INH
XGDX XGDY
Exchange D with X Exchange D with Y
IX → D, D → IX IY → D, D → IY
INH INH
Machine Coding (Hexadecimal) Opcode Operand(s) 00 07 7D hh ll 6D ff 18 6D ff 4D 5D 30 18 30 35 18 35 3E 8F 18 8F
Cycle
TEST TPA TST (opr)
Operation
Bytes
Source Form(s)
1 1 3 2 3 1 1 1 2 1 2 1
** 2 6 6 7 2 2 3 4 3 4 ***
1 2
3 4
Cycle Condition Codes by Cycle* S X H I N Z V C 2-20 - - - - - - - 2-1 - - - - - - - 5-9 - - - - ↕ ↕ 0 0 6-4 7-4 2-1 - - - - ↕ ↕ 0 0 2-1 - - - - ↕ ↕ 0 0 2-3 - - - - - - - 2-5 - - - - - - - 2-2 - - - - - - - 2-4 - - - - - - - 2-16 - - - - - - - 2-2 2-4
---------------
*Cycle-by-cycle number provides a reference to Tables 10-2 through 10-8 which detail cycle-by-cycle operation. Example: Table 10-1 Cycle-by-Cycle column reference number 2-4 equals Table 10-2 line item 2-4. **Infinity or Until Reset Occurs ***12 Cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an integer number of MPU E-clock cycles (n) until an interrupt is recognized. Finally, two additional cycles are used to fetch the appropriate interrupt vector (14 + n total). dd = 8-Bit Direct Address ($0000 –$00FF) (High Byte Assumed to be $00) ff = 8-Bit Positive Offset $00 (0) to $FF (255) (Is Added to Index) hh = High Order Byte of 16-Bit Extended Address ii = One Byte of Immediate Data jj = High Order Byte of 16-Bit Immediate Data kk = Low Order Byte of 16-Bit Immediate Data ll = Low Order Byte of 16-Bit Extended Address mm = 8-Bit Bit Mask (Set Bits to be Affected) rr = Signed Relative Offset $80 (– 128) to $7F (+ 127) (Offset Relative to the Address Following the Machine Code Offset Byte)
Page 6
JSR, JUMP TO SUBROUTINE
WAI, WAIT FOR INTERRUPT
MAIN PROGRAM PC
DIRECT
$9D = JSR dd RTN NEXT MAIN INSTR. MAIN PROGRAM PC
INDEXED, X
$AD = JSR ff RTN NEXT MAIN INSTR. MAIN PROGRAM PC
INDEXED, Y
$18 = PRE $AD = JSR RTN ff NEXT MAIN INSTR.
7
STACK
PC
SP SP+1 SP+2 SP+3 SP+4 SP+5 SP+6 SP+7 SP+8
➩ SP+9
INTERRUPT ROUTINE
0
7
SP+2 SP+3 SP+4 SP+5 SP+6 SP+7 SP+8
➩ SP+9 SWI, SOFTWARE INTERRUPT MAIN PROGRAM PC
$3F = SWI
7
JMP, JUMP
SP–7 SP–6 SP–5
WAI, WAIT FOR INTERRUPT
SP–4
MAIN PROGRAM
SP–3
$3E = WAI
SP–2 SP–1
MAIN PROGRAM PC
$6E = JMP ff
SP
BSR, BRANCH TO SUBROUTINE
INDEXED, X
MAIN PROGRAM X + ff NEXT MAIN INSTR.
PC
$8D = BSR
INDEXED, Y
$18 = PRE $6E = JMP ff
RTS, RETURN FROM SUBROUTINE MAIN PROGRAM $39 = RTS
X + ff NEXT MAIN INSTR.
EXTENDED
$7E = JMP hh ll
hh ll NEXT MAIN INSTR.
STACK
0
SP SP+1
RTNH RTNL
LEGEND: RTN = ADDRESS OF NEXT INSTRUCTION IN MAIN PROGRAM TO BE EXECUTED UPON RETURN FROM SUBROUTINE RTNH = MOST SIGNIFICANT BYTE OF RETURN ADDRESS RTNL = LEAST SIGNIFICANT BYTE OF RETURN ADDRESS ➩ = STACK POINTER POSITION AFTER OPERATION IS COMPLETE dd = 8-BIT DIRECT ADDRESS ($0000–$00FF) (HIGH BYTE ASSUMED TO BE $00) ff = 8-BIT POSITIVE OFFSET $00 (0) TO $FF (256) IS ADDED TO INDEX hh = HIGH-ORDER BYTE OF 16-BIT EXTENDED ADDRESS ll = LOW-ORDER BYTE OF 16-BIT EXTENDED ADDRESS rr= SIGNED RELATIVE OFFSET $80 (–128) TO $7F (+127) (OFFSET RELATIVE TO THE ADDRESS FOLLOWING THE MACHINE CODE OFFSET BYTE)
Figure 10-2 Special Operations
Page 7
0
RTNH RTNL
7
➩ SP+2
MAIN PROGRAM
STACK
➩ SP–2 SP
PC
PC
7 SP–1
MAIN PROGRAM PC
0
CCR ACCB ACCA IXH IXL IYH IYL RTNH RTNL
SP–8
PC
STACK
➩ SP–9
PC
$BD = PRE hh RTN ll NEXT MAIN INSTR.
CCR ACCB ACCA IXH IXL IYH IYL RTNH RTNL
SP+1
MAIN PROGRAM INDEXED, Y
0
SP
$3E = WAI
CCR ACCB ACCA IXH IXL IYH IYL RTNH RTNL
STACK
