Hai Vo-Ba
[email protected]
Hewlett Packard System VLSI Technology Operation, Fort Collins, Colorado
2
Overview • Library cell characterization bottle-neck • A new and improved cell characterization process • Result qualification • Key learnings
3
LC Requirements for Synthesis • Environment description and operating conditions • Timing model for each cell – Non-linear delay model (NLDM) ➢ Input slopes ➢ Output loads
tin
Cin
tdly
Cout
tout
tout = f1(tin,Cout) tdly = f2(tin,Cout)
4
LC Requirements for Synthesis (cont.) • Cell function description – Logical description – Unate-ness – Clocking
• Cell physical information – Area – Input capacitance – Output capacitance
• Schematic symbols
5
Traditional Library Characterization • Circuit simulator-based approaches require – Tech file generation – Device model calibration – Data reduction / post-processing
• They can handle a larger class of circuits • They have better accuracy but are CPU-intensive – Users often have to trade off between accuracy and run time
6
PathMill-Based Library Cell Characterization • PathMill is FET-level static timing analyzer that – can generate an ITS timing model for a custom block or library cell – can produce one set of models for the longest paths and an optional set of models for the shortest paths
• PathMill is quite fast and there is no need to provide circuit stimulus • For this to work, PathMill must be able to “recognize” your circuits
7
Accuracy & Approximation • Design Compiler analyzes and predicts timing behavior of a design using a combination of lookup tables and linear interpolation
Z1 = a + bX1 + cY1 + dX1Y1 z
Prop delay
Z2 = a + bX2 + cY2 + dX2Y2 Z3 = a + bX3 + cY3 + dX3Y3 Z4 = a + bX4 + cY4 + dX4Y4
Output cap Input slew
x
y
8
Accuracy & Approximation (cont.) • The over-all accuracy of this tool flow depends on several factors – how many break-points are selected and how they are selected – cell netlist is generated from schematic or actual artwork – parasitic R and C are included or not
• Spice’s accuracy may be an over-kill after all?
9
Characterization Point Selection • Any where between 5x5 up to 200x200
10
Characterization Point Selection • Geometric spacing is better than linear one
11
Validation Process For each cell, 10 “mid-points” are selected and submitted to DC for timing analysis
12
Validation Process (cont.) From DC timing report, the worst case path for each cell at a given “mid-point” is matched against the results from PathMill analysis as well as your favorite Spice simulation rising risingedge edge
SPICE ---------------R 0.700 0.000 F 0.726 0.026 R 0.888 0.162 -----0.188 falling fallingedge edge
PATHMILL ---------------0.700 0.000 0.729 0.029 0.899 0.170 -----0.199
ERROR ------0.00% 11.54% 5.74%
node ---C NZ Z
input input
0.011 output output
difference differencebetween betweenPathMill PathMilland andSpice Spice
13
How Well Does It Work? • The results of this 3-way comparison are expressed in percentage – a negative number indicating that DC timing is faster than either Spice or PathMill – averages are computed across all cell families from both signed values and absolute ones
• This data is used to tune the process to improve the overall average • It is also used to diagnose any out-liers
14
How Well Does It Work? (cont.) • On the average, the DC timing reports are within +4% of Spice simulation results • This is achieved with a 2 orders of magnitude improvement in throughput
2
-11.7
4
-10.5
4 8
-9.2
More Statistics
1
-13.0
16
-8.0
23
-6.8
40
-5.5 31
-4.3
36
-3.0
53
-1.8
77
-0.6
155 205
3.1 175
4.4 95
5.6 63
6.9
Error Distribution
117
1.9
52
8.1 25
Percent (faster ==> slower)
0.7
9.3
29
10.6 16 15
11.8 13.0 8
14.3
6
15.5 16.8
3
18.0
3
19.2
1
20.5
0
21.7
1
23.0
0
24.2
1
25.4
0
15
2
More
250
1
-14.2
200
1
-15.4
150
100
50
0
-16.7
16
Issues • PathMill could have done better at figuring out the unate-ness for the muxes and the xor’s/xnor’s
17
Issues (cont.) • We have to make 2 passes to completely characterize the transparent latches
SET
DIN
OUT
18
Key Learnings • A FET-level static timing analyzer such as PathMill is a very viable tool to characterize static CMOS library cells. • A validation suite is essential to ensure the quality of the results.
19
Future Work • Hold time characterization using min_delay • Characterization of larger and more complex cells: – sequential circuits – asynchronous circuits – dynamic circuits
