GOLFIER Arnaud

B16 – 1004, Moyenne corniche des Pugets, 06700 Saint Laurent du Var 31 years old, married, two children

 (+33)6.87.84.19.67  [email protected]  http://arnaudgolfier.free.fr/cv_en.php http://lnkd.in/PpjcqE

Digital ASIC Leader Skills Strengths Language

Technical skills

Large problem solver aptitude and strongly committed to ensure schedule and quality within cost budget. Excellent team player with recognized expertise in IC designs (Front-End / Synthesis / STA / verification). English: fluent speaker and daily used (Meetings, Conf. calls, Reports). RTL coding: VHDL, Verilog and Esterel (ESL) Design flow: LEC, CLP, Spyglass, Magillem, Genesis, ModelSim, NC-Sim, DesignCompiler, RTLCompiler, Primetime, ETS, Talus, Tetramax, Fastscan Strong programming skills: TCL, PERL, C and assembly languages. Beginner in Java/Eclipse. Daily user of Windows, Pack Office (Excel, Word, PowerPoint…), Unix, Linux

Professional Experience October 2009 RTL Design Leader for highly complex multi-cores Application Processors ASICs (OMAP) dedicated until today to automotive/wireless/industrial applications. (3years) Texas Instruments (Villeneuve-Loubet, France)

2007 until today (5years) Texas Instruments (Villeneuve-Loubet, France)

September 2004 - October 2009 (5 years) Texas Instruments (Villeneuve-Loubet, France)

OMAP4430, OMAP4460 and OMAP543x design team leader – (45nm and 28nm process driver)  Management of the OMAP SoC Integration team (4-5 engineers).  Design of custom SoC IPs and IO pin-muxing - From specifications up to synthesis.  Integration of IPs and Subchips into System-on-Chip design.  Semi-automatic insertion of power management cells (isolation and level shifters).  ECO in Front-End and Back-End databases.  Equivalence checking (RTL to RTL, RTL to Gate and Gate to Gate) + Quality checks (Spyglass)  Leading, Planning, Reporting, Resources management, Risk assessment, Schedule tracking.  Support of synthesis, STA, RTL/gate simulations and silicon validation.  Owner of the Bugs management flow (debug, impact analysis, workaround, schedule assessment, fix).  Worldwide SoC review initiative responsibility: Regrouping RTL designers from different projects to share and cross-review automotive or wireless programs.  Leader of several cross-teams task forces (Software/Hardware/System/Test/IT) to ensure prompt problems resolution and widen overall skills.  Trained and mentored new comers. Go-to guy for all Front-End design aspects.  Recognition: Presented to 2012 TI Technical Ladder election – Process on-going. Custom design analysis tool Architect  Definition and coding of a netlist static analyzer in TCL: Clock and reset tree parser gathering information and generating custom reports (e.g. custom power management rules).  Presentations in symposiums, support, trained >30 users and ramped-up 4 trainees on development.

Verification and Design Electrical Engineer for various wireless devices within Ericsson Business Unit (jointed-design partnership)

2 projects as design team leader (team of 3-4 engineers) – (65nm)  IPs development: Planning, execution, integration, support. RTL development in Esterel language, VHDL and Verilog. DFT insertion, synthesis.  Synthesis expert: Main interface with SNPS application engineers, R&D and TI EDA team. Advanced work on Topographical and Power Management synthesis techniques. Trained >10 co-workers.  Led RTL integration for complex Subsystems and SoCs: Architecture definition, RTL, quality checks.  Provided expertise on STA constraints development: Functional/DFT modes and critical interfaces. 2 pre-study projects as design team leader – (45nm)  Managed platform definition on Multimedia (CSI, DSI, HDMI) and communication IPs (SPI, I2C...)  Trained Ericsson engineers on TI 45nm Power Management design techniques. 2 projects as verification engineer – (90nm)  RTL and gate functional simulations at SoC and subsystems levels. C and assembly coding.

February-June 2004 (6 months) Texas Instruments (Villeneuve-Loubet, France)

Internship as microelectronic engineer within the “Hardware accelerator” department  Hardware architecture study of a dynamic binary translator in order to reach high-performance software compatibility between C55x and C64x DSPs.  C-model & VHDL coding, RTL simulation and synthesis.

Education Juin 2004 (Aubière, France)

H-Master's Level Degree at Polytech’ Clermont (aka C.U.S.T.) graduating in Electrical Engineering with honor.

Interests Rugby, football, tennis and webmaster experiences (HTML, PHP)