1

2

3

4

5

6

8

7

Memory Memory.Sch

Mem_EE_SA[0..2] Mem_EE_SCL Mem_EE_SDA Mem_EE_WP

D

Virtex Virtex.Sch

PC[0..2] RESET_PHY PHY_PD NoCable

STAT[0..2] BCLK LENDIAN M8BIT MCMODE MCA MDINV DMCLK DMDONE DMERROR DMPRE DMREADY DMRW PKTFLAG CYCLEIN CYSTART RESET_LINK IRQ2

STAT[0..2] BCLK LENDIAN M8BIT MCMODE MCA MDINV DMCLK DMDONE DMERROR DMPRE DMREADY DMRW PKTFLAG CYCLEIN CYSTART RESET_LINK IRQ2

READY WR RD CS[0..4]

BOS_IO_[0..107]

BOS_IO_[0..107]

BOS_D[0..15]

C

BOS_D[0..15]

BOS_CTRL[0..9]

BOS_CTRL[0..9]

BOS_CTRL10_IO

BOS_CTRL10_IO

BOS_CTRL10_GClk

BOS_CTRL10_GClk

Clocks_Generators Clocks_Generators.Sch PLL_Serial_Data PLL_Serial_Clock PLL_Suspend

READY WR RD CS[0..4]

GLOB_RST M_CLK DONE

Mem_EE_SA[0..2] Mem_EE_SCL Mem_EE_SDA Mem_EE_WP

PC[0..2] RESET_PHY PHY_PD NoCable

C

Mem_Clock0 Mem_Clock1

A[0..6] D[0..7] DMD[0..15]

Mem_CS#[0..3] Mem_DQMB_[0..6] Mem_CAS# Mem_RAS# Mem_WE# Mem_BA_[0..1]

A[0..6] D[0..7] DMD[0..15]

Backplane Backplane.Sch Mem_DATA_[0..63] Mem_Addr_[0..12]

FireWire FireWire.Sch

B

Mem_Clock0 Mem_Clock1

D

Mem_CS#[0..3] Mem_DQMB_[0..6] Mem_CAS# Mem_RAS# Mem_WE# Mem_BA_[0..1]

Mem_DATA_[0..63] Mem_Addr_[0..12]

Power_Supply Power_Supply.Sch

GLOB_RST M_CLK

PLL_Serial_Data PLL_Serial_Clock PLL_Suspend

PLL_Ref_A

PLL_Ref_A

PLL_Ref_B

PLL_Ref_B

Global_Clock_1 Global_Clock_0

B

Global_Clock_1 Global_Clock_0

JTAG JTAG.Sch DONE A

A

Title :

Controller & FW Interface Board

Title

Drawn by Size

T.Bocquet Number

v3.2 Revision Revision

A3

mar 2002 Date : 08 Controller_v3.0.prj Date: 21-Aug-2002 File:

1

2

3

4

5

6

Sheet Sheet of C:\Projects\Controller_v3.2\Controller_v3.2_5_chips.ddb Drawn By: 7

8

1/8

1

2

3

4

5

6

7

8

A[0..6]

A[0..6]

D[0..7]

D[0..7]

DMD[0..15]

DMD[0..15]

PHY signals PC[0..2]

PC[0..2]

RESET_PHY

LENDIAN M8BIT MCMODE MCA MDINV DMCLK DMDONE

M_CLK

M_CLK

45 46 47 48 49 50

uC signals READY

READY

WR

WR

+3.3

RD

RD

R2000

CYCLEIN

1K

CS[0..4]

CS[0..4]

UP_TX UP_RX M_CLK

18 19 20 21 24 25 26 27 28 29 30 12 11 9 10 129 128

UC_TCK UC_TDI UC_TDO UC_TMS

B

UC_TRST

3 4 5 6 144

JP2000 UC_BRKIN 34 JUMP UC_BRKOUT 35 143

GND

17 130

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 T3OUT T4IN T3IN T2IN MRST MTSR TX RX BHE# SCLK CLKOUT

CS0# CS1# CS2# CS3# CS4#

DPLS DMNS TCK TDI TDO TMS TRST# BRKIN# BRKOUT# TEST

GND

DMD0 DMD1 DMD2 DMD3 DMD4 DMD5 DMD6 DMD7 DMD8 DMD9 DMD10 DMD11 DMD12 DMD13 DMD14 DMD15

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

A0 A1 A2 A3 A4 A5 A6

14 127

7 22 32 43 51 58 64 75 79 85 91 97 104 112 122 135 141 +3.3 GND GND DONE UC_BRKOUT

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

GND +3.3 15

UC_Debug

A

V6

UP_TX

11

UP_RX

9 GND +3.3

V+

C1C2+

1 12

C2010

3

GND 100n C2011

7

100n

C2T1in

T1out

R1out

R1in

EN# ForceON

J2002 DCD DSR RX RTS TX CTS DTR RI GND

GND

INVALID# ForceOFF#

13 8 10 16

J2001 +3.3

1 2 3

14

MAX3221 GND

GND

1 6 2 7 3 8 4 9 5

MCMODE M8BIT MDINV LENDIAN

46 50 51 52 48 49 77 24 23 22 21 19 18 17 99 98 97 96 94 93 92 91 89 88 87 86 84 83 82 81 14 13 11 75 12

R2004 10k +3.3

R2007

R2009

J2000 1 2 3

+3.3 1M 31

6k34

R2005 GNDCONTNDR 10k

66 67 17 22 19

NoCable LINKON LPS LREQ SCLK

DMCLK DMDONE PKTFLAG DMERROR DMPRE DMRW DMREADY

CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7

MA0 MA1 MA2 MA3 MA4 MA5 MA6

CYCLEIN DIRECT

MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15

CONTNDR MCA# MCS# MWR# TEA# BCLK RESET# STAT2 STAT1 STAT0 CYSTART INT# TESTMODE

MCMODE/SIZ1 M8BIT/SIZ0 MDINV LENDIAN COLDFIRE

64 53 74 72

1 2

R2008 0E

70 69

4 5

67 66 63 62 61 60 59 58 76

7 8 10 11 12 13 14 15 CYCLEIN

79

R2006

65

1k CONTNDR

4 7 8

MCA CS2 WR

3 6 9

BCLK Reset_LINK

56 55 54

STAT2 STAT1 STAT0

2 1 16

CYSTART IRQ2

PC0 PC1 PC2

+3.3

23 24 25

PHY_PD Reset_PHY C2012 10n

18 78 R2020 100k

ISO#

TESTM CPS

R0 R1

TPBIAS1 TPA1+ TPA1TPB1+ TPB1-

CNA C/LKON LPS LREQ SYSCLK

TPBIAS2 TPA2+ TPA2TPB2+ TPB2-

CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7

TPBIAS0 TPA0+ TPA0TPB0+ TPB0FILTER0 FILTER1

PC0 PC1 PC2

XO XI SE SM

PD RESET#

PHY2000 0

GND

26

R2010

27

1k R2011

R2012 GND 56E R2015 56E

+3.3

390

53 52 51 50 49

PWR TPA+ TPATPB+ TPBGND

7

SHIELD

C2006 C2007 10n C2005 R2019 1n 220p R2016 1M 5K GND GND GND

59 58 57 56 55

GND

B

GND C2004 1u

46 45 44 43 42

C2016 1u GND

71 72

GND

R2017 R2013 56E 56E

GND C2001 100n

C2002

77 76

R2014 GND 56E R2018 56E

GND 22p Y2000 24.576MHz C2003

32 33 R2022 R20211k 0E

1 6 5 4 3 2

CONFW2001 PWR TPA+ TPATPB+ TPBGND

7

SHIELD CON1394

C2014 C2015 10n C2013 R2024 1n 220p R2023 1M 5K GND GND GND

GND 22p

GND GND

GND

CONFW2000 1 6 5 4 3 2

CON1394

TSB41AB3

GND

GND

GND

R2033

D15

4k7 R2034

D12

4k7 TSB12LV32

A

R2035

D11

4k7 R2036

D7 GND

DB9

PAD

GND

GND

GND

R2003 R2002 56E 56E

+3.3

CONTNDR

5 25 30 45 57 73 78 90 100

C2009 100n

4 5

GND

C2008 100n

C1+

VCC

IC2000 2

Link_LAYER2000 26 DMD0 27 DMD1 28 DMD2 29 DMD3 31 DMD4 32 DMD5 33 DMD6 34 DMD7 36 DMD8 37 DMD9 38 DMD10 39 DMD11 41 DMD12 42 DMD13 43 DMD14 44 DMD15

DMCLK DMDONE PKTFLAG DMERROR DMPRE DMRW DMREADY

GND 2 4 6 8 10 12 14 16

3 2 1

C2000 1u +3.3

C165UTAH

JP2002 1 3 5 7 9 11 13 15

CS0 CS1 CS2 CS3 CS4

60 61 62 63 66 67 68 69 70 71 77 78 81 82 83 84

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

GND

UC_TMS UC_TDO UC_XTAL2 UC_TDI UC_TRST UC_TCK UC_BRKIN

117 118 119 120 121

C

124 125 126

HOLD# HLDA# BREQ#

FSC DCL DU DD

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 STAT0 STAT1 STAT2

9

PKTFLAG DMERROR NoCable

EXINT0 EXINT1 EXINT2 EXINT3 EXINT4 EXINT5 EXINT6 EXINT7

87 88 89 90 93 94 95 96 99 100 101 102 103 109 110 111 31 37 38 39 40 41 42

J2004 CS1/CS0

VDD5V

+3.3

131 132 133 134 137 138 139 140

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22

NMI#

CS1

J2003 CS0/CS1

PLLGND PLLGND

R2025 R2026 10k 10k

GLOB_RST

GLOB_RST

IRQ2

EA#

READY

74 75

DONE

1k

57 116

55 56

73

uC system DONE

GND R2001

+3.3

READY# ALE

PLLVDD

IRQ2

RSTIN# RSTOUT#

DGND DGND DGND DGND DGND DGND DGND

RESET_LINK

RESET_LINK IRQ2

114 115

CS0

79 69 68 30 29 6

DONE GLOB_RST

CS_RAM WR RD

CS1

63 62 54 48 47 35 34

CYSTART

RD WR

85 35 10

GND

53 54

95 80 71 68 47 40 20 15

7

GND

RD# WR#

VDD VDD VDD VDD VDD VDD VDD VDD

NC 16MHz

CYSTART

XTAL1 XTAL2 CLKMODE

22 29 24

GND CS0

GND GND GND GND GND GND GND GND GND

1

15 UC_XTAL2 16 13 +3.3

VDDAX VDDU

CYCLEIN

CYCLEIN

8

Out

GNDAX GNDU

Vcc

PKTFLAG

PKTFLAG

GND UC2000

Qz2000 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

+3.3 14

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

DMRW

8 23 33 44 52 59 65 76 80 86 92 98 105 113 123 136 142

DMREADY

DMREADY DMRW

D0 D1 D2 D3 D4 D5 D6 D7

16

+3.3

13 14 15 17 18 19 20 21

CY62148

16

AM29LV040

DMPRE

DMPRE

VCC

VCC

DMERROR

DMERROR

D0 D1 D2 D3 D4 D5 D6 D7

CE# WE# OE#

DVDD DVDD DVDD DVDD DVDD DVDD

DMDONE

CS_FL WR RD

A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

3 16 20 21 28 70 80

DMCLK

22 31 24

CE# WE# OE#

AVDD AVDD AVDD AVDD AVDD AVDD AVDD

MDINV

30 1 2 31 3 28 4 25 23 26 27 5 6 7 8 9 10 11 12

AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND

MCA

D0 D1 D2 D3 D4 D5 D6 D7

13 14 15 17 18 19 20 21

D0 D1 D2 D3 D4 D5 D6 D7

SRAM2000 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

36 37 38 39 40 41 60 61 64 65

MCMODE

A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

3 2 1

M8BIT

1 30 2 3 29 28 4 25 23 26 27 5 6 7 8 9 10 11 12

GND

BCLK

LENDIAN

C

A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

STAT[0..2]

BCLK

D

FLASH2000

LINK signals STAT[0..2]

+3.3

32

NoCable

NoCable

32

+3.3

PHY_PD

PHY_PD

VDD5V VDD5V VDD5V

D

GND

RESET_PHY

4k7 R2037

D6

Serial_TXRX

Title :

4k7

GND

D4

JP2001 Debug_Mode

Controller & FW Interface Board

Title

R2038 4k7

Drawn by Size

GND

T.Bocquet Number

v3.2 Revision Revision

A2

mar 2002 Date : 08 FireWire.Sch Date: 21-Aug-2002 File:

1

2

3

4

5

6

7

Sheet of C:\Projects\Controller_v3.2\Controller_v3.2_5_chips.ddb Drawn By: 8

Sheet 2/8

1

2

3

4

5

6

7

8

Memory Buses Mem_DATA_[0..63]

Mem_Addr_[0..12] D

Mem_DATA_[0..63]

Mem_Addr_[0..12] D

Memory Control signals Mem_CS#[0..3] Mem_DQMB_[0..6] Mem_CAS# Mem_RAS# Mem_WE# Mem_BA_[0..1]

Mem_Clock0 Mem_Clock1

A3000

Mem_CS#[0..3] Mem_DQMB_[0..6] Mem_CAS#

1 2 3 4 5 6 +3.3 Mem_Data_4 7 Mem_Data_5 8 Mem_Data_6 9 Mem_Data_7 10 Mem_Data_8 11 12 GND Mem_Data_9 13 Mem_Data_10 14 Mem_Data_11 15 Mem_Data_12 16 Mem_Data_13 17 18 +3.3 Mem_Data_14 19 Mem_Data_15 20 21 22 23 GND 24 25 26 +3.3 Mem_WE# 27 Mem_DQMB_0 28 Mem_DQMB_0 29 Mem_CS#0 30 31 32 GND Mem_Addr_0 33 Mem_Addr_2 34 Mem_Addr_4 35 Mem_Addr_6 36 Mem_Addr_8 37 Mem_Addr_10 38 Mem_BA_1 39 40 +3.3 41 +3.3 Mem_Clock0 42 43 GND 44 Mem_CS#2 45 Mem_DQMB_246 Mem_DQMB_247 48 49 +3.3 50 51 52 53 54 GND Mem_Data_16 55 Mem_Data_17 56 Mem_Data_18 57 Mem_Data_19 58 59 +3.3 Mem_Data_20 60 61 62 63 +3.3 64 GND Mem_Data_21 65 Mem_Data_22 66 Mem_Data_23 67 68 GND Mem_Data_24 69 Mem_Data_25 70 Mem_Data_26 71 Mem_Data_27 72 73 +3.3 Mem_Data_28 74 Mem_Data_29 75 Mem_Data_30 76 Mem_Data_31 77 78 GND Mem_Clock1 79 80 Mem_EE_WP 81 Mem_EE_SDA 82 Mem_EE_SCL 83 84 +3.3 GND Mem_Data_0 Mem_Data_1 Mem_Data_2 Mem_Data_3

Mem_CS#0 Mem_CS#1 Mem_CS#2 Mem_CS#3 Mem_DQMB_0 Mem_DQMB_2 Mem_DQMB_4 Mem_DQMB_6

Mem_RAS# Mem_WE# Mem_BA_[0..1]

Mem_Clock0 Mem_Clock1

EEPROM signals Mem_EE_SA[0..2] C

Mem_EE_SCL Mem_EE_SDA Mem_EE_WP

Mem_EE_SA[0..2] Mem_EE_SCL Mem_EE_SDA Mem_EE_WP

B

A

Vss DQ0 DQ1 DQ2 DQ3 Vdd DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 Vdd DQ14 DQ15 NC NC Vss NC NC Vdd WE# DQMB0 DQMB1 S0# DNU Vss A0 A2 A4 A6 A8 A10 BA1 Vdd Vdd CK0 Vss DNU S2# DQMB2 DQMB3 DNU Vdd NC NC NC NC Vss DQ16 DQ17 DQ18 DQ19 Vdd DQ20 NC NC CKE1 Vss DQ21 DQ22 DQ23 Vss DQ24 DQ25 DQ26 DQ27 Vdd DQ28 DQ29 DQ30 DQ31 Vss CK2 NC WP SDA SCL Vdd

Vss DQ32 DQ33 DQ34 DQ35 Vdd DQ36 DQ37 DQ38 DQ39 DQ40 Vss DQ41 DQ42 DQ43 DQ44 DQ45 Vdd DQ46 DQ47 NC NC Vss NC NC Vdd CAS# DQMB4 DQMB5 S1# RAS# Vss A1 A3 A5 A7 A9 BA0 A11 Vdd CK1 A12 Vss CKE0 S3# DQMB6 DQMB7 NC Vdd NC NC NC NC Vss DQ48 DQ49 DQ50 DQ51 Vdd DQ52 NC NC NC Vss DQ53 DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 Vdd DQ60 DQ61 DQ62 DQ63 Vss CK3 NC SA0 SA1 SA2 Vdd

85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168

GND Mem_Data_32 Mem_Data_33 Mem_Data_34 Mem_Data_35 +3.3 Mem_Data_36 Mem_Data_37 Mem_Data_38 Mem_Data_39 Mem_Data_40 GND Mem_Data_41 Mem_Data_42 Mem_Data_43 Mem_Data_44 Mem_Data_45 +3.3 Mem_Data_46 Mem_Data_47

GND C

+3.3 Mem_CAS# Mem_DQMB_4 Mem_DQMB_4 Mem_CS#1 Mem_RAS# GND Mem_Addr_1 Mem_Addr_3 Mem_Addr_5 Mem_Addr_7 Mem_Addr_9 Mem_BA_0 Mem_Addr_11 +3.3 Mem_Clock0 Mem_Addr_12 GND +3.3 Mem_CS#3 Mem_DQMB_6 Mem_DQMB_6 +3.3

B GND Mem_Data_48 Mem_Data_49 Mem_Data_50 Mem_Data_51 +3.3 Mem_Data_52

GND Mem_Data_53 Mem_Data_54 Mem_Data_55 GND Mem_Data_56 Mem_Data_57 Mem_Data_58 Mem_Data_59 +3.3 Mem_Data_60 Mem_Data_61 Mem_Data_62 Mem_Data_63 GND Mem_Clock1 Mem_EE_SA0 Mem_EE_SA1 Mem_EE_SA2

A

Title :

+3.3

Controller & FW Interface Board

Title

SDRAM_SIMM

Drawn by Size

T.Bocquet Number

v3.2 Revision Revision

A3

mar 2002 Date : 08 Memory.Sch Date: 21-Aug-2002 File:

1

2

3

4

5

6

Sheet Sheet of C:\Projects\Controller_v3.2\Controller_v3.2_5_chips.ddb Drawn By: 7

8

3/8

1

2

3

4

5

6

7

8

9

10

12

11

Global FW buses A[0..6]

A[0..6]

Memory Buses

D[0..7]

D[0..7]

Mem_DATA_[0..63]

DMD[0..15]

DMD[0..15]

Mem_DATA_[0..63]

Mem_Addr_[0..12]

PC[0..2] RESET_PHY PHY_PD NoCable

PC[0..2]

Mem_CS#[0..3]

RESET_PHY

Mem_DQMB_[0..6]

PHY_PD

Mem_CAS#

NoCable

Mem_RAS#

Mem_CS#[0..3] Mem_DQMB_[0..6] Mem_CAS# Mem_RAS#

Mem_WE#

D

Mem_BA_[0..1]

LINK signals STAT[0..2]

STAT[0..2]

Mem_Clock0

BCLK

BCLK

Mem_Clock1

LENDIAN

LENDIAN

M8BIT

M8BIT

Mem_EE_SA[0..2] Mem_Data_51 Mem_Data_18 Mem_Data_50 Mem_Data_17 Mem_Data_49 Mem_Data_16 Mem_Data_48 Mem_DQMB_2 Mem_DQMB_6 Mem_CS#2 Mem_CS#3 Mem_Addr_12 Mem_Clock0 Mem_BA_1 Mem_Addr_11 Mem_Addr_10 Mem_BA_0 Mem_Addr_8 Mem_Addr_9 Mem_Addr_6 Mem_Addr_7 Mem_Addr_4 Mem_Addr_5 Mem_Addr_2 Mem_Addr_3 Mem_Addr_0 Mem_Addr_1 Mem_RAS# Mem_CS#0 Mem_CS#1 Mem_DQMB_0 Mem_DQMB_4 Mem_WE# Mem_CAS# Mem_Data_15 Mem_Data_47 Mem_Data_14 Mem_Data_46 Mem_Data_13 Mem_Data_45 Mem_Data_12 Mem_Data_44 Mem_Data_11 Mem_Data_43 Mem_Data_10 Mem_Data_42 Mem_Data_9 Mem_Data_41 Mem_Data_8 Mem_Data_40 Mem_Data_7 Mem_Data_39 Mem_Data_6 Mem_Data_38 Mem_Data_5 Mem_Data_37 Mem_Data_4 Mem_Data_36 Mem_Data_3 Mem_Data_35 Mem_Data_2 Mem_Data_34 Mem_Data_1 Mem_Data_33 Mem_Data_0 Mem_Data_32 BOS_IO_54 BOS_IO_27 BOS_IO_0 BOS_D0 BOS_IO_28 BOS_IO_1 BOS_D1 BOS_IO_81

MCA MDINV

MDINV

DMCLK

DMCLK

DMDONE

DMDONE

DMERROR

DMERROR

Mem_WE#

D

Mem_BA_[0..1]

Mem_Clock0 Mem_Clock1

EEPROM signals

MCMODE

MCMODE MCA

Mem_EE_SCL Mem_EE_SDA

Mem_EE_SA[0..2] Mem_EE_SCL Mem_EE_SDA

Mem_EE_WP

Mem_EE_WP

E28 E29 E30 E31 F28 F29 F31 G28 G29 G30 H28 H29 H30 H31 J28 J29 J30 K28 K30 K31 L29 L30 M28 M29 M30 M31 N28 N30 N31 P28 P29 P30 R28 R29 R30 R31 T30 T31 U28 U29 U30 U31 V28 V29 V30 W28 W29 W30 Y28 Y29 Y30 Y31 AA29 AA30 AB28 AB29 AB31 AC28 AC29 AC30 AD28 AD29 AD30 AD31 AE28 AE30 AF28 AF29 AF30 AF31 AG28 AG29 AG30 AG31

DMPRE

DMPRE

DMREADY

DMREADY

IC5000A

CYCLEIN

CYCLEIN

CYSTART

CYSTART

STAT2 D0 D6 CYSTART DMD3 DMD0 DMD8

RESET_LINK

RESET_LINK

IRQ2

IRQ2

M_CLK

uC system

PKTFLAG Mem_EE_SA1 Mem_Data_63 Mem_Data_60 Mem_Data_57 Mem_Data_55 Mem_Data_21 STAT0 D1 D4 D7 MCA A6 A3 A2 A5 A0 DMD4 DMD10 DMD14 DMPRE DMD13 DMD15 Mem_EE_SA2 Mem_EE_SDA Mem_Data_31 Mem_Data_28 Mem_Data_26 Mem_Data_23 Mem_Data_54 Mem_Data_53 READY D3 IRQ2 BCLK WR RESET_LINK DMD2 A4 DMD5 DMD11 DMD9 DMRW Mem_EE_SCL Mem_EE_SA0 Mem_Clock1 Mem_Data_62 Mem_Data_61 Mem_Data_59 Mem_Data_25 Mem_Data_56 Mem_Data_22 Mem_Data_52 NoCable CYCLEIN STAT1 RD D2 D5 DMREADY M8BIT DMD1 MCMODE A1 DMD6 DMD7

DONE

DONE

GLOB_RST

GLOB_RST

M_CLK

M_CLK

uC signals READY

READY

WR

WR

RD

RD

CS[0..4]

CS[0..4]

!! 2 times Mem_Clock !!

DMCLK

DMD12 DMERROR DMDONE Mem_EE_WP Mem_Data_30 Mem_Data_29 Mem_Data_27 Mem_Data_58 Mem_Data_24 Mem_Data_20 Mem_Data_19

B

A4 A5 A6 A8 A12 A13 A15 A16 A19 A20 A22 A24 A26 A27 A28 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B24 B25 B27 B28 B29 C5 C6 C8 C9 C10 C11 C12 C13 C15 C16 C17 C18 C20 C21 C22 C23 C24 C25 C26 C27 C28 C30 D1 D2 D3 D5 D6 D7 D8 D9 D10 D12 D13 D14 D15 D17 D18 D19 D20 D22 D23 D24 D25 D26 D27 D30 D31

IO_L32N_Y IO_L30N_YY IO_L28P_YY IO_L26N_Y IO IO_VREF_L19P_YY IO_L17N_Y GCK2 IO_L13P_YY IO_L12N_YY IO IO_L8P_YY IO IO_L4P_YY IO_L2P_YY IO_WRITE_L33N_YY IO_L31N_YY IO_L29N_Y IO_VREF_L27P_YY IO_L26P_Y IO IO_L24N_YY IO IO_L21P_YY IO_L20N_YY IO_L19N_YY IO_L17P_Y IO_LVDS_DLL_L16P IO_L15P_Y IO_L14N_Y IO_VREF_L13N_YY IO IO_L11N_YY IO_L9P_YY IO_L7P_Y IO_L6N_Y IO_L3N_Y IO_L1N_YY IO_L0N_Y IO_L32P_Y IO_VREF_L30P_YY IO_L27N_YY IO_L25N_Y IO_VREF_L24P_YY IO_L23P_YY IO_L22P_YY IO_L21N_YY IO_L18N_Y IO IO_LVDS_DLL_L16N IO_VREF_L15N_Y IO_L11P_YY IO_L10N_YY IO_L9N_YY IO IO_VREF_L7N_Y IO_L5P_YY IO_L3P_Y IO_L1P_YY IO IO IO_L36P_Y IO_L35P IO_DOUT_BUSY_L34P_YY IO_CS_L33P_YY IO_L31P_YY IO_L29P_Y IO_L28N_YY IO IO_VREF_L25P_Y IO_L23N_YY IO_L22N_YY IO_L20P_YY IO_L18P_Y GCK3 IO_L14P_Y IO_L12P_YY IO_L10P_YY IO_VREF_L8N_YY IO_L6P_Y IO_VREF_L5N_YY IO_L4N_YY IO_VREF_L2N_YY IO_L0P_Y IO_L135P_Y IO_L135N_Y

IO_VREF_L72P_YY IO_L74P_YY IO_L75N_YY IO_VREF_L78P_YY IO_L79N_YY IO IO_VREF_L83P_YY IO GCK0 IO_LVDS_DLL_L86N IO_L89P_YY IO_L90N_YY IO_L93N_YY IO_VREF_L95N_Y IO_L98P_YY IO_L99N_Y IO_L101N_YY IO_L69N_YY IO_L70N_Y IO_L72N_YY IO_L74N_YY IO IO_VREF_L77P_Y IO_L78N_YY IO_L79P_YY IO_L80N_YY IO_L81N_YY IO_L83N_YY IO_VREF_L85P_Y GCK1 IO_L87P_Y IO_L88N_Y IO_L91P_YY IO_L92N_YY IO_VREF_L94N_YY IO_L96P_Y IO_L97P_YY IO_L98N_YY IO_VREF_L100N_YY IO_L102N_Y IO_L69P_YY IO_L71P_YY IO_L73P_Y IO_VREF_L75P_YY IO_L76N_Y IO_L77N_Y IO IO_L81P_YY IO_L82N_YY IO_L84N_Y IO_L85N_Y IO_VREF_L87N_Y IO_VREF_L89N_YY IO IO_L92P_YY IO_L93P_YY IO_L94P_YY IO IO IO_VREF_L97N_YY IO_L100P_YY IO_L102P_Y IO_L103N_YY IO_L66N_Y IO_L67P IO_L70P_Y IO_L71N_YY IO_L73N_Y IO_L76P_Y IO IO_L80P_YY IO_L82P_YY IO_L84P_Y IO_LVDS_DLL_L86P IO_L88P_Y IO_L90P_YY IO_L91N_YY IO IO_L95P_Y IO_L96N_Y IO_L99P_Y IO_L101P_YY IO_L103P_YY IO_L104P

Virtex 600 E - BG432

IO part

AL4 AL5 AL6 AL8 AL10 AL12 AL13 AL15 AL16 AL17 AL19 AL20 AL22 AL24 AL26 AL27 AL28 AK3 AK4 AK5 AK6 AK7 AK8 AK9 AK10 AK11 AK12 AK14 AK15 AK16 AK17 AK18 AK20 AK21 AK23 AK24 AK25 AK26 AK27 AK28 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ11 AJ12 AJ13 AJ14 AJ15 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ30 AH1 AH2 AH5 AH6 AH7 AH9 AH10 AH12 AH13 AH14 AH15 AH17 AH18 AH19 AH20 AH22 AH23 AH25 AH26 AH30 AH31

BOS_IO_97 BOS_CTRL0 BOS_IO_15 BOS_D14 BOS_IO_93 BOS_IO_65 BOS_D11 BOS_IO_63 BOS_IO_89 BOS_IO_61 BOS_IO_87 BOS_IO_86 BOS_IO_58 BOS_IO_3 BOS_IO_56 BOS_IO_2 BOS_IO_44 BOS_CTRL1 BOS_IO_16 BOS_IO_42 BOS_IO_68 BOS_IO_14 BOS_IO_40 BOS_D13 BOS_IO_39 BOS_IO_92 BOS_IO_37 BOS_IO_90 BOS_D9 BOS_IO_8 BOS_D7 BOS_IO_33 BOS_IO_5 BOS_IO_85 BOS_D4 BOS_IO_30 BOS_IO_83 BOS_IO_29 BOS_IO_17 BOS_IO_43 BOS_IO_69 BOS_IO_95 BOS_IO_41 BOS_IO_67 BOS_IO_66 BOS_D12 BOS_IO_11 BOS_IO_64 BOS_D10 BOS_IO_9 BOS_IO_35 BOS_IO_88 BOS_IO_7 BOS_IO_60 BOS_D6 BOS_IO_32 BOS_D5 BOS_IO_4 BOS_IO_57 BOS_D3 BOS_D2 BOS_IO_98 BOS_IO_71 BOS_IO_70 BOS_IO_96 BOS_D15 BOS_IO_94 BOS_IO_13 BOS_IO_12 BOS_IO_38 BOS_IO_91 BOS_IO_10 BOS_IO_36 BOS_IO_62 BOS_D8 BOS_IO_34 BOS_IO_6 BOS_IO_59 BOS_IO_31 BOS_IO_84 BOS_IO_82 BOS_IO_55

Global_Clock_1

C

Global_Clock_0 BOS_CTRL10_GClk

J4000 1 2 3 GClk/BosClk

Backplane Signals

BOS_IO_[0..107] BOS_D[0..15] BOS_CTRL[0..9]

BOS_CTRL10_IO BOS_CTRL10_GClk

BOS_IO_[0..107] BOS_D[0..15] BOS_CTRL[0..9]

BOS_CTRL10_IO BOS_CTRL10_GClk

B

IO_L38P IO_VREF_L37P_Y IO_L36N_Y IO_L35N IO_L39P_Y IO_L38N IO_L37N_Y IO_L40N_YY IO_VREF_L40P_YY IO_L39N_Y IO_VREF_L42P_Y IO_L41N_Y IO_L41P_Y IO IO_VREF_L43P_YY IO IO_L42N_Y IO_L44N_YY IO_D2_L44P_YY IO_D1_L43N_YY IO_L45P_Y IO IO IO_L46N_Y IO_L46P_Y IO_L45N_Y IO_VREF_L48P_YY IO_L47N_Y IO_L47P_Y IO_L49N_Y IO_L49P_Y IO_D3_L48N_YY IO_L51P_YY IO IO_VREF_L50P_Y IO_L50N_Y IO IO_L51N_YY IO_L53P_Y IO_VREF_L52N_Y IO IO_L52P_Y IO_VREF_L54N_YY IO_L53N_Y IO_D4_L54P_YY IO IO_L55P_Y IO_L55N_Y IO_L56P_Y IO_L57N_Y IO_L56N_Y IO_L57P_Y IO IO_L58P_YY IO_D5_L58N_YY IO_D6_L59P_YY IO_VREF_L59N_YY IO IO_VREF_L60N_Y IO_L61P_Y IO_L60P_Y IO_L61N_Y IO_L62P_YY IO_VREF_L62N_YY IO IO_L63N_Y IO_L64P IO_L63P_Y IO_VREF_L65N_Y IO_L66P_Y IO_L64N IO_L65P_Y IO_L67N IO_D7_L68P_YY

PKTFLAG

PKTFLAG

IO_L136P IO_L136N IO_L133P IO_L133N IO_VREF_L134P_Y IO_L134N_Y IO_VREF_L131P_YY IO_L132P_Y IO_L132N_Y IO_L130P_Y IO_L131N_YY IO IO_L130N_Y IO IO_VREF_L129P_Y IO_L129N_Y IO_VREF_L128P_YY IO_L128N_YY IO_L127P_YY IO_L127N_YY IO IO_L126P_Y IO_L125P_Y IO_L125N_Y IO_L126N_Y IO IO_L124N_Y IO_VREF_L123P_YY IO_L124P_Y IO_L122P_Y IO_L122N_Y IO_L123N_YY IO IO_L120P_YY IO_L121N_Y IO_VREF_L121P_Y IO IO_L120N_YY IO_VREF_L119N_Y IO_L118P_Y IO_L119P_Y IO IO_VREF_L117N_YY IO_L117P_YY IO_L118N_Y IO IO_L116N_Y IO_L116P_Y IO_L114N_Y IO_L114P_Y IO_L115N_Y IO_L115P_Y IO_L113P_YY IO IO_VREF_L112N_YY IO_L112P_YY IO_L113N_YY IO_VREF_L111N_Y IO_L111P_Y IO IO_L109P_YY IO IO_L110N_Y IO_L110P_Y IO_L108N_Y IO_VREF_L109N_YY IO_VREF_L106N_Y IO_L107N IO_L107P IO_L108P_Y IO_L104N IO_L105N_Y IO_L105P_Y IO_L106P_Y

DMRW

DMRW

C

Mem_Addr_[0..12]

Memory Control signals

PHY signals

BOS_IO_53 BOS_IO_80 BOS_IO_107 BOS_IO_79 BOS_IO_106 BOS_CTRL10_IO BOS_IO_26 BOS_IO_25 BOS_IO_52 BOS_IO_51 BOS_IO_78 BOS_IO_105 BOS_CTRL9 BOS_IO_104 BOS_CTRL8 BOS_IO_24 BOS_IO_23 BOS_IO_50 BOS_IO_77 BOS_IO_49 BOS_IO_76 BOS_IO_103 BOS_CTRL7 BOS_CTRL6 BOS_IO_22 BOS_IO_48 BOS_IO_75 BOS_IO_102 BOS_IO_101 BOS_CTRL5 BOS_IO_21 BOS_CTRL4 BOS_IO_20 BOS_IO_47 BOS_IO_74 BOS_IO_46 BOS_IO_73 BOS_IO_100 BOS_IO_99 BOS_CTRL3 BOS_IO_19 BOS_CTRL2 BOS_IO_18 BOS_IO_45 BOS_IO_72

Back_LED

Con_GP_IO_0 Con_GP_IO_1 Con_GP_IO_2 Con_GP_IO_3 Con_GP_IO_4 Con_GP_IO_5 Con_GP_IO_6 Con_GP_IO_7 Front_LED_0 Front_LED_1

CS0 CS2 GLOB_RST CS1 MDINV CS3 PC0 CS4 PC1 LENDIAN PC2 PHY_PD RESET_PHY PLL_Serial_Data PLL_Ref_A PLL_Ref_B PLL_Serial_Clock PLL_Suspend

E1 E2 E3 E4 F2 F3 F4 G2 G3 G4 H1 H2 H3 H4 J2 J3 J4 K1 K2 K4 L2 L3 M1 M2 M3 M4 N1 N3 N4 P2 P3 P4 R1 R2 R3 R4 T2 T3 U1 U2 U3 U4 V2 V3 V4 W1 W3 W4 Y1 Y2 Y3 Y4 AA2 AA3 AB1 AB3 AB4 AC2 AC3 AC4 AD1 AD2 AD3 AD4 AE2 AE3 AE4 AF2 AF3 AF4 AG1 AG2 AG3 AG4

XCV300-600E-BG432

D4002 R4015 300E

D4000 GND

Clock Generation Signals

300E

PLL_Suspend

GND

PLL_Serial_Data

300E LED_SMD

PLL_Serial_Clock PLL_Suspend PLL_Ref_A

PLL_Ref_A

PLL_Ref_B

Global_Clock_0 Global_Clock_1

R4016 R4017 120E R4018 120E R4019 120E R4020 120E R4021 120E R4022 120E R4023 120E 120E

R4002 R4003 R4004 R4005 R4006 R4007 R4008 R4009 10k10k10k10k10k10k10k10k

Con_GP_IO_R_0 Con_GP_IO_R_1 Con_GP_IO_R_2 Con_GP_IO_R_3 Con_GP_IO_R_4 Con_GP_IO_R_5 Con_GP_IO_R_6 Con_GP_IO_R_7

Global_Clock_0

2 4 6 8 10 12 14 16

PLL_Ref_B

Con_GP_IO_0 Con_GP_IO_1 Con_GP_IO_2 Con_GP_IO_3 Con_GP_IO_4 Con_GP_IO_5 Con_GP_IO_6 Con_GP_IO_7

Global_Clock_1

A

JP4000 Generics IO

1 3 5 7 9 11 13 15

A

+3.3

R4001

Con_GP_IO_R_0 Con_GP_IO_R_1 Con_GP_IO_R_2 Con_GP_IO_R_3 Con_GP_IO_R_4 Con_GP_IO_R_5 Con_GP_IO_R_6 Con_GP_IO_R_7

PLL_Serial_Clock

R4000

LED_SMD D4001

PLL_Serial_Data

GND LED_SMD

GND

Title :

Controller & FW Interface Board

Title

Drawn by Size

T.Bocquet Number

v3.2 Revision Revision

A1

mar 2002 Date : 08 Virtex.Sch Date: 21-Aug-2002 File:

1

2

3

4

5

6

7

8

9

10

11

Sheet of C:\Projects\Controller_v3.2\Controller_v3.2_5_chips.ddb Drawn By: 12

Sheet 4/8

1

2

3

4

5

6

8

7

Backplane Signals

BOS_IO_[0..107]

BOS_IO_[0..107] BOS_D[0..15]

BOS_D[0..15]

D

D BOS_CTRL[0..9]

BOS_CTRL10_IO BOS_CTRL10_GClk

BOS_CTRL[0..9]

BOS_CTRL10_IO BOS_CTRL10_GClk

P5000 BACKPLANE_5

C

J5001

Global Clock

B

3 2 1

BOS_CTRL10_GClk BOS_CTRL10_IO

BOS_D0 BOS_D1 BOS_D2 BOS_D3 BOS_D4 BOS_D5 BOS_D6 BOS_D7 BOS_D8 BOS_D9 BOS_D10 BOS_D11 BOS_D12 BOS_D13 BOS_D14 BOS_D15 BOS_CTRL0 BOS_CTRL1 BOS_CTRL2 BOS_CTRL3 BOS_CTRL4 BOS_CTRL5 BOS_CTRL6 BOS_CTRL7 BOS_CTRL8 BOS_CTRL9 BOS_CTRL10

+5 GND +12 -12 AGND R5000A R5001B 39E R5002C 39E R5003D 39E R5005A 39E R5006B 39E R5007C 39E R5008D 39E R5010A 39E R5011B 39E R5012C 39E R5013D 39E R5015A 39E R5016B 39E R5017C 39E R5018D 39E R5020A 39E R5021B 39E R5022C 39E R5023D 39E R5025A 39E R5026B 39E R5027C 39E R5028D 39E R5030A 39E R5031B 39E R5032C 39E 39E

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32

BOS_IO_0 BOS_IO_1 BOS_IO_2 BOS_IO_3 BOS_IO_4 BOS_IO_5 BOS_IO_6 BOS_IO_7 BOS_IO_8 BOS_IO_9 BOS_IO_10 BOS_IO_11 BOS_IO_12 BOS_IO_13 BOS_IO_14 BOS_IO_15 BOS_IO_16 BOS_IO_17 BOS_IO_18 BOS_IO_19 BOS_IO_20 BOS_IO_21 BOS_IO_22 BOS_IO_23 BOS_IO_24 BOS_IO_25 BOS_IO_26

+5 GND +12 -12 AGND R5000B R5001C 39E R5002D 39E R5004A 39E R5005B 39E R5006C 39E R5007D 39E R5009A 39E R5010B 39E R5011C 39E R5012D 39E R5014A 39E R5015B 39E R5016C 39E R5017D 39E R5019A 39E R5020B 39E R5021C 39E R5022D 39E R5024A 39E R5025B 39E R5026C 39E R5027D 39E R5029A 39E R5030B 39E R5031C 39E R5032D 39E 39E

C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32

BOS_IO_27 BOS_IO_28 BOS_IO_29 BOS_IO_30 BOS_IO_31 BOS_IO_32 BOS_IO_33 BOS_IO_34 BOS_IO_35 BOS_IO_36 BOS_IO_37 BOS_IO_38 BOS_IO_39 BOS_IO_40 BOS_IO_41 BOS_IO_42 BOS_IO_43 BOS_IO_44 BOS_IO_45 BOS_IO_46 BOS_IO_47 BOS_IO_48 BOS_IO_49 BOS_IO_50 BOS_IO_51 BOS_IO_52 BOS_IO_53

+5 GND +12 -12 AGND R5000C R5001D 39E R5003A 39E R5004B 39E R5005C 39E R5006D 39E R5008A 39E R5009B 39E R5010C 39E R5011D 39E R5013A 39E R5014B 39E R5015C 39E R5016D 39E R5018A 39E R5019B 39E R5020C 39E R5021D 39E R5023A 39E R5024B 39E R5025C 39E R5026D 39E R5028A 39E R5029B 39E R5030C 39E R5031D 39E R5033A 39E 39E

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32

BOS_IO_54 BOS_IO_55 BOS_IO_56 BOS_IO_57 BOS_IO_58 BOS_IO_59 BOS_IO_60 BOS_IO_61 BOS_IO_62 BOS_IO_63 BOS_IO_64 BOS_IO_65 BOS_IO_66 BOS_IO_67 BOS_IO_68 BOS_IO_69 BOS_IO_70 BOS_IO_71 BOS_IO_72 BOS_IO_73 BOS_IO_74 BOS_IO_75 BOS_IO_76 BOS_IO_77 BOS_IO_78 BOS_IO_79 BOS_IO_80

+5 GND +12 -12 AGND R5000D R5002A 39E R5003B 39E R5004C 39E R5005D 39E R5007A 39E R5008B 39E R5009C 39E R5010D 39E R5012A 39E R5013B 39E R5014C 39E R5015D 39E R5017A 39E R5018B 39E R5019C 39E R5020D 39E R5022A 39E R5023B 39E R5024C 39E R5025D 39E R5027A 39E R5028B 39E R5029C 39E R5030D 39E R5032A 39E R5033B 39E 39E

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32

BOS_IO_81 BOS_IO_82 BOS_IO_83 BOS_IO_84 BOS_IO_85 BOS_IO_86 BOS_IO_87 BOS_IO_88 BOS_IO_89 BOS_IO_90 BOS_IO_91 BOS_IO_92 BOS_IO_93 BOS_IO_94 BOS_IO_95 BOS_IO_96 BOS_IO_97 BOS_IO_98 BOS_IO_99 BOS_IO_100 BOS_IO_101 BOS_IO_102 BOS_IO_103 BOS_IO_104 BOS_IO_105 BOS_IO_106 BOS_IO_107

+5 GND +12 -12 AGND R5001A R5002B 39E R5003C 39E R5004D 39E R5006A 39E R5007B 39E R5008C 39E R5009D 39E R5011A 39E R5012B 39E R5013C 39E R5014D 39E R5016A 39E R5017B 39E R5018C 39E R5019D 39E R5021A 39E R5022B 39E R5023C 39E R5024D 39E R5026A 39E R5027B 39E R5028C 39E R5029D 39E R5031A 39E R5032B 39E R5033C 39E 39E

Z1 Z2 Z3 Z4 Z5 Z6 Z7 Z8 Z9 Z10 Z11 Z12 Z13 Z14 Z15 Z16 Z17 Z18 Z19 Z20 Z21 Z22 Z23 Z24 Z25 Z26 Z27 Z28 Z29 Z30 Z31 Z32

C

B

2 1

BosGClk/BosIO

J5000 Clock_Loop

A

A

Title :

Controller & FW Interface Board

Title

Drawn by Size

T.Bocquet Number

v3.2 Revision Revision

A3

mar 2002 Date : 08 Backplane.Sch Date: 21-Aug-2002 File:

1

2

3

4

5

6

Sheet Sheet of C:\Projects\Controller_v3.2\Controller_v3.2_5_chips.ddb Drawn By: 7

8

5/8

1

2

3

4

5

6

8

7

R6002

D

+5

U6001 C6015 100u

GND

1 4 5

C6016 100n GND

R6001 GND 1k

IN OUT FB ON/OFF

LM2596T-ADJ(5)

+1.8

L6002

2

33uH

C6017 100u

D6001 30BQ015 GND

GND

+ C6003 100u

C6001 10u

Supply6000 RT6000

GND GND

C6018 100n

GND 0/100k GND depopulate RT6000 for 350KHz

28 27 26

C6002 47n

GND

GND GND

GND

+ C6005 100u

25 R6000

C6004 100n +5

4

10k

3

GND

2

VIN VIN VIN VIN VIN

C6000 10u

24 23 22 21 20

+5

463

RT

C6006 47n

SYNC SS/ENA VBIAIS PWRGD COMP VSENSE

C6027 100n

C6029 100n

C6031 100n

C6033 100n

C6035 100n

C6037 100n

C6039 100n

C6041 100n

C6043 100n

C6045 100n

GND

C6022 100n

C6024 100n

C6026 100n

C6028 100n

C6030 100n

C6009 10u GND

C6010 10u GND

GND

15 16 17 18 19

0

1

+1.8 C6020 100n

+ C6008 100u

TPS54616

1.8 Volts 0603 Cap

C

6uH

PGND PGND PGND PGND PGND

C6025 100n

PowerPAD

C6023 100n

AGND

C6021 100n

+3.3

L6000

6 7 8 9 10 11 12 13 14

PH PH PH PH PH PH PH PH PH

+1.8 C6019 100n

D

5

BOOT

GND C6032 100n

C6034 100n

C6036 100n

C6038 100n

C6040 100n

C6042 100n

C6044 100n

C6046 100n

C6061 100n

C6063 100n

C6065 100n

C6067 100n

C6069 100n

C6071 100n

C6073 100n

C

GND

+3.3 C6049 100n

C6047 100n

C6051 100n

C6053 100n

C6055 100n

C6057 100n

C6059 100n

C6075 100n

C6077 100n

+5

U6000 C6011 100u

GND +3.3 C6050 100n

C6048 100n

C6052 100n

C6054 100n

C6056 100n

C6058 100n

GND C6060 100n

C6062 100n

C6064 100n

C6066 100n

C6068 100n

C6070 100n

C6072 100n

C6074 100n

C6076 100n

1 4 5

C6012 100n GND

GND

IN OUT FB ON/OFF LM2596T3.3(5)

+3.3

L6001

2

33uH

C6013 100u

D6000 30BQ015

C6014 100u

GND

GND

C6078 100n GND

GND +3.3

B C6081 100n

C6079 100n

C6083 100n

C6085 100n

C6087 100n

C6089 100n

B C6091 100n

C6093 100n

C6095 100n

C6097 100n

C6099 100n

C6101 100n

C6103 100n

C6105 100n

C6107 100n

C6109 100n

C6094 100n

C6096 100n

C6098 100n

C6100 100n

C6102 100n

C6104 100n

C6106 100n

C6108 100n

C6110 100n

C6118 100n

C6119 100n

C6120 100n

C6121 100n

C6122 100n

C6123 100n

C6124 100n

C6125 100n

C6126 100n

3.3 Volts 0603 Cap

GND +3.3 C6082 100n

C6080 100n

C6084 100n

C6086 100n

C6088 100n

C6090 100n

C6092 100n

GND

+3.3

A

C6112 100n

C6111 100n

C6113 100n

C6114 100n

C6115 100n

C6116 100n

C6117 100n

GND

3.3 Volts 1206 Cap

+3.3 C6128 100n

C6127 100n

C6129 100n

C6130 100n

C6131 100n

C6132 100n

C6133 100n

A

C6134 100n

C6135 100n

C6136 100n

C6137 100n

C6138 100n

C6139 100n

C6140 100n

C6141 100n

Title :

Controller & FW Interface Board

Title

Drawn by Size

C6142 100n

File:

2

v3.2 Revision Revision

mar 2002 Date : 08 Power_Supply.Sch Date: 21-Aug-2002

GND 1

T.Bocquet Number

A3

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A1 AL1 A11 AL11 L28 L31 A21 AL21 A31 AL31 L1 L4 AA28 AA31 C3 AJ3 AA1 AA4 C29 AJ29 D11 AH11 D21 AH21

+3.3 +1.8

VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT

D

J7000 M0 M1 M2 TDO CCLK IO_DIN_D0_L34N_YY TDI TCK TMS

Virtex 600 E - BG432

Power part

GND

AH28 AH29 GND AJ28

IO_INIT_L68N_YY DONE PROGRAM

BOOT +3.3

C4 D4 C2 B3 D28 D29

TCK TMS

AJ2

INIT

AH4

DONE

AH3

PROG

CCLK XV_D0

AK29 AH27

DXP DXN

1 2

+3.3 R7000 4k7

+3.3 R7001 300E R7002 4k7

S7000 Reset

DXP DXN

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

D

A10 F1 AK13 AE29 A17 AK19 AK22 AB30 K3 W31 AJ10 N2 AJ16 T29 T1 B23 B26 N29 W2 C7 AH8 K29 C14 AB2 C19 AH24 F30 AF1

VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO

IC5000B

GND

C

C

AE31 AL2 AL3 A2 A3 A7 AC31 A9 AL7 AE1 A14 A18 AL9 A23 A25 A29 A30 B1 B2 AL14 AC1 AL18 AL23 AL25 AL29 V31 AL30 AK1 AK2 V1 T28 T4 P31 P1 AK30 J31 B30 AK31 B31 AJ1 C1 G31 J1 AJ31 G1 AH16 C31 D16

XCV300-600E-BG432

Power Pins of the Virtex

GND

CCLK

XV_D0 +3.3

34 35 36 37 38 39 40 41 42 43 44

GND

GND

34 35 36 37 38 39 40 41 42 43 44

+3.3

DONE used for Rest

CCLK

XV_D0

1 2

J7001 Bypass 2nd PROM

D1 GND D3 Vcco D5

TMS GND TCK Vcco D4 CF#

TMS GND

TCK

+3.3

GND +3.3

PROG

D0 GND D2 CLK

Vcc

33 32 31 30 29 28 27 26 25 24 23

Vcc Vcco

D0 GND D2 CLK

Vcc

TDI

1 2 3 4 5 6 7 8 9 10 11

TDO

TDI

D1 GND D3 Vcco D5

TMS GND TCK Vcco D4 CF#

D7 GND Vcc Vcco CE# D6 OE/nReset

+3.3

TDO

IC7001

CEO#

GND

33 32 31 30 29 28 27 26 25 24 23

D7 GND Vcc Vcco CE# D6 OE/nReset

DONE

DONE

CEO#

B

Vcc Vcco

IC7000

100E

TMS GND

TCK

+3.3 PROG

+3.3

R7003

TMS TDO

R7004

TCK

R7005

J7002

B

1 2 3 4 5 6

GND

100E

XV_JTAG

100E

XC18VXX_Slave

INIT

GND +3.3 INIT

GND +3.3 DONE

TDI

22 21 20 19 18 17 16 15 14 13 12

22 21 20 19 18 17 16 15 14 13 12

XC18VXX_Master

1 2 3 4 5 6 7 8 9 10 11

A

A

Title :

Controller & FW Interface Board

Title

Drawn by Size

T.Bocquet Number

v3.2 Revision Revision

A3

mar 2002 Date : 08 JTAG.Sch Date: 21-Aug-2002 File:

1

2

3

4

5

6

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Clock Generation Signals PLL_Serial_Data

PLL_Serial_Data

PLL_Serial_Clock

PLL_Serial_Clock

PLL_Suspend

PLL_Suspend

PLL_Ref_A

PLL_Ref_A

D

PLL_Ref_B

PLL_Ref_B

Global_Clock_0

Global_Clock_0

Global_Clock_1

New Clock Generator

Old Clock Generator with its own power supply

+12

RG8000 3

Y8000

IN

1

OUT

C8001 100n

78L05 +3.3

5

1 2 3 4

8 7 6 5 SW DIP-4

12 13

+3.3

15 16

13

2

PLL8001

VDD XBUF

XTALOUT SDAT SCLK SUSPEND# POWERDOWN# AGND

PLL_Serial_Data PLL_Serial_Clock PLL_Suspend

GND

PLL8000 XTALIN

XTAL 14,31818MHz S8000

GND

CLKA CLKB CLKC CLKD CLKE

PLL_Ref_A PLL_Ref_B

6 10 9 1 7 8

R8002 R8003 33E 33E

Global_Clock_0 Global_Clock_1

Y8002

15 2 5 6 7

XTAL 14,31818MHz

PLL_Serial_Data 16 PLL_Serial_Clock12 PLL_Suspend 1

GND

4

AVDD

Y8001 C

14

CRYSTAL

C8002 100n

MUXREFA# MUXREFB#

VCC

Global_Clock_1

XTALIN XTALOUT XBUF DATA SCLKA SCLKB

OEB CLKB

14 11 10 9

R8000

Global_Clock_0

39E

3 8

R8001

Global_Clock_1

39E

ICD2051

11

4

CY22393 3

OEA CLKA/4 CLKA/2 CLKA

C

GND

D

GND

GND

B

B

A

A

Title :

Controller & FW Interface Board

Title

Drawn by Size

T.Bocquet Number

v3.2 Revision Revision

A3

mar 2002 Date : 08 Clocks_Generators.Sch Date: 21-Aug-2002 File:

1

2

3

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