CD4051B, CD4052B, CD4053B August 1998 - Revised January 2003

Data sheet acquired from Harris Semiconductor SCHS047F

Features • Wide Range of Digital and Analog Signal Levels - Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V - Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20VP-P

[ /Title • Low ON Resistance, 125Ω (Typ) Over 15VP-P Signal Input Range for VDD -VEE = 18V (CD405 • High OFF Resistance, Channel Leakage of ±100pA (Typ) 1B, CD4052 at VDD -VEE = 18V • Logic-Level Conversion for Digital Addressing Signals of B, to 20V (VDD -VSS = 3V to 20V) to Switch Analog CD4053 3V Signals to 20VP-P (VDD -VEE = 20V) B) • Matched Switch Characteristics, rON = 5Ω (Typ) for /SubVDD -VEE = 15V ject Low Quiescent Power Dissipation Under All Digital(CMOS • Very Control Input and Supply Conditions, 0.2µW (Typ) at Analog VDD -VSS = VDD -VEE = 10V Multi- • Binary Address Decoding on Chip plexers/Dem • 5V, 10V, and 15V Parametric Ratings ultiplex- • 100% Tested for Quiescent Current at 20V ers with • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range, 100nA at 18V and 25oC Logic Level • Break-Before-Make Switching Eliminates Channel Overlap Conversion) /Author Applications • Analog and Digital Multiplexing and Demultiplexing () /Key• A/D and D/A Conversion words • Signal Gating (Harris CMOS Analog Multiplexers/Demultiplexers Semiconduc- with Logic Level Conversion tor, The CD4051B, CD4052B, and CD4053B analog multiplexers CD4000 are digitally-controlled analog switches having low ON

The CD4051B is a single 8-Channel multiplexer having three binary control inputs, A, B, and C, and an inhibit input. The three binary signals select 1 of 8 channels to be turned on, and connect one of the 8 inputs to the output. The CD4052B is a differential 4-Channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input signals select 1 of 4 pairs of channels to be turned on and connect the analog inputs to the outputs. The CD4053B is a triple 2-Channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole, double-throw configuration. When these devices are used as demultiplexers, the “CHANNEL IN/OUT” terminals are the outputs and the “COMMON OUT/IN” terminals are the inputs.

Ordering Information PART NUMBER

TEMP. RANGE (oC)

PACKAGE

CD4051BF3A, CD4052BF3A, CD4053BF3A

-55 to 125

16 Ld CERAMIC DIP

CD4051BE, CD4052BE, CD4053BE

-55 to 125

16 Ld PDIP

CD4051BM, CD4051BM96 CD4052BM, CD4052BM96, CD4053BM, CD4053BM96

-55 to 125

16 Ld SOIC

CD4051BNSR, CD4052BNSR, CD4053BNSR

-55 to 125

16 Ld SOP

CD4051BPW, CD4051BPWR, CD4052BPW, CD4052BPWR CD4053BPW, CD4053BPWR

-55 to 125

16 Ld TSSOP

NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel.

impedance and very low OFF leakage current. Control of analog signals up to 20VP-P can be achieved by digital signal amplitudes of 4.5V to 20V (if VDD -VSS = 3V, a VDD -VEE of up to 13V can be controlled; for VDD -VEE level differences above 13V, a VDD -VSS of at least 4.5V is required). For example, if VDD = +4.5V, VSS = 0V, and VEE = -13.5V, analog signals from -13.5V to +4.5V can be controlled by digital inputs of 0V to 5V. These multiplexer circuits dissipate extremely low quiescent power over the full VDD -VSS and VDD -VEE supply-voltage ranges, independent of the logic state of the control signals. When a logic “1” is present at the inhibit input terminal, all channels are off. 1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated

CD4051B, CD4052B, CD4053B Pinouts CD4051B (PDIP, CDIP, SOIC, SOP, TSSOP) TOP VIEW 4 1

16 VDD

6 2

15 2

COM OUT/IN 3

14 1

7 4

13 0

CHANNELS IN/OUT

CD4052B (PDIP, CDIP, SOP, TSSOP) TOP VIEW 0 1

16 VDD

2 2

15 2

COMMON “Y” OUT/IN 3

14 1

Y CHANNELS IN/OUT

X CHANNELS IN/OUT

CHANNELS IN/OUT CHANNELS IN/OUT

Y CHANNELS IN/OUT

3 4

13 COMMON “X” OUT/IN

5 5

12 3

1 5

12 0

INH 6

11 A

INH 6

11 3

VEE 7

10 B

VEE 7

10 A

VSS 8

9 C

VSS 8

9 B

X CHANNELS IN/OUT

CD4053B (PDIP, CDIP, SOP, TSSOP) TOP VIEW

IN/OUT

by 1

16 VDD

bx 2

15 OUT/IN bx OR by

cy 3

14 OUT/IN ax OR ay

OUT/IN CX OR CY 4

13 ay

IN/OUT CX 5

12 ax

INH 6

11 A

VEE 7

10 B

VSS 8

9 C

IN/OUT

Functional Block Diagrams CD4051B CHANNEL IN/OUT

16 VDD

7

6

5

4

3

2

1

0

4

2

5

1

12

15

14

13 TG

TG A

†

11 TG

B

†

10 LOGIC LEVEL CONVERSION

C

†

9

INH

†

6

BINARY TO 1 OF 8 DECODER WITH INHIBIT

TG

3 TG

TG

TG

TG

8 VSS

7 VEE

† All inputs are protected by standard CMOS protection network.

2

COMMON OUT/IN

CD4051B, CD4052B, CD4053B Functional Block Diagrams

(Continued) CD4052B X CHANNELS IN/OUT 3

2

1

0

11

15

14

12

TG 16 VDD

A

†

10

B

†

9

INH

†

6

TG

BINARY TO 1 OF 4 DECODER WITH INHIBIT

LOGIC LEVEL CONVERSION

TG

COMMON X OUT/IN

TG

13

TG TG

3 COMMON Y OUT/IN

TG TG

8 VSS

7

VEE

1

5

2

4

0

1

2

3

Y CHANNELS IN/OUT

CD4053B

LOGIC LEVEL CONVERSION

16 VDD

BINARY TO 1 OF 2 DECODERS WITH INHIBIT

IN/OUT cy

cx

by

bx

ay

ax

3

5

1

2

13

12 TG

COMMON OUT/IN ax OR ay 14

A

†

11

TG

TG

COMMON OUT/IN bx OR by 15

B

C

†

†

10

TG

TG

9

4 TG

INH

†

COMMON OUT/IN cx OR cy

6

VDD

8

VSS

7

VEE

† All inputs are protected by standard CMOS protection network.

3

CD4051B, CD4052B, CD4053B TRUTH TABLES INPUT STATES INHIBIT

C

B

A

“ON” CHANNEL(S)

0

0

0

0

0

0

0

0

1

1

0

0

1

0

2

0

0

1

1

3

0

1

0

0

4

0

1

0

1

5

0

1

1

0

6

0

1

1

1

7

1

X

X

X

None

CD4051B

CD4052B INHIBIT

B

A

0

0

0

0x, 0y

0

0

1

1x, 1y

0

1

0

2x, 2y

0

1

1

3x, 3y

1

X

X

None

CD4053B INHIBIT

A OR B OR C

0

0

ax or bx or cx

0

1

ay or by or cy

1

X

None

X = Don’t Care

4

CD4051B, CD4052B, CD4053B Absolute Maximum Ratings

Thermal Information

Supply Voltage (V+ to V-) Voltages Referenced to VSS Terminal . . . . . . . . . . . -0.5V to 20V DC Input Voltage Range . . . . . . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . ±10mA

Package Thermal Impedance, θJA (see Note 1): PDIP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W SOIC package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W SOP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W TSSOP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W Maximum Junction Temperature (Ceramic Package) . . . . . . . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265oC (SOIC - Lead Tips Only)

Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. Common Conditions Here: If Whole Table is For the Full Temp. Range, VSUPPLY = ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified (Note 3)

Electrical Specifications

LIMITS AT INDICATED TEMPERATURES (oC)

CONDITIONS

25 PARAMETER

VIS (V)

VEE (V)

VSS (V)

VDD (V)

-55

-40

85

125

MIN

TYP

MAX

UNITS

SIGNAL INPUTS (VIS) AND OUTPUTS (VOS) -

-

-

5

5

5

150

150

-

0.04

5

µA

-

-

-

10

10

10

300

300

-

0.04

10

µA

-

-

-

15

20

20

600

600

-

0.04

20

µA

-

-

-

20

100

100

3000

3000

-

0.08

100

µA

-

0

0

5

800

850

1200

1300

-

470

1050

Ω

-

0

0

10

310

330

520

550

-

180

400

Ω

-

0

0

15

200

210

300

320

-

125

240

Ω

Change in ON Resistance (Between Any Two Channels), ∆rON

-

0

0

5

-

-

-

-

-

15

-

Ω

-

0

0

10

-

-

-

-

-

10

-

Ω

-

0

0

15

-

-

-

-

-

5

-

Ω

OFF Channel Leakage Current: Any Channel OFF (Max) or ALL Channels OFF (Common OUT/IN) (Max)

-

0

0

18

-

±0.01

±100 (Note 2)

nA

Capacitance:

-

-5

5-

5

Quiescent Device Current, IDD Max

Drain to Source ON Resistance rON Max 0 ≤ VIS ≤ VDD

Input, CIS

±100 (Note 2)

±1000 (Note 2)

-

-

-

-

-

5

-

pF

CD4051

-

-

-

-

-

30

-

pF

CD4052

-

-

-

-

-

18

-

pF

CD4053

-

-

-

-

-

9

-

pF

-

-

-

-

-

0.2

-

pF

5

-

-

-

-

-

30

60

ns

10

-

-

-

-

-

15

30

ns

15

-

-

-

-

-

10

20

ns

Output, COS

Feedthrough CIOS Propagation Delay Time (Signal Input to Output

VDD

5

RL = 200kΩ, CL = 50pF, tr , tf = 20ns

CD4051B, CD4052B, CD4053B Common Conditions Here: If Whole Table is For the Full Temp. Range, VSUPPLY = ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified (Continued) (Note 3)

Electrical Specifications

LIMITS AT INDICATED TEMPERATURES (oC)

CONDITIONS

25 PARAMETER

VIS (V)

VEE (V)

VSS (V)

VDD (V)

-55

-40

85

125

MIN

TYP

MAX

UNITS

5

1.5

1.5

1.5

1.5

-

-

1.5

V

10

3

3

3

3

-

-

3

V

15

4

4

4

4

-

-

4

V

5

3.5

3.5

3.5

3.5

3.5

-

-

V

10

7

7

7

7

7

-

-

V

15

11

11

11

11

11

-

-

V

±0.1

µA

CONTROL (ADDRESS OR INHIBIT), VC Input Low Voltage, VIL , Max

VIL = VDD through 1kΩ; VIH = VDD through Input High Voltage, VIH , 1kΩ Min

Input Current, IIN (Max)

VEE = VSS , RL = 1kΩ to VSS , IIS < 2µA on All OFF Channels

VIN = 0, 18

18

±0.1

±0.1

±1

±1

-

±10-5

Propagation Delay Time: Address-to-Signal tr , tf = 20ns, OUT (Channels ON or CL = 50pF, OFF) See Figures 10, RL = 10kΩ 11, 14

0

0

5

-

-

-

-

-

450

720

ns

0

0

10

-

-

-

-

-

160

320

ns

0

0

15

-

-

-

-

-

120

240

ns

-5

0

5

-

-

-

-

-

225

450

ns

0

0

5

-

-

-

-

-

400

720

ns

0

0

10

-

-

-

-

-

160

320

ns

0

0

15

-

-

-

-

-

120

240

ns

-10

0

5

-

-

-

-

-

200

400

ns

0

0

5

-

-

-

-

-

200

450

ns

0

0

10

-

-

-

-

-

90

210

ns

0

0

15

-

-

-

-

-

70

160

ns

-10

0

5

-

-

-

-

-

130

300

ns

-

-

-

-

-

5

7.5

pF

Propagation Delay Time: Inhibit-to-Signal OUT tr , tf = 20ns, (Channel Turning ON) CL = 50pF, See Figure 11 RL = 1kΩ

Propagation Delay Time: Inhibit-to-Signal OUT (Channel Turning OFF) See Figure 15

tr , tf = 20ns, CL = 50pF, RL = 10kΩ

Input Capacitance, CIN (Any Address or Inhibit Input) NOTE:

2. Determined by minimum feasible leakage measurement for automatic testing.

Electrical Specifications TEST CONDITIONS PARAMETER

VIS (V)

VDD (V)

RL (kΩ)

Cutoff (-3dB) Frequency Channel ON (Sine Wave Input)

5 (Note 3)

10

1

VOS at Common OUT/IN

VEE = VSS , V OS 20Log ------------ = – 3dB V IS

6

VOS at Any Channel

LIMITS TYP

UNITS

CD4053

30

MHz

CD4052

25

MHz

CD4051

20

MHz

60

MHz

CD4051B, CD4052B, CD4053B Electrical Specifications TEST CONDITIONS

LIMITS

PARAMETER

VIS (V)

VDD (V)

RL (kΩ)

TYP

UNITS

Total Harmonic Distortion, THD

2 (Note 3)

5

10

0.3

%

3 (Note 3)

10

0.2

%

5 (Note 3)

15

0.12

%

VEE = VSS, fIS = 1kHz Sine Wave -40dB Feedthrough Frequency (All Channels OFF)

5 (Note 3)

10

1

VOS at Common OUT/IN

CD4053

8

MHz

CD4052

10

MHz

CD4051

12

MHz

VOS at Any Channel

8

MHz

Between Any 2 Channels

3

MHz

Between Sections, CD4052 Only

Measured on Common

6

MHz

Measured on Any Channel

10

MHz

Between Any Two Sections, CD4053 Only

In Pin 2, Out Pin 14

2.5

MHz

In Pin 15, Out Pin 14

6

MHz

10 (Note 4)

65

mVPEAK

VEE = 0, VSS = 0, tr , tf = 20ns, VCC = VDD - VSS (Square Wave)

65

mVPEAK

VEE = VSS , V OS 20Log ------------ = – 40dB V IS

-40dB Signal Crosstalk Frequency

%

5 (Note 3)

10

1

VEE = VSS , V OS 20Log ------------ = – 40dB V IS

Address-or-Inhibit-to-Signal Crosstalk

-

10

NOTES: V DD – V EE ----------------------------2

3. Peak-to-Peak voltage symmetrical about 4. Both ends of channel.

Typical Performance Curves 300 VDD - VEE = 10V

VDD - VEE = 5V

rON , CHANNEL ON RESISTANCE (Ω)

rON , CHANNEL ON RESISTANCE (Ω)

600

500

400 TA = 125oC

300

TA = 25oC

200

TA = -55oC 100

0 -4

-3

-2

-1

0

1

2

3

4

VIS , INPUT SIGNAL VOLTAGE (V)

FIGURE 1. CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES)

7

5

250 TA = 125oC

200

150 TA = 25oC 100 TA = -55oC 50

0 -10

-7.5

-5 -2.5 0 2.5 5 VIS , INPUT SIGNAL VOLTAGE (V)

7.5

FIGURE 2. CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES)

10

CD4051B, CD4052B, CD4053B Typical Performance Curves

(Continued)

600

250 rON , CHANNEL ON RESISTANCE (Ω)

rON , CHANNEL ON RESISTANCE (Ω)

TA = 25oC VDD - VEE = 5V

500 400 300 200

10V 15V

100 0 -10

-7.5

-5

-2.5

0

2.5

5

7.5

VDD - VEE = 15V 200

TA = 125oC

150 TA = 25oC

100

TA = -55oC 50

0 -10

10

-7.5

-5

FIGURE 3. CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES)

PD , POWER DISSIPATION PACKAGE (µW)

100Ω

-2

-4

-2 0 2 4 VIS , INPUT SIGNAL VOLTAGE (V)

TA = 25oC ALTERNATING “O” AND “I” PATTERN CL = 50pF

f

VDD = 15V 103 VDD = 10V 102

VDD = 5V CL = 15pF

10 1

10

TEST CIRCUIT VDD

CD4029 VDD B/D A B 100Ω 10 9 1 3 CL 13 5 12 2 4 CD4052 14 15 6 11 7 8

Ι

102 103 104 SWITCHING FREQUENCY (kHz)

105

FIGURE 7. DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD4052B)

8

VDD = 5V

10

B/D CD4029 A B C

VDD 100Ω 11 10 9 13 14 15 12 CD4051 1 5 3 2 48 7 6 C L 100Ω

Ι

CL = 15pF 1

100Ω

PD , POWER DISSIPATION PACKAGE (µW)

VDD = 10V

10

6

FIGURE 5. ON CHARACTERISTICS FOR 1 OF 8 CHANNELS (CD4051B)

104

7.5

f

VDD = 15V

102

-4

10

102 103 104 SWITCHING FREQUENCY (kHz)

105

FIGURE 6. DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD4051B)

PD , POWER DISSIPATION PACKAGE (µW)

VOS , OUTPUT SIGNAL VOLTAGE (V)

1kΩ 500Ω

103

-6

5

TEST CIRCUIT VDD

TA = 25oC ALTERNATING “O” AND “I” PATTERN CL = 50pF 104

RL = 100kΩ, RL = 10kΩ

0

105

2.5

105

VDD = 5V VSS = 0V VEE = -5V TA = 25oC

2

-6

0

FIGURE 4. CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES)

6

4

-2.5

VIS , INPUT SIGNAL VOLTAGE (V)

VIS , INPUT SIGNAL VOLTAGE (V)

105

TA = 25oC ALTERNATING “O” AND “I” PATTERN CL = 50pF

104

103

VDD = 5V

102

CL = 15pF

VDD = 15V VDD = 10V TEST CIRCUIT VDD f 9 4 CL 100Ω 3 12 5 13 100Ω CD4053 2 10 1 15 11 14 6 7 8

Ι

10 1

10

102 103 104 SWITCHING FREQUENCY (kHz)

105

FIGURE 8. DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD4053B)

CD4051B, CD4052B, CD4053B Test Circuits and Waveforms VDD = 15V

VDD = 7.5V

VDD = 5V

VDD = 5V

5V

7.5V 16

5V

16

16

16

VSS = 0V

VSS = 0V

VSS = 0V VEE = 0V

7 8

VEE = -7.5V

7 8

VEE = -10V

7 8

7 8

VEE = -5V

VSS = 0V (D)

(C)

(B)

(A)

NOTE: The ADDRESS (digital-control inputs) and INHIBIT logic levels are: “0” = VSS and “1” = VDD. The analog signal (through the TG) may swing from VEE to VDD. FIGURE 9. TYPICAL BIAS VOLTAGES

tr = 20ns

tr = 20ns

tf = 20ns

90% 50%

90% 50%

10%

tf = 20ns

90% 50%

90% 50% 10%

10%

10% TURN-ON TIME 90% 50%

90% 10%

10%

10% TURN-OFF TIME

TURN-OFF TIME

FIGURE 10. WAVEFORMS, CHANNEL BEING TURNED ON (RL = 1kΩ)

FIGURE 11. WAVEFORMS, CHANNEL BEING TURNED OFF (RL = 1kΩ)

VDD

VDD

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9 CD4051

IDD

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9 CD4052

VDD

IDD

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9 CD4053

FIGURE 12. OFF CHANNEL LEAKAGE CURRENT - ANY CHANNEL OFF

9

TURN-ON TIME

tPHZ

IDD

CD4051B, CD4052B, CD4053B Test Circuits and Waveforms (Continued) VDD

1 2 3 4 5 6 7 8

IDD

VDD

16 15 14 13 12 11 10 9

1 2 3 4 5 6 7 8

IDD

VDD

16 15 14 13 12 11 10 9

1 2 3 4 5 6 7 8

CD4052

CD4051

16 15 14 13 12 11 10 9

IDD

CD4053

FIGURE 13. OFF CHANNEL LEAKAGE CURRENT - ALL CHANNELS OFF

VDD 1 2 3 4 5 6 7 8

VDD

VEE VSS

16 15 14 13 12 11 10 9

OUTPUT

VDD

OUTPUT

OUTPUT

1 RL CL 2 RL CL 3 VDD VEE 4 VDD 5 VEE 6 VEE VSS CLOCK 7 IN 8 VSS

VSS

CD4051

16 15 14 13 12 11 10 9

VDD

VEE

VDD

VSS CLOCK VSS IN VSS

CD4052

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9 CD4053

RL

CL VEE

VDD

VSS CLOCK IN VSS

FIGURE 14. PROPAGATION DELAY - ADDRESS INPUT TO SIGNAL OUTPUT

VDD

OUTPUT RL

1 2 3 4 5 6 7 8

50pF VEE

VDD VSS

VDD CLOCK VEE IN VSS

16 15 14 13 12 11 10 9

VDD

OUTPUT 50pF

RL

VEE VDD VSS

VDD CLOCK VEE IN VSS

tPHL AND tPLH VSS CD4051

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

OUTPUT RL

50pF VEE VDD

VDD VSS CLOCK VEE IN VSS

V tPHL AND tPLH SS CD4052

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

VDD

V tPHL AND tPLH SS CD4053

FIGURE 15. PROPAGATION DELAY - INHIBIT INPUT TO SIGNAL OUTPUT VDD

VIH

1K

VIH VIL

VDD

VDD

µA

1K

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

VIH VIL

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

1K

1K

µA VIH

1K

VIL VIH

VIL

MEASURE < 2µA ON ALL “OFF” CHANNELS (e.g., CHANNEL 6)

1K

µA

VIH VIL

VIL MEASURE < 2µA ON ALL “OFF” CHANNELS (e.g., CHANNEL 2x)

MEASURE < 2µA ON ALL “OFF” CHANNELS (e.g., CHANNEL by)

FIGURE 16. INPUT VOLTAGE TEST CIRCUITS (NOISE IMMUNITY)

10

16 15 14 13 12 11 10 9

CD4053B

CD4052B

CD4051B

1 2 3 4 5 6 7 8

CD4051B, CD4052B, CD4053B Test Circuits and Waveforms (Continued) VDD

VDD 1 2 3 4 5 6 7 8 Ι

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9 Ι

CD4051 CD4053

VDD

16 15 14 13 12 11 10 9

KEITHLEY 160 DIGITAL MULTIMETER TG “ON”

10kΩ

X-Y PLOTTER

FIGURE 18. CHANNEL ON RESISTANCE MEASUREMENT CIRCUIT

VDD 1 2 3 4 5 6 7 8

VDD Ι VSS

CD4051 CD4053

VSS

X

H.P. MOSELEY 7030A

CD4052

VDD 16 15 14 13 12 11 10 9

Y

VSS

FIGURE 17. QUIESCENT DEVICE CURRENT

1 2 3 4 5 6 7 8

1kΩ RANGE

VSS

16 15 14 13 12 11 10 9

VDD Ι VSS

CD4052

NOTE: Measure inputs sequentially, to both VDD and VSS connect all unused inputs to either VDD or VSS .

NOTE: Measure inputs sequentially, to both VDD and VSS connect all unused inputs to either VDD or VSS .

FIGURE 19. INPUT CURRENT

5VP-P

CHANNEL ON 5VP-P

OFF CHANNEL VDD

RF VM

RL

1K

RL

RL

RL

FIGURE 20. FEEDTHROUGH (ALL TYPES)

FIGURE 21. CROSSTALK BETWEEN ANY TWO CHANNELS (ALL TYPES)

CHANNEL IN Y ON OR OFF

CHANNEL IN X ON OR OFF RL

RF VM RL

FIGURE 22. CROSSTALK BETWEEN DUALS OR TRIPLETS (CD4052B, CD4053B)

11

RF VM

CHANNEL ON

RF VM

CHANNEL OFF

6 7 8

5VP-P

COMMON

CHANNEL OFF

CD4051B, CD4052B, CD4053B Test Circuits and Waveforms (Continued) DIFFERENTIAL SIGNALS

CD4052

CD4052

COMMUNICATIONS LINK

DIFF. AMPLIFIER/ LINE DRIVER

DIFF. MULTIPLEXING

DIFF. RECEIVER

DEMULTIPLEXING

FIGURE 23. TYPICAL TIME-DIVISION APPLICATION OF THE CD4052B

Special Considerations In applications where separate power sources are used to drive VDD and the signal inputs, the VDD current capability should exceed VDD/RL (RL = effective external load). This provision avoids permanent current flow or clamp action on the VDD supply when power is applied or removed from the CD4051B, CD4052B or CD4053B.

A B CD4051B C INH

A B C

D E

Q0

A B E

1/2 CD4556

A B CD4051B C INH

Q1 Q2

A B CD4051B C INH

FIGURE 24. 24-TO-1 MUX ADDRESSING

12

COMMON OUTPUT

CD4051B, CD4052B, CD4053B

13

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