Addressing the Challenge of Backside Circuit Edit of Wafer Level Chip
Addressing the Challenge of Backside Circuit Edit of Wafer Level Chip Scale Packages by T Lundquist, D Di Donato, T Malik (Credence Systems). Backside edit ...
Addressing the Challenge of Backside Circuit Edit of Wafer Level Chip Scale Packages by T Lundquist, D Di Donato, T Malik (Credence Systems)
Backside edit has become commonplace at IDMs and even at some CE (circuit edit) service houses. For packaged devices only die down BGA type devices have been problematic due to access to the silicon. As can be readily understood, small die which require direct attach to a printed circuit board (PCB) may present a challenge to circuit edit. This direct use of bare die is a major trend in manufacturing electronic systems, as it decreases the number of process steps and thus reduces cost. (Die costs are generally less than a traditional package.) A package is no longer present—the die is the package (WL-CSP). Another driver to WL-CSP is the PCB real estate—smaller is better everywhere.
Example of Wafer Level-Chip Scale Package (optical image) showing
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