CONTENTS SAFETY PRECAUTIONS:................................................................................................................................................................ 2
• •
TV set switched off........................................................................................................................ 2 Measurements ............................................................................................................................... 2
PERI-TV SOCKET.............................................................................................................................................................................. 2 • SCART 1 ......................................................................................................................................... 2 1. INTRODUCTION ........................................................................................................................................................................... 3
2. SMALL SIGNAL PART WITH STV2248 .................................................................................... 3 • • • • • • • •
2.1 Vision IF amplifier...................................................................................................................................................................3 2.2 QSS Sound circuit (QSS versions).......................................................................................................................................3 2.3 AM demodulator ...................................................................................................................................................................3 2.4 FM demodulator ....................................................................................................................................................................3 2.5 Video switch............................................................................................................................................................................4 2.6 Synchronisation circuit..........................................................................................................................................................4 2.7 Chroma and luminance processing......................................................................................................................................4 2.8 RGB output circuit ..................................................................................................................................................................5 • 2.9 µ-Controller................................................................................................................................. 6 3. TUNER.............................................................................................................................................................................................. 6 5. SOUND OUTPUT STAGE TDA7496.......................................................................................................................................... 7 6. VERTICAL OUTPUT STAGE WITH TDA8174A.................................................................................................................... 7 7. VIDEO OUTPUT AMPLIFIER STV5114................................................................................................................................... 7 8. POWER SUPPLY (SMPS)............................................................................................................................................................ 7 10. SERIAL ACCESS CMOS 8K EEPROM 24C08..................................................................................................................... 7 12. SAW FILTERS ............................................................................................................................................................................. 7 13. IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM................................................................................................ 8 • ST92195.........................................................................................................................................................................................8 • STV224X .....................................................................................................................................................................................10 • UV1316, UV1336.........................................................................................................................................................................11 • TDA7496.....................................................................................................................................................................................12 • TDA8174.....................................................................................................................................................................................13 • STV5114 ......................................................................................................................................................................................13 • MC44608 .....................................................................................................................................................................................14 • 24CO8 ..........................................................................................................................................................................................15 • SAW FILTERS...........................................................................................................................................................................16 GENERAL BLOCK DIAGRAM of 11AK46.................................................................................................................................17 Service menu ....................................................................................................................................................................................18 Options................................................................................................................................................................................................19 Languages ..........................................................................................................................................................................................22
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DO NOT CHANGE ANY MODULE UNLESS THE SET IS SWITCHED OFF The mains supply part of the switch mode power supply’s transformer is live. Use an isolating transformer. The receiver complies with the safety requirements. SAFETY PRECAUTIONS: The service of this TV set must be carried out by qualified persons only. Components marked with the warning symbol on the circuit diagram are critical for safety and must only be replaced with an identical component. - Power resistor and fused resistors must be mounted in an identical manner to the original component. - When servicing this TV, check that the EHT does not exceed 26kV. TV set switched off: Make short-circuit between HV-CRT clip and CRT ground layer. Short C809 before changing IC800 or other components in primary side of the SMPS part. Measurements: Voltage readings and oscilloscope traces are measured under the following conditions: Antenna signal’s level is 60dB at the color bar pattern from the TV pattern generator. (100% white, 75% color saturation) Brightness, contrast, and color are adjusted for normal picture performance. Mains supply, 220VAC, 50Hz.
PERI-TV SOCKET
- The figure of PERI-TV socket-
SCART 1 PINING 1 Audio right output 2 Audio right input 3 Audio left output 4 Ground AF 5 Ground Blue 6 Audio left input 7 Blue input 8 AV switching input 9 Ground Green 10 11 Green input 12 13 Ground Red 14 Ground Blanking 15 Red input 16 Blanking input 17 Ground CVBS output 18 Ground CVBS input
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0.5Vrms / 1K 0.5Vrms / 10K 0.5Vrms / 1K
0.5Vrms / 10K 0.7Vpp / 75ohm 0-12VDC /10K
0.7Vpp / 75ohm
0.7Vpp / 75ohm 0-0.4VDC, 1-3VDC / 75 Ohm
2
19 CVBS output 20 CVBS input 21 Ground
1Vpp / 75ohm 1Vpp / 75ohm
1. INTRODUCTION 11AK46 is a 90° chassis capable of driving 14” tubes at the appropriate currents. The chassis is capable of operating in PAL, SECAM and NTSC standards. The sound system is capable of giving 3,5 watt RMS output into a load of 8 ohms. One page, 7 page SIMPLETEXT, TOPTEXT, FASTTEXT and US Closed Caption is also provided. The chassis is equipped with a 42 pin Scart connector. 2. SMALL SIGNAL PART WITH STV2248: STV2248 video processor is essential for realizing all small signal functions for a color TV receiver. 2.1 Vision IF amplifier3 The vision IF amplifier can demodulate signals with positive and negative modulation. The PLL demodulator is completely alignment-free. Although the VCO (Toko-coil) of the PLL circuit is external, yet the frequency is fixed to the required value by the original manufacturer thus the Toko-coil does not need to be adjusted manually. The setting of the various frequencies (38.9 or 45.75 MHz) can be made via changing the coil itself. 2.2 QSS Sound circuit (QSS versions) The sound IF amplifier is similar to the vision IF amplifier and has an external AGC de-coupling capacitor. The single reference QSS mixer is realised by a multiplier. In this multiplier the SIF signal is converted to the inter-carrier frequency by mixing it with the regenerated picture carrier from the VCO. The mixer output signal is supplied to the output via a high-pass filter for attenuation of the residual video signals. With this system a high performance hi-fi stereo sound processing can be achieved. The AM sound demodulator is realised by a multiplier. The modulated sound IF signal is multiplied in phase with the limited SIF signal. The demodulator output signal is supplied to the output via a low-pass filter for attenuation of the carrier harmonics. The AM signal is supplied to the output via the volume control. 2.3 AM DEMODULATOR The AM demodulated signal results from multiplying the input signal by itself, it is available on AM/FM output. 2.4 FM demodulator and audio amplifier : The FM demodulator is realized as narrow-band PLL with external loop filter, which provides the necessary selectivity without using an external band-pass filter. To obtain a good selectivity a linear phase detector and constant input signal amplitude are required. For this reason the inter-carrier signal is internally supplied to the demodulator via a gain controlled amplifier and AGC circuit. The nominal frequency of the demodulator is tuned to the required frequency (4.5/5.5/6.0/6.5 MHz) by means of a calibration circuit that uses the clock frequency of the µ-controller/Teletext decoder as a reference. The setting to the wanted frequency is realized by means of the software. It can be read whether the PLL frequency is inside or outside the window and whether the PLL is in lock or not. With this information it is possible to make an automatic search system for the incoming sound frequency. This is realized by means
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of a software loop that alternate the demodulator to various frequencies, then select the frequency on which a lock condition has been found. De-emphasis output signal amplitude is independent of the TV standard and has the same value for a frequency deviation of ±25 kHz at the 4.5 MHz standard and for a deviation of ±50 kHz for the other standards. When the IF circuit is switched to positive modulation the internal signal on de-emphasis pin is automatically muted. The audio control circuit contains an audio switch and volume control. In the mono inter-carrier sound versions the Automatic Volume Leveling (AVL) function can be activated. The pin to which the external capacitor has to be connected depends on the IC version. For the 90° types the capacitor is connected to the EW output pin (pin 20). When the AVL is active it automatically stabilizes the audio output signal to a certain level. 2.5 Video switching The video processor (STV2248C) has three CVBS inputs and two RGB inputs. The first CVBS input is used for external CVBS from SCART 1, the second is used for either CVBS or Y/C from BAV/FAV, and the third one is used for internal video. The selection between both external video inputs signals is realized by means of software and hardware switches. 2.6 Synchronization circuit The video processor (STV224X) performs the horizontal and vertical processing. The external horizontal deflection circuit is controlled via the Horizontal output pulse (HOUT). The vertical scanning is performed through an external ramp generator and a vertical power amplifier IC controlled by the Vertical output pulse (VOUT). The main components of the deflection circuit are: • PLL1: the first phase locked loop that locks the internal line frequency reference on the CVBS input signal. It is composed of an integrated VCO (12 MHz) that requires the chroma Reference frequency (4.43MHz or 3.58MHz crystal oscillator reference signal), a divider by 768, a line decoder, and a phase comparator. • PLL2: The second phase locked loop that controls the phase of the horizontal output (Compensation of horizontal deflection transistor storage time variation). Also the horizontal position adjustment is also performed in PLL2. • A vertical pulse extractor. • A vertical countdown system to generate all vertical windows (vertical synchronization window, frame blanking pulses, 50/60Hz identification window...). • Automatic identification of 50/60Hz scanning. • PLL1 time constant control. • Noise detector, video identification circuits, and horizontal coincidence detector. • Vertical output stage including de-interlace function, vertical position control. • Vertical amplitude control voltage output (combined with chroma reference output and Xtal 1 indication). 2.7 Chroma and luminance processing: The chroma decoder is able to demodulate PAL, NTSC and SECAM signals. The decoder dedicated to PAL and NTSC sub-carrier is based on a synchronous demodulator, and an Xtal PLL locked on the phase reference signal (burst). The SECAM demodulation is based on a PLL with automatic calibration loop. The color standard identification is based on the burst recognition. Automatic and forced modes can be selected through the I2C bus.
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NTSC tint, and auto flesh are controlled through I2C bus. Xtal PLL can handle up to 3 crystals to work in PAL M, PAL N and NTSC M for South America. ACC an ACC overload control the chroma sub-carrier amplitude within 26dB range. Both ACC s are based on digital systems and do not need external capacitor. All chroma filters are fully integrated and tuned via a PLL locked on Xtal VCO signal. A second PLL is used for accurate fine-tuning of the SECAM bell filter. This tuning is achieved during the frame blanking. An external capacitor memorizes the bell filter tuning voltage. A base-band chroma delay-line rebuilds the missing color line in SECAM and removes transmission phase errors in PAL. The base-band chroma delay line is clocked with 6MHz signal provided by the horizontal scanning VCO. The luminance processor is composed of a chroma trap filter, a luminance delay line, a peaking function with noise coring feature, a black stretch circuit. Trap filter and luminance delay lines are achieved with the use of bi-quad integrated filters, auto-aligned via a master filter phase locked loop. 2.8 RGB output circuit: The video processor performs the R, G, B processing. There are three sources: 1. Y,U,V inputs (coming from luma part (Y output), and chroma decoder outputs (R-Y, B-Y outputs). 2. External R,G,B inputs from SCART (converted internally in Y,U,V), with also the possibility to input YUV signals from a DVD player, (YUV specification is Y=0.7 V PP , U= 0.7 V PP , V = 0.7V PP for 100% color bar). 3. Internal R,G,B inputs (for OSD and Teletext display) The main functions of the video part are: - Y,U,V inputs with integrated clamp loop, allowing a DC link with YUV outputs, - External RGB inputs (RGB to YUV conversion), or direct YUV inputs, - Y,U,V switches, - Contrast, saturation, brightness controls, - YUV to RGB matrix, - OSD RGB input stages (with contrast control), - RGB switches, - APR function, - DC adjustment of red and green channels, - Drive adjustments (R, G, B gain), - Digital automatic cut-off loop control, - Manual cut-off capability with I2C adjustments, - Half tone, oversize blanking, external insertion detection, blue screen, - Blanking control and RGB output stages.
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2.9 µ-Controller The ST92195 is the micro-controller, which is required for a color TV receiver. ST92195D1 is the version with one page Teletext and ST92195D7 is the one with 7 page Teletext. The IC has the supply voltages of 5 V and they are mounted in PSDIP package with 56 pins. µ-Controller has the following features • Display of the program number, channel number, TV Standard, analogue values, sleep timer, parental control and mute is done by OSD • Single LED for standby and on mode indication • System configuration with service mode • 3 level logic output for SECAM and Tuner band switching 3. TUNER PLL tuner is used as a tuner.
Channel coverage of UV1316:
BAND Low Band Mid Band High Band
OFF-AIR CHANNELS CHANNELS FREQUENCY RANGE (MHz) E2 to C 48.25 to 82.25 (1) E5 to E12 175.25 to 224.25 E21 to E69 471.25 to 855.25 (2)
CABLE CHANNELS CHANNELS FREQUENCY RANGE (MHz) S01 to S08 69.25 to 154.25 S09 to S38 161.25 to 439.25 S39 to S41 447.25 to 463.25
(1). Enough margin is available to tune down to 45.25 MHz. (2). Enough margin is available to tune up to 863.25 MHz.
Noise Typical Low band : 5dB Mid band : 5dB High band : 6dB
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Max. 9dB 9dB 9dB
Gain Min. Typical Max. All channels : 38dB 44dB 52dB Gain Taper (of-air channels): 8dB
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Channel Coverage UV1336:
BAND
CHANNELS
Low Band Mid Band High Band
2 to D E to PP QQ to 69
FREQUENCY RANGE (MHz) 55.25 to 139.25 145.25 to 391.25 397.25 to 801.25
Noise is typically 6dB for all channels. Gain is minimum 38dB and maximum 50dB for all channels. 5. SOUND OUTPUT STAGE TDA7496 TDA7496 is used as the AF output stereo amplifier . It is supplied by +20 VDC coming from a separate winding in the SMPS transformer. An output power of 3.5W (THD=0.5%) can be delivered into an 8ohm load. 6. VERTICAL OUTPUT STAGE WITH TDA8174A The TDA8174A is a power amplifier circuit for use in 90° and 110° colour deflection systems for 25 to 200 Hz field frequencies, and for 4: 3 and 16: 9 picture tubes. 7. VIDEO OUTPUT DISCRETE AMPLIFIERS There are three monolithic video output amplifiers. Each amplifier consist of two transistors which are TR_2SC2482 and BF421. 8. POWER SUPPLY (SMPS) The DC voltages required at various parts of the chassis are provided by an SMPS transformer controlled by the IC MC44608 which is designed for driving, controlling and protecting switching transistor of SMPS. The transformer produces 115V for FBT input, ±14V for audio output IC, S+3.3, S+5V and 8V for ST92195. 10. SERIAL ACCESS CMOS 8K EEPROM 24C08 The 24C08 is a 8Kbit electrically erasable programmable memory (EEPROM), organized as 4 blocks of 256*08 bits. The memory is compatible with the I²C standard, two wire serial interface which uses a bidirectional data bus and serial clock. 12. SAW FILTERS Saw filter type: -66M: J1981 : K2958M: L9653M: G3967M: G9353M: K3958M: K9356M:
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Model: PAL SECAM B/G/D/K/I MONO PAL-I MONO PAL-SECAM B/G-D/K (38) MONO SECAM L/L’ AM MONO (AUDIO IF) PAL-SECAM B/G STEREO (VIDEO IF) PAL-SECAM B/G STEREO (AUDIO IF) PAL-SECAM B/G/D/K/I/L/L’ STEREO (VIDEO IF) PAL-SECAM B/G/D/K/I STEREO (AUDIO IF)
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K9656M: K3958M: K9356M: M1962M: M3953M: M9370M:
PAL-SECAM B/G/D/K/I/L/L’ STEREO (AUDIO IF) PAL I NICAM (VIDEO IF) PAL I NICAM (AUDIO IF) PAL M/N NTSC M MONO PAL M/N NTSC M STEREO (VIDEO IF) PAL M/N NTSC M STEREO (AUDIO IF)
IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM • ST92195 • STV224X • TUNER (UV1316, UV1336) • TDA7496L • TDA8174A • STV5114 • MC44608 • 24C08 • SAW FILTERS G1975M, K2966M, K2962M, L9653M, G3962M, G9353M, K3958M, K9356M, K9656M, K6263K, K9652M, M1962M, M3953M, M9370M
ST92195 The ST92195 is a member of the ST9+ family of micro-controllers, completely developed and produced by SGS-THOMSON Microelectronics using a proprietary n-well HCMOS process. The nucleus of the ST92195 is the advanced Core, which includes the Central Processing Unit (CPU), the ALU, the Register File and the interrupt controller. The Core has independent memory and register buses to add to the efficiency of the code. A set of on-chip peripherals form a complete sys-tem for TV set and VCR applications: – Voltage Synthesis – VPS/WSS Slicer – Teletext Slicer – Teletext Display RAM – OSD Additional peripherals include a watchdog timer , a serial peripheral interface (SPI), a 16-bit timer and an A/D converter.
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STV224X Video processor: The STV2246/2247/2248 are fully bus controlled ICs for TV including PIF, SIF, luma, Chroma and deflection processing. Used with a vertical frame booster (TDA1771 or TDA8174 for 90° chassis, STV9306 for 110° chassis), they allow the design of multi-standard (BGDKIMNLL, PAL/ SECAM/NTSC) sets with very few external components and no manual adjustments.
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UV1316, UV1336 General description of UV1316: The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range of applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L’, I and I’. Features of UV1316: • Member of the UV1300 family small sized UHF/VHF tuners • Systems CCIR: B/G, H, L, L’, I and I’; OIRT: D/K • Digitally controlled (PLL) tuning via I²C-bus • Off-air channels, S-cable channels and Hyper-band • World standardized mechanical dimensions and world standard pinning • Complies to “CENELEC EN55020” and “EN55013” PINNING 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.
Gain control voltage (AGC) Tuning voltage I²C-bus address select I²C-bus serial clock I²C-bus serial data Not connected PLL supply voltage ADC input Tuner supply voltage Symmetrical IF output 1 Symmetrical IF output 2
PIN VALUE :4.0V, Max:4.5V :Max:5.5V :Min:-0.3V, Max:5.5V :Min:-0.3V, Max:5.5V :5.0V, Min:4.75V, Max:5.5V :33V, Min:30V, Max:35V
General description of UV1336: UV1336 series is developed for reception of channels broadcast in accordance with the M, N standard. Features of UV1336: • Global standard pinning • Integrated Mixer-Oscillator & PLL function • Conforms to CISPR 13, FCC and DOC (Canada) regulations • Low power consumption • Both Phono connector and ‘F’ connector are available
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PINNING 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.
PIN VALUE
Gain control voltage Tuning voltage Address select Serial clock Serial data Not connected Supply voltage ADC input (optional) Tuning supply voltage Ground IF output
:4.0V, Max:4.5V Max:5.5V :Min:-0.3V, Max:5.5V :Min:-0.3V, Max:5.5V :5.0V, Min:4.75V, Max:5.5V :33V, Min:30V, Max:35V
TDA7496 DESCRIPTION The TDA7496 is a stereo 5+5W class AB power amplifier assembled in the @ Multiwatt 15 pack-age, specially designed for high quality sound, TV applications. Features of the TDA7496 include linear volume control, Stand-by and mute functions. -5+5W OUTPUT POWER -RL =? W@THD= 10% VCC = 22V -ST-BY AND MUTE FUNCTIONS -LOW TURN-ON TURN-OFF POP NOISE -LINEAR VOLUME CONTROL DC COUPLED -WITH POWEROP. AMP. -NO BOUCHEROT CELL -NO ST-BY RC INPUT NETWORK -SINGLE SUPPLY RANGING UP TO 35V -SHORT CIRCUIT PROTECTION -THERMAL OVERLOAD PROTECTION -INTERNALLY FIXED GAIN -SOFT CLIPPING -VARIABLE OUTPUT AFTER VOLUME CON-TROL -CIRCUIT -MULTIWATT 15 PACKAGE
PINNING 1 2 3 4 5 6 “1
INR. VAROUT_R VOLUME VAROUT_L
INL NC 12
7 8 9 10 11 12 13 14 15
SWR S_GNR STBY MUTE PW_GND OUTL VS OUTR PW1_GND
TDA8174AW Independent vertical amplitude adjustement. buffer stage. Power amplifier flyback generator thermal protection . Internal reference voltage decou-pling General Description: TDA8174A and TDA8174AWare a monolithic integrated circuits. It is a full performance and very efficient vertical deflection circuit intended for direct drive of a TV picture tube in Color and B & W television as well as in Monitor and Data displays. PINNING 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.
POWER OUTPUT OUTPUT STAGE Vs TRIGGER INPUT HEIGHT ADJUSTMENT VOLTAGE REF DECOUPLING GROUND RAMP GENERATOR BUFFER OUTPUT INVERTING INPUT Vs FLYBACK GENERATOR
STV5114 25MHz BANDWIDTH CROSSTALK : 55dB SHORT CIRCUIT TO GROUND OR VCC PRO-TECTED ANTI SATURATION GAIN CHANGING VIDEO SWITCHING
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DESCRIPTION This integrated circuit provides RGB switching al-lowing connections between peri TV plug, internal RGB generator and video processor in a TV set. The input signal black level is tied to the same reference voltageon each input in order to have no differential voltage when switching two RGB generators. An AC output signal higher than 2 Vpp makes gain going slowly down to 0dBto protect the TV set video amplifier from saturation. Fast blanking output is a logicial OR between FB1 (Pin 8) and FB2 (Pin 10).
PINNING 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.
PIN VALUE R1IN GND R2IN G1IN G2IN B1IN B2IN FB1IN FBOUT FB2+FBBIN BOUT FBGIN GOUT VCC FBRIN ROUT
MC44608 General description: The MC44608 is a high performance voltage-mode controller designed for off–line converters. This high voltage circuit that integrates the start–up current source and the oscillator capacitor, requires few external components while offering a high flexibility and reliability. The device also features a very high efficiency stand–by management consisting of an effective Pulsed Mode operation. This technique enables the reduction of the stand–by power consumption to approximately 1W while delivering 300mW in a 150W SMPS. • Integrated start–up current source • Loss less off–line start–up • Direct off–line operation • Fast start–up General Features • Flexibility • Duty cycle control
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• On chip oscillator switching frequency 40, or 75kHz • Secondary control with few external components Protections • Maximum duty cycle limitation • Cycle by cycle current limitation • Demagnetization (Zero current detection) protection • “Over V CC protection” against open loop • Programmable low inertia over voltage protection against open loop • Internal thermal protection GreenLine Controller • Pulsed mode techniques for a very high efficiency low power mode • Lossless startup • Low dV/dT for low EMI radiations PINNING 1. 2. 3. 4. 5. 6. 7. 8.
Demagnetization I Sense Control Input Ground Driver Supply voltage No connection Line Voltage
PIN VALUE Zero cross detection voltage: 50 mV typ. Over current protection voltage 1V typ. Min: 7.5V Max.: 18V Iout 2A p-p during scan 1.2A p-p during flyback Output resistor 8.5 Ohm sink 15 Ohm source typ. Max:16V (Operating range 6.6V-13V) Min:50V Max:500V
24CO8 General description: The 24C16 is a 8Kbit electrically erasable programmable memory (EEPROM), organized as 4 blocks of 256 * 08 bits. The memory operates with a power supply value as low as 2.5V. Features: • Minimum 1 million ERASE/WRITE cycles with over 10 years data retention • Single supply voltage:4.5 to 5.5V • Two wire serial interface, fully I²C-bus compatible • Byte and Multi-byte write (up to 8 bytes) • Page write (up to 16 bytes) • Byte, random and sequential read modes • Self timed programming cycle PINNING
PIN VALUE
1. 2. 3. 4. 5.
Write protect enable Not connected Chip enable input Ground Serial data address input/output
6.
Serial clock
:0V :0V :0V :0V :Input LOW voltage: :Input HIGH voltage: :Input LOW voltage: :Input HIGH voltage:
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Min:-0.3V, Max:0.3*Vcc Min:0.7*Vcc, Max:Vcc+1 Min:-0.3V, Max:0.3*Vcc Min:0.7*Vcc, Max:Vcc+1
7.
Multibyte/Page write mode
8.
Supply voltage
:Input LOW voltage: :Input HIGH voltage: :Min:2.5V, Max:5.5V
STR
MONO
Saw filter’s list: PAL BG PSBG DK PAL II' PSBGDKK' II' PSBGDKK' LL'
VIDEO G1975M K2966M J1981 K2966M K2962M
AUDIO
L9653
PAL BG PAL II' PSBGDKK' II' PSBGDKK' LL'
VIDEO G3967M K3958M K3958M K3958M
AUDIO G9353M K9356 K9356 K9656
PINNING 1. Input 2. Input-ground 3. Chip carrier-ground 4. Output 5. Output
K9656M, L9653M PINNING 1. Input 2. Switching Input 3. Chip carrier-ground 4. Output 5. Output
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Min:-0.3V, Max:0.5V Min:Vcc-0.5, Max:Vcc+1
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GENERAL BLOCK DIAGRAM of 11AK46
SCART
F-AV
DVD MODULE TDA7496 AUDIO SWITCHING R CIRCUITS PLL TUNER UV1316
L
AU. AMP
R
2
I
C
SERVICE CONNECTOR
MONO
NVM
KEYPAD
RGB AMP
IF ST92195 MICRO CONTROLLER
STV2248C VIDEO PROCESSOR
VER AMP
IR SENSOR
TDA8174AW SMPS
MC 44608
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115V +12V AUD.
+8V +5V +5V St-by
VIDEO SWITCHING CIRCUITS HORIZONTAL DRIVE BU808DF
19
FBT
DVD SCART1 FAV/BAV SVHS DVD POWER SUPPLY
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SIRA REGISTER PARAMETER NO 1 OSD OSD Horizontal Position 2
IF1
IF Coarse Adjust
3
IF2
IF Fine Adjust
4
IF3
IF Coarse Adjust for L-Prime
5
IF4
IF Fine Adjust for L-Prime
6
AGC
Automatic Gain Control
7
VLIN
Vertical Linearity
8
VS1A
Vertical Size for 50 Hz / 4:3
9
VS1B
Vertical Size for 50 Hz / 16:9
10
VP1
Vertical Position for 50 Hz
11
HP1
Horizontal Position for 50 Hz
12
VS2A
Vertical Size for 60 Hz / 4:3
13
VS2B
Vertical Size for 60 Hz / 16:9
14
VP2
Vertical Position for 60 Hz
15
HP2
Horizontal Position for 60 Hz
16
RGBH
RGB Horizontal Shift Offset
17
WR
White Point Adjust for RED
18
WG
White Point Adjust for GREEN
19
WB
White Point Adjust for BLUE
20
BR
Bias for RED
21
BG
Bias for GREEN
22
APR
APR Threshold
23
FMP1
FM Prescaler when AVL is OFF
24
NIP1
NICAM Prescaler when AVL is OFF
25
SCP1
SCART Prescaler when AVL is OFF
26
FMP2
FM Prescaler when AVL is ON
27
NIP2
NICAM Prescaler when AVL is ON
28
SCP2
SCART Prescaler when AVL is ON
29
F1H
High Byte of crossover frequency for VHF1-VHF3
30
F1L
Low Byte of crossover frequency for VHF1-VHF3
31
F2H
High Byte of crossover frequency for VHF3-UHF
32
F2L
Low Byte of crossover frequency for VHF3-UHF
33
BS1
Band Switch Byte for VHF1 Meaningful for only
34
BS2
Band Switch Byte for VHF3 Meaningful for only
35
BS3
Band Switch Byte for UHF Meaningful for only
36
CB
Control Byte Meaningful for only PLL Tuner
37
OP1
Option 1 (see the Option List)
38
OP2
Option 2 (see the Option List)
39
OP3
Option 3 (see the Option List)
40
OP4
Option 4 (see the Option List)
41
OP5
Option 5 (see the Option List)
42
TX1
Teletext Option 1 (see the Option List)
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OP1 – Peripheral Options BIT-7
NOT USED
BIT-6
1, Display “AV-3” as “F-AV” 0, Display “AV-3” as “B-AV” 1, Turn back TV mode after the last AV (with AV key) 0, Turn back first AV mode after the last AV 1, SVHS is available in AV key stream 0, SVHS is NOT available in AV key stream 1, RGB is available in AV key stream 0, RGB is NOT available in AV key stream 1, AV-3 is available in AV key stream 0, AV-3 is NOT available in AV key stream 1, DVD is available in AV key stream 0, DVD is NOT available in AV key stream 1, AV-1 is available in AV key stream 0, AV-1 is NOT available in AV key stream
BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0
OP2 – Reception Standard Options BIT-7
BIT-2
1, 3-button keyboard (V-, P+, V+) 0, 4/5 button keyboard (V-, V+, P-, P+, Menu) 1, L/L’ is available 0, L/L’ is not available 1, I is available 0, I is not available 1, DK is available 0, DK is not available 1, BG is available 0, BG is not available RESERVED (Keep as "0")
BIT-1
RESERVED (Keep as "0")
BIT-0
1, WFI available 0, WFI NOT available
BIT-6 BIT-5 BIT-4 BIT-3
OP3 – Video Options BIT-7 BIT-6
BIT-5 BIT-4 BIT-3 BIT-2
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Xtal Configuration 00, 1 Xtal PAL 4.43 01, 2 Xtal PAL/NTSC 4.43/3.58 10, 1 Xtal PAL/SEC/NTSC 4.43 11, 2 Xtal PAL/SEC/NTSC 4.43/3.58 1, Enable Blue back when no signal in AV modes 0, No Blue back in AV modes 1, White Insertion is ON 0, White Insertion is OFF 1, Blue Background when no signal 0, Disable Blue Background 1, Semi-transparent background for menu 0, Solid Menu background for menu
22
BIT-1 BIT-0
1, Black Stretch is ON 0, Black Stretch is OFF 1, APR is ON 0, APR is OFF
OP4 – TV Features BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2
1, Headphone is available (for STEREO models) 0, Headphone is not available 1, Arabic/Persian ON 0, Arabic/Persian OFF 1, Hebrew ON 0, Hebrew OFF 1, Hotel Mode can be activated 0, Hotel Mode can not be activated 1, No Signal Timer is enabled 0, No Signal Timer is disabled For PLL Tuner 1, Frequency based search 0, Channel table based search For VST Tuner 1, VST Band drive is negative logic (with transistors on the chassis) 0, VST Band drive is positive logic (without transistors on the chassis)
BIT-1 BIT-0
1, 3-band tuning (VHF1, VHF3, UHF) 0, 1-band tuning (only UHF) 1, Extra 200 msec blanking for VST 0, no-extra blanking
OP5 – Channel Tables BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0
1, Extra 150 msec blanking more for VST 0, no-extra blanking 1, “Programme” item in AUTOSTORE menu is visible 0, “Programme” item in AUTOSTORE menu is invisible NOT USED 1, French OS Channel Table is available 0, French OS Channel Table is not available 1, French Channel Table is available 0, French Channel Table is not available 1, England Channel Table is available 0, England Channel Table is not available 1, East Europe Channel Table is available 0, East Europe Channel Table is not available 1, West Europe Channel Table is available 0, West Europe Channel Table is not available
TX1 – Teletext Options BIT-7
NOT USED
BIT-6
RESERVED (must be 0)
“1
23
BIT-5 BIT-4 BIT-3
5 4 3 Teletext Language Groups 000, Group 1 – West (English, French, Swedish, Czech, German, Portuguese, Italien, Rumanian) 001, Group 2 – West/East (Polish, French, Swedish, Czech, German, Serbian, Italien, Rumanian) 010, Group 3 – West/Turkish (English, French, Swedish, Turkish, German, Portuguese, Italien, Rumanian) 011, Group 4 – East/Cyrillic (English, Cyrillic, Swedish, Czech, German, Serbian, Lettish, Rumanian) 100, Group 5 – Arabic (English, French, Swedish, Turkish, German, Hebrew, Italien, Arabic)
BIT-2 BIT-1 BIT-0
2 1 0 Device type selection 000, EPROM M6 A 001, ROM H5 P 010, ROMLESS H5 P 011, EPROM M6 R 100, ROM M6 R 101, OSDEPROM M6 R 110, ROM M6 P 111, Read Auto Gain Table for the device from EEPROM
AK46/TITANIUM – Languages Groups GROUP 1 - WEST • • • • • • • •
ENGLISH FRENCH SWEDISH CZECH GERMAN PORTUGUESE ITALIAN RUMANIAN
GROUP 2 – WEST / EAST • • • • • • • • • • • • • • • • •
POLISH FRENCH SWEDISH CZECH GERMAN SERBIAN ITALIAN RUMANIAN GROUP 3 – WEST / TURKEY ENGLISH FRENCH SWEDISH TURKISH GERMAN PORTUGUESE ITALIAN RUMANIAN
GROUP 4 – EAST / CYRILLIC • • •
“1
ENGLISH CYRILLIC SWEDISH
24
• • • • •
CZECH GERMAN SERBIAN LETTISH RUMANIAN
GROUP 5 - ARABIC • • • • • • • •
ENGLISH FRENCH SWEDISH TURKISH GERMAN HEBREW ITALIAN ARABIC
Using Coloured Buttons RED : No function. GREEN : Is used to switch the aspect ratio between 4:3 and 16:9. YELLOW : Is used to prepare the system for screen-adjustments. BLUE : No function.
“1
25
CONTENTS 1. 2. 2.1 2.2 2.3 2.4 2.5 3. 4. 5. 5.1 5.2 6 6.1 6.2 7. 8. 9. 10. 11. 11.1 11.2 12. 13. 14. 15. 15.1 15.2 15.3 15.4 16. 16.1 16.2 16.3 17. 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 18. 19. 20. 20.1 20.2
CHANGE HISTORY .................................................................................................................... 4 GENERAL DESCRIPTION .......................................................................................................... 4 STI5508 ...................................................................................................................................... 4 M2 .............................................................................................................................................. 5 DRIVE INTERFACES .................................................................................................................. 5 FRONT PANEL ........................................................................................................................... 5 REAR PANEL ............................................................................................................................. 6 GPIO, IRQ, AND CHIP SELECT ASSIGNMENTS ........................................................................ 6 JUMPER CONFIGURATION ........................................................................................................ 7 AUDIO OUTPUT .......................................................................................................................... 8 AUDIO DACS .............................................................................................................................. 8 AUDIO MUTE .............................................................................................................................. 8 VIDEO INTERFACE .................................................................................................................... 8 SCART INTERFACE ................................................................................................................... 9 DIGITAL VIDEO INTERFACE ....................................................................................................... 9 MPEG DECODER SDRAM MEMORY ........................................................................................ 9 PROCESSOR SDRAM MEMORY .............................................................................................. 9 FLASH MEMORY ....................................................................................................................... 10 SERIAL EEPROM MEMORY ..................................................................................................... 10 TMM DRIVE INTERFACE ............................................................................................................ 10 CONNECTION INFORMATION .................................................................................................... 10 TMM DRIVE TRAY MOTOR CONTROL AND PUSH AND STALL SENSE CIRCUITRY................. 11 ATAPI DRIVE INTERFACE AND EPLD ........................................................................................ 11 AUDIO SAMPLING RATE AND EXTERNAL PLL COMPONENT CONFIGURATION ..................... 11 UART SERIAL PORT .................................................................................................................. 11 FRONT PANEL ........................................................................................................................... 12 FRONT PANEL MICRO ............................................................................................................... 12 VFD CONTROLLER .................................................................................................................... 12 MICROPHONE INPUTS .............................................................................................................. 12 HEADPHONE OUTPUTS ............................................................................................................ 12 MISCELLANEOUS FUNCTIONS ................................................................................................. 12 POWER DOWN .......................................................................................................................... 12 RESET CIRCUITRY .................................................................................................................... 13 VOLTAGE REGULATORS ........................................................................................................... 13 CONNECTORS ........................................................................................................................... 13 ATAPI DRIVE STANDARD CONNECTOR .................................................................................... 13 TMM DRIVE CONNECTORS ....................................................................................................... 14 STI5508 JTAG INTERFACE ......................................................................................................... 15 RS232 SERIAL PORT ................................................................................................................. 16 DIGITAL YUV OUTPUT HEADER ................................................................................................ 16 ANALOG VIDEO INPUT HEADER .............................................................................................. 16 SCART CONNECTORS .............................................................................................................. 16 POWER CONNECTOR ............................................................................................................... 17 SCHEMATICS ............................................................................................................................. 17 BILL OF MATERIALS .................................................................................................................. 17 BOARD LAYOUT ........................................................................................................................ 17 TOP SIDE ASSEMBLY DRAWING ............................................................................................. 17 BOTTOM SIDE ASSEMBLY DRAWING ...................................................................................... 17
1 CHANGE HISTORY
2
2.3 DRIVE INTERFACES The system supports either a standard ATAPI drive interface or the SGS Thomson TVM502 drive (simply called TMM). The TMM drive is supplied with either a three connector interface or a single FFC cable connection. The design supports either connection method. The TMM three connector interface utilizes separate connectors for power, data, and drive tray motor control. Circuitry to control the TMM drive tray is located on the decoder board when this TMM drive version is used. The interface to the ATAPI drive is included within the STi5508. The ATAPI data bus is buffered so that the ATAPI cable does not interfere with signal quality. An ATAPI drive is connected via the standard 34 pin dual row PC style IDE header. An IDE power connector is also supported for convenience. 2.4 FRONT PANEL The front panel is included in the reference design and is based around an inexpensive Futaba VFD and a common NEC front panel controller chip, (uPD16311). The STi5508 controls the uPD16311 using several control signals, (clock, data, chip select). The infra-red remote control signal is passed directly to the STi5508 for decoding. A more advanced front panel is possible with the addition of a front panel microcontroller. A Microchip PIC can be used to control the 16311, receive the infra-red remote control decoding, and system power down. Communication between the STi5508 and the front panel PIC is accomplished over an I²C interface. The front panel connector also supports two microphone inputs and a stereo headphone output. 2.5 REAR PANEL A typical rear panel is included in the reference design. This rear panel supports: - Six channel and two channel simultaneous audio outputs - Optical and coax S/PDIF outputs are supported - Composite, S-Video, and RBG/YUV outputs - Dual SCART provides SCART passthrough when DVD output is not supplied - External video DENC Connections The six video signals used to provide CVBS, S-Video, and RGB/YUV are generated by the STi5508s internal video DAC. The video signals are be buffered by external circuitry. The STi5508 can generate either RGB or YUV outputs on three of the pins by configuring internal STi5508 registers. Six channel audio output by the STi5508 in the form of three I²S (or similar) data streams. An addition, an I²S stream is generated by the STi5508 to support simultaneous two-channel output. The S/PDIF serial stream is also generated by the STi5508 output by the rear panel. A six-channel audio DAC, a stereo DAC, or both can be installed. 3 GPIO, IRQ, AND CHIP SELECT ASSIGNMENTS PIO Port Bit
Pin #
STi5508 Alternate Function
CineMaster CE Function
Port 0 Bit 0 Port 0 Bit 1 Port 0 Bit 2 Port 0 Bit 3 Port 0 Bit 4 Port 0 Bit 5 Port 0 Bit 6 Port 0 Bit 7 Port 1 Bit 0 Port 1 Bit 1 Port 1 Bit 2 Port 1 Bit 3 Port 1 Bit 4 Port 1 Bit 5 Port 1 Bit 6 Port 1 Bit 7 Port 2 Bit 0 Port 2 Bit 1 Port 2 Bit 2 Port 2 Bit 3 Port 2 Bit 4 Port 2 Bit 5 Port 2 Bit 6
186 187 188 189 190 191 192 193 194 195 196 197 200 201 202 203 204 205 206 207 208 1 2
SC0_DATA #ATAPI_RD #ATAPI_WR SC0_CLK SC0_RST SC0_CMD_VCC SC0_DATA_DIR SC0_DETECT SSC0_DATA SSC0_CLK PARA_DVALID/SC_EXT_CLK TXD2 RXD2 PARA_SYNC/TXD1 TRIGIN TRIGOUT SC1_DATA PARA_REQ/RXD1 PARA_STR SC1_CLK SC1_RST SC1_CMD_VCC DAC_DATA/SC1_DATA_DIR
#SOFT_RESET #ATAPI_RD #ATAPI_WR DAC_CCLK (Audio DAC control) DAC_CCLK (Audio DAC control) #DAC_CS0 (Audio DAC control) #DAC_CS1 (Audio DAC control) Unused (Test Point 39) SDA (I2C) SCL (I2C) Unused (Test Point 35) TXD (Serial Port) RXD (Serial Port) SR0 (for PLL1700) TRIGIN (JTAG) TRIGOUT (JTAG) FPCLK (Front Panel) FS0 (for PLL1700) FS1 (for PLL1700) RTS (Serial Port) CTS (Serial Port) FPDATA (Front Panel) DAC_DATA (Stereo Audýo)
Port 2 Bit 7
3
SC1_DETECT
FPSTRB (Front Panel)
4
1. CHANGE HISTORY Revision Rev 1.0 Rev 1.1
Date 7/23/2000 8/23/2000
Author Jim Loughin Jim Loughin
Comments Initial Release Updated to match final design
2. GENERAL DESCRIPTION Major functional blocks are discussed briefly in this section. A more detailed description is contained later in the document. 2.1 STI5508 The STi5508 provides a highly integrated back-end solution for DVD applications. A host CPU handles both the general application (the user interface, and the DVD, CD-DA, VCD, SVCD navigation) and the drivers of the different embedded peripheral (audio/video, karaoke, sub-picture decoders, OSD, PAL/NTSC encoder...). Because of its memory savings, increased number of internal peripherals, improved development platform and reference design, theSTi5508 offers a costeffective solution to DVD applications, with rapid time-to-market. These functions include: Integrated 32-bit host CPU @ 60MHz - 2 Kbytes of instruction cache, 2 Kbytes of data cache, and 4Kbytes of SRAM configurable as data cache. Audio decoder - 5.1 channel Dolby Digital® /MPEG-2 multi-channel decoding, 3 X 2-channel PCM outputs - IEC60958 IEC61937 digital output - DTS® digital out 5.1 channel - SRS®/TruSurround® - MP3 decoding Karaoke processor - Echo, pitch shift, microphone inputs, voice cancellation and multiple other effects Video decoder - Supports MPEG-2 MP@ML - Fully programmable zoom-in and zoom-out - PAL to NTSC and NTSC to PAL conversion DVD and SVCD subpicture decoder High performance on-screen display - to 8 bits per pixel OSD options - Anti-flicker, anti-flutter and anti-aliasing filters PAL/NTSC/SECAM encoder - RGB, CVBS, Y/C and YUV outputs with 10-bit DACs - Macrovision® 7.01/6.1 compatible Shared SDRAM memory interface - Supports one or two 16Mbit, or one 64Mbit 125 MHZ SDRAMs Programmable CPU memory interface for SDRAM, ROM, peripherals... Front-end interface - DVD, VCD, SVCD and CD-DA compatible - Serial, parallel and ATAPI interfaces - Hardware sector filtering - Integrated CSS decryption and track buffer Integrated peripherals - UARTS, 2 SmartCards, I2C controller, 3 PWM outputs, 3 capture timers - Modem support - 38 bits of programmable I/O Please refer to the STi5508 Data Sheets: STi5508 DVD HOST PROCESSOR WITH ENHANCED AUDIO FEATURES and STi5508 REGISTER MANUAL for more detailed information. 2.2 MEMORY The STi5508 includes all of the interface signals to connect to industry standard SDRAM, DRAM, ROM, and I2C memory devices. The system includes one or two SDRAM components. The MPEG decoder unit interfaces to a single 4M x 16bit SDRAM over the SMI bus. The general purpose processor can share the decoder SDRAM or can access an optional SDRAM installed on the EMI bus. This EMI SDRAM can be either a 1Mx16 or 4Mx16 chip. The optional EMI SDRAM can be installed if the system requires higher performance of requires more RAM than is standard system (due to complex trick modes, advanced GUI, etc). The standard production Ravisent CineMasterCE software will execute without EMI SDRAM installed, however EMI SDRAM is required to perform debugging and prototyping. A single 1Mx16 FLASH ROM device is support on the EMI bus. There is also a small I²C serial EEPROM (from 1Kbit to 256Kbit) for storage of user player settings, software configuration information, title specific information, or other purposes. 3
Port 3 Bit 0 Port 3 Bit 1 Port 3 Bit 2 Port 3 Bit 3 Port 3 Bit 4 Port 3 Bit 5 Port 3 Bit 6 Port 3 Bit 7 Port 4 Bit 0 Port 4 Bit 1 Port 4 Bit 2 Port 4 Bit 3 Port 4 Bit 4 Port 4 Bit 5 Port 4 Bit 6 Port 4 Bit 7
6 7 8 9 10 11 12 13 39 40 41 42 43 44 45 46
PARA_DATA0 PARA_DATA1 PARA_DATA2 PARA_DATA3 PARA_DATA4 PARA_DATA5 PARA_DATA6/COMP1 PARA_DATA7/COMP2 YUV0 YUV1 YUV2 YUV3 YUV4 YUV5 YUV6 YUV7
OPEN (TMM Tray Control) CLOSE (TMM Tray Control) Unused (Test Point 36) Front Panel IR Unused (Test Point 37) Unused (Test Point 38) #SENSE (TMM Tray Control) #PUSH (TMM Tray Control) YUV0 (External Video DENC) YUV1 YUV2 YUV3 YUV4 YUV5 YUV6 YUV7
* Front Panel uses the 16311 controller. In the CineMaster design, FPDIN and FPDOUT are connected together as FPDATA. Pin Name #CE1 #CE2 #CE3 #IRQ0 #IRQ1 #IRQ2
Pin # 134 133 132 127 126 125
STi5508 Pin Function Programmable Chip Enable 1 Programmable Chip Enable 2 Programmable Chip Enable 3 Interrupt 1 Interrupt 2 Interrupt 3
CineMaster CE Function ATAPI Buffer Chip Enable Unused FLASH Memory Chip Select Front Panel Interrupt Front End Interrupt (ATAPI/TMM) Unused
Table 1 GPIO, IRQ, and Chip Select Assignments 4. JUMPER CONFIGURATION Jumper JP1
Function Power Down
JP3
Boot From Link
* Note: There is no JP2
Installed +3.3V, +5V and +12V are disconnected from the STi5508 and associated circuitry using a FET switch forces STi5508 to boot from JTAG interface only
Not Installed Uninstalled all components are powered Not Installed STi5508 will attempt to boot from FLASH, but will also boot from JTAG interface
Table 2 Jumper Configuration
5. AUDIO OUTPUT The STi5508 supports both a six channel analog output and a stereo output configuration. Both of these output configurations are available simultaneously (eight analog outputs total). In a system configuration with six analog outputs, the front left and right channels can be configured to provide the stereo outputs, Dolby Surround, and SRS TruSurround, or the left and right front channels for a 5.1 channel surround system. The STi5508 also provides a stereo output channel that can be used in combination with the 5.1 outputs. An example of this configuration is a DVD player with these stereo outputs connected to the TV and the six channel outputs connected to the surround sound amplifier unit. In this setup, the consumer can use the TV speakers or the surround speaker without changing any wires. The stereo output can be configured separately from the six-channel left and right outputs, so, for example, the stereo output can be configured for Dolby ProLogic. The Sti5508 also provides digital output in S/PDIF format. The evaluation board supports both optical and coaxial S/PDIF outputs. 5.1 AUDIO DACs The STi5508 supports several variations of an I²S type bus, varying the order of the data bits (leading or no leading zero bit, left or right alignment within frame, and MSB or LSB first) is possible using the Sti5508 internal configuration registers. The I²S format uses four stereo data lines and three clock lines. The I²S data and clock lines can be connected directly to one or more audio DAC to generate analog audio output. 5
The evaluation board uses a six-channel DAC and also a two-channel DAC. The six-channel DAC is connected to the three STI5508 data signals for six-channel output and the two-channel DAC is connected to the STi5508 optional stereo output. The board can be configured with either the six- or two-channel DAC, or both. When the two-channel DAC is not used, the left and right front audio can be connected to the stereo audio output connectors by installing zero ohm resistors R364 and R365. The six-channel DAC is an AKM AK4356. The two-channel DAC is an AK4394 also made by AKM. Both of these DACs support up to 192Khz sampling rate. A less expensive 96kHz two-channel DAC with the same pin-out can be placed instead of the AK4394. Four STi5508 PIO pins are used to configure the audio DACs. The outputs of the DACs are differential, not single ended so a slightly more expensive buffering circuit is required. The buffer circuits use NJR NJM5532 opamps to perform the low-pass filtering and the buffering. 5.2 AUDIO MUTE The audio DACs contain an internal mute circuit and can be enabled by the STi5508 PIO pins. The evaluation board may output a small pop when the system is powered on and off, but no audible pops should be heard during operation or when entering or leaving standby mode. 6. VIDEO INTERFACE The STi5508 integrates a PAL/NTSC encoder. It converts the digital MPEG/Sub Picture/OSD stream into a standard analog baseband PAL/NTSC signals. Six analog video outputs provide CVBS, S-Video (Y/C), and RGB/YUV formats. The three RGB signals can be configured via an internal STi5508 register setting to output either RGB or YUV video signals. The encoder handles interlaced and non-interlaced mode. It can perform Closed Captions, CGMS or Teletext encoding and allows Macrovision 7.01/6.1 copy protection. The encoder supports both master and slave modes for synchronization. The six video signals are routed to the back panel where they are low-pass filtered and buffered. The six active video buffer circuits on the decoder board are identical and use a video speed MAX4018 opamp made by Maxim. The buffered CVBS video is available on a RCA (cinch) style jack, S-Video on a mini-DIN, RGB/YUV on a triple RCA jack, and all six signals (and stereo audio) are available on a SCART connector. Note:The STi5508 is not capable of placing the video synch information in the green signal as required by some RGB monitors. The synch information must be obtained from the CVBS output and connected to the external sync input of an RGB monitor. Note:When the STi5508 is configured to output YUV signals, the RGB pins of the SCART connector will also output YUV. 6.1 SCART INTERFACE The Ravisent evaluation board contains a SCART controller chip from ST Microelectronics, the STv6412. This controller chip allows SCART daisy-chaining the SCART output from another device can be connected to the DVD player SCART input and passed through when the DVD player is in standby. All SCART functions are controlled by the 6412 chip, which is in turn controlled by the STi5508 over the I²C bus. Please see the STv6412 AUDIO/VIDEO SWITCH MATRIX data sheet for more detailed information. 6.2 DIGITAL VIDEO INTERFACE An external video DENC can be connected to the STi5508. The digital output and analog input headers are provided on the board, J20 and J19 respectively. The video encoder is controlled via I2C through the header. Also supplied on the header are +3.3V, +5V, ground, and +5V and 5V analog supplies. The output of the external DENC is then fed into the video filter-buffers on board. The values of the discrete components in the filter-buffers should be changed to match the characteristics of the external DENC. 7. MPEG DECODER SDRAM MEMORY The STi5508 includes glueless interfaces to SDRAM memory for the MPEG decoder. The STi5508 supports one or two 1Mx16bit chips or a 4Mx16bit SDRAM chip. However, the Ravisent evaluation board supports only a 64Mbit chip. The device used is a 4M x 16 bit, 125MHz, 3.3V, 54 pin TSOP II, Micron Technology MCT48LC4M16A2TG-7 or equivalent. 8. PROCESSOR SDRAM MEMORY The STi5508 supports DRAM or SDRAM on its processor bus without any glue logic required. The Ravisent evaluation board supports only SDRAM - either a 1Mx16bit or a 4Mx16bit SDRAM. The STi5508 processor can be configured to share the decoder memory. This will reduce performance slightly, but will reduce the cost of the system, as processor SDRAM is no longer required. It is expected that a typical DVD player will not need any processor SDRAM and this chips will only be installed for test and debug purposes. Dual PCB footprints were used to accommodate the differences in packaging between 16M and 64M SDRAMS. U5/1 is the 16Mbit footprint and U5/2 is the 64Mbit footprint. The same 64Mbit SDRAM used for decoder memory can be used for processor SDRAM.
6
9. FLASH MEMORY The decoder board supports a single 1Mx16bit FLASH memory device. The device is a 1M x 16, 90ns, bottom boot block, 3.3V, 48 pin TSOP II, SGS Thomson M29F160BB-90N1 or equivalent. Both 3.3V and 5V FLASH devices can be installed. Our current FLASH loading software supports several FLASH chips from different manufacturers. To support new chips, the programming algorithm will have to be adapted, but this is a rather simple adaptation. Note: Intel and Micron FLASH require that pins 13 and 14 are tied to the positive power supply to allow programming in circuit. To support these device families, install zero ohm (0R0) resistors in locations R79 and R80. Note: Install a zero ohm resistor in location R350 to support +5V FLASH. Install zero ohms in R352 to support +3.3V FLASH. Never install both R350 and R352 at the same time as this will short the 3.3 and 5V supplies together. The default is +3.3V. Note: Some FLASH devices use pin 15 for address pin A19, while most others use pin 9. To support a chip that uses pin 15, install R81. 10. SERIAL EEPROM MEMORY An I²C serial EEPROM is used to store user configuration (i.e. language preferences, speaker setup, etc.) and software configuration information (i.e. remote control type). Industry standard EEPROM range in size from 1kbit to 256kbit and share the same IC footprint and pinout. The default device is 2kbit, 256k x 8, SOIC8 SGS Thomson ST24C02M1 or equivalent. See the section on Reset Circuitry for a less costly EEPROM solution. 11. TMM DRIVE INTERFACE The STi5508 will directly supports a Thomson TVM502 drive (or a similar drive built around the ST chip drive set) without any external glue logic. The newer TVM drives include the disc tray motor control circuitry, but the older drives do not. Tray motor control circuitry is included on the evaluation board to support these older drives. 11.1 CONNECTION INFORMATION The newer TMM drive uses a 19 pin FFC connector while the older drives use two PicoFlex ribbon connectors and a two pin tray motor connector. Both connector systems are supported on the evaluation board. The drive interface, with the exception of the tray motor circuitry, is contained entirely in the STi5508. The older TMM drive connects to the evaluation board in three places: J5 Drive tray motor terminals J6 Power cable connector J7 Data cable connector The newer TMM drive connects to the evaluation board with a single connector: J8 FFC19 connector The connectors selected by Thomson for the data and power cables are in the PicoFlex product line manufactured by Molex and Lumberg. The FFC connector is available from many suppliers including Molex. See Bill of Material for part numbers. 11.2 TMM DRIVE TRAY MOTOR CONTROL AND PUSH AND STALL SENSE CIRCUITRY There is circuitry on the decoder board to power the TMM drive tray and to monitor its activity. When the tray is being opened or closed and the tray has reached the end of its travel or is being jammed, the motor will stall and draw a high current. Circuitry monitors the level of current used by the motor and will toggle a PIO pin of the STi5508 when the motor has stalled, (schematic net name: #SENSE). The STi5508 will then remove power to the motor. Also, if the tray is open and the user pushes the tray to close it, the motor will generate voltage. Circuitry will sense this voltage and toggle another PIO pin, (schematic net name: #PUSH). The STi5508 will then close the tray. The sensitivity of the push sense can be adjusted by changing the value of R114 in relation to R117. When the tray is motionless, the voltage across the motor is zero. When the tray is pushed the voltages at either side of the motor begin to diverge. These two voltages are fed into a comparator to create the trigger signal. This is an improved circuit from the Ravisent STi5505 evaluation boards and this new circuit is not sensitive to temperature or component tolerances. Note: To disable the push sense circuit, remove R109 and R112. R106 and R107 should already be installed. 12. ATAPI DRIVE INTERFACE AND EPLD The STi5508 includes a glueless ATAPI interface on-chip. While this interface limits performance of the system, it is a lower cost solution than providing external logic to interface the drive to the STi5508 front-end interface. Standard ATAPI DVD drives are supported through the ATAPI EPLD interface. The drive connects to the decoder board through a standard 40 pin header, The header is a 2 row by x 20 pins, 0.1 pin spacing, and has 0.025 square pins. Note: The decoder board supports the standard ATAPI electrical connections, but the software protocol within the drive is not always supported according to ATAPI specifications. Custom software may need to be developed and tested to support ATAPI drives from different manufacturers. 7
13 AUDIO SAMPLING RATE AND EXTERNAL PLL COMPONENT CONFIGURATION The decoder board has optional PLLs, which can be installed to provide the audio clock for the system. The initial version of the STi5505 was not able to provide an audio clock for 96kHz support and an external PLL was used to support this. This was fixed in the STi5505 later chip revisions and therefore no problems are expected in the STi5508. However, in case a problem arises, the PLL circuit can be installed to provide a high quality clock particularly important in S/PDIF applications. In the default configuration, a small buffer chip is installed to buffer the audio clock between the STi5508 and the audio DACs. 14 UART SERIAL PORT The evaluation board provides an RS232 connection to the STi5508. A standard DB9 connector ribbon cable can be connected to the 10 pin header provided, (J9). The RS232 buffer can also be bypassed and the 3.3V signals can be accessed on the header. ASC2 is the serial port used to this connection. 15. FRONT PANEL 15.1 FRONT PANEL MICRO A Microchip PIC can be installed in the system to control the front panel VFD, perform IR remote control decoding and power down functions, and read the position on two POTs with its internal ADC. When the front panel micro is installed, the entire decoder board circuit can be powered down in standby mode because the PIC will decode the IR signals. 15.2 VFD CONTROLLER The VFD controller is a NEC uPD16311. This controller is not a processor, but does include a simple state machine which scans the VFD and reads the front panel button matrix. The 16311 also includes RAM so it can store the current state of all the VFD icons and segments. Therefore, the 16311 need only be accessed when the VFD status changes and when the button status is read. The STI5508 can control this chip directly using PIO pins or can allow the front panel PIC to control the VFD. 15.3 MICROPHONE INPUTS The board has two ¼ phono-jacks for microphone input. The microphone circuits consist of microphone pre-amps, a signal buffers, and a stereo ADC. The microphone pre-amp, SSM2165, conditions the signal for better performance. The stereo ADC is a Crystal CS5331 and connects directly to the STi5508 digital audio input via I²S. Adjusting the value POT1 and POT2 can vary the compression characteristics of the microphone signal. See the SSM2165 data sheet for a graph of the compression characteristics and POT settings. When the correct POT setting is found, the pots can be replaced with fixed resistors, R382 and R383. 15.4 HEADPHONE OUTPUTS The left and right audio is amplified and output through a stereo ¼ phono-jack. The audio is from the two-channel output, not the let and right channel of the six-channel, (the left and right six-channel audio can be connected to the left and right two-channel output when the stereo DAC is not installed). A dual logarithmic POT is used to adjust the volume of the audio before amplification, POT5. The connections for left and right channels at the headphone jack can be swapped by changing the resistor stuffing options, R376-379 . 16 MISCELLANEOUS FUNCTIONS 16.1 POWER DOWN Two dual FET ICs can be installed on the decoder board to enable a power down feature. Power down is activated by connecting a switch across JP1, shorting the two pins together pulling pin 2 to +5V. The front panel microcontroller can also control the power down status by driving FPPWD high. When in power down state, power can be removed from all of the circuitry except the front panel micro, which must remain power to decode remote control signaling and scanning the front panel buttons. If the front panel micro is not used, then the STi5508 cannot be powered down. The board can be configured in several ways to accomplish a power down goal. The net VCC_PIC is always powered. VCC can either be switched (by installing R3) or always powered (by installing R1). VCC3 can either be switched (by installing R5)or always powered (by installing R2). VCC-S, VCC3-S, +12V-S, and +8V-S are switched. There are four LEDs used to indicate power state and they can be connected on either side of the FET switch. The dual FET is a Fairchild NDS8934 and is located at Q1 and Q2. Note: If the power down feature is enabled FPPWD must be driven by the front panel micro or some other source. 16.2 RESET CIRCUITRY Three different chips are supported to provide the power-on-reset and pushbutton reset function: Analog Device ADM707 (or equivalent), Telcom Semiconductor TC1270, or Xicor X1242. The TC1270 is a lower cost alternative to the ADM707. The Xicor device also includes 2kbits of Serial EEPROM storage and can be used to replace both the reset and SEEPROM devices to reduce cost. All three devices support and pushbutton reset switch.
8
16.3 VOLTAGE REGULATORS There are two +5V linear regulators to generate +5V for the analog circuitry from +12V. A smaller DPAK surface mount device can be used in most circumstances, but in applications were more than 150mA are required, a TO-220 throughhole package can be used. The STi5508 requires 2.5V to operate. This voltage is generated from +5V. Negative 5V is required by the audio buffer circuitry and this is generated in one of three ways. If 12V is supplied by the power supply, it is regulated to 5V with a linear regulator. If no 12V is supplied, a DC-DC can be installed in U51 to generate either 12V or 5V. The use of a switching regulator to generate the negative voltage may introduce noise into that voltage, so better audio performance may be produced by generating 12V with the DC-DC converter and then regulating this to 5V with a linear regulator. 17 CONNECTORS 17.1 ATAPI DRIVE STANDARD CONNECTOR Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
ATAPI Drive Interface J23 Description Pin #RESET 2 DATA7 4 DATA6 6 DATA5 8 DATA4 10 DATA3 12 DATA2 14 DATA1 16 DATA0 18 GND 20 DMARQ 22 #IOW 24 #IOR 26 IOCHRDY 28 #DMACK 30 INTRQ 32 ADDR1 34 ADDR0 36 #CS0 38 40 Table 3 ATAPI Drive Interface J23
17.2 TMM DRIVE CONNECTORS
TMM Tray Connector J5 Pin Description 1 +12V 2 GND 3 GND 4 +5V Table 4 ATAPI Power Connector J4 TMM Tray Connector J5 Pin Description 1 OPEN 2 CLOSE Table 5 TMM Tray Connector J5 TMM Power Connector J6 Pin Description 1 +5V (filtered) 2 +5V 3 GND 4 GND (filtered) 5 GND 6 +8V 7 GND 8 +12V 9 GND 10 +3.3V Table 6 TMM Power Connector J6 9
Description GND DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 GND GND GND GND GND HIO16 #PDIAG ADDR2 #CS1 GND
TMM Data Connector J7 Pin Description 2 GND 3 SYNC 4 FLAG 5 DATA 6 BCLK 7 GND 8 #FE RESET 9 FE I NT 10 SCL 11 SDA 12 GND Table 7 TMM Data Connector J7 Pin 1 2 3 4 5 6 7 8 9 10
Description GND SYNC FLAG DATA BCLK GND #FRESET FEINT SCL
TMM FFC19 Connector J8 Pin 11 12 13 14 15 16 17 18 19
Description SDA GND GND +3.3V +5V GND GND (filtered) +12V +8V or +12V
Table 8 TMM FFC19 Connector J8 17.3 STI5508 JTAG INTERFACE Pin 1 3 5 7 9 11 13 15 17 19
JTAG Programming Interface J2 Description Pin Description 2 GND PIO3_7 4 GND PIO3_6 6 GND 8 GND TMS 10 GND TCK 12 GND TDI 14 GND TDO 16 GND #JTAG_RESET 18 GND #TRST 20 GND Table 9 JTAG Programming Interface J2
17.4 RS232 SERIAL PORT Pin 1 3 5 7 9
RS232 Serial Port Header J9 Description Pin 2 TXD 4 RXD 6 8 GND 10 Table 10 RS232 Serial Port Header J9
10
Description CTS RTS -
17.5 DIGITAL YUV OUTPUT HEADER Pin 1 3 5 7 9 11 13 15 17 19 21 23 25
Digital YUV Output Header J20 Description Pin YUV0 2 YUV1 4 YUV2 6 YUV3 8 YUV4 10 YUV5 12 YUV6 14 YUV7 16 PIXCLK 18 20 SCL 22 SDA 24 GND 26
Description GND GND GND VSYNC HSYNC GND GND GND +5V or +3.3V +5V (analog) -5V (analog)
Table 11 Digital YUV Output Header J20 17.6 ANALOG VIDEO INPUT HEADER Pin 1 3 5 7 9 11
Analog Video Input Header J19 Description Pin Description RED 2 GND GREEN 4 GND BLUE 6 GND CHROMA 8 GND LUMA 10 GND CVBS 12 GND Table 12 Analog Video Input Header J19
17.7 SCART CONNECTORS Pin 1 3 5 7 9 11 13 15 17 19 21
SCART Connectors J10 Description Pin RIGHT AUDIO OUT 2 LEFT AUDIO OUT 4 GND 6 BLUE 8 GND 10 GREEN 12 GND 14 RED (CHROMA) 16 GND 18 CVBS OUT (LUMA) 20 GND (shield)
Description RIGHT AUDIO IN GND LEFT AUDIO IN SWITCH GND BLANK GND CVBS IN
Table 13 SCART Connectors J10 17.8 POWER CONNECTOR Pin 1 2 3 4 5 6 71 81
Power Connector J1 Description +5 V +3.3 V +3.3 V GND GND +12 V GND -12 V
Table 14 Power Connector J1 Connection to these two terminals is not required unless the board uses 12V. In a system without 12V, a six pin header can be installed into pins one (1) through six (6) leaving pins seven (7) and eight (8) unpopulated. 1
18 SCHEMATICS 19 BILL OF MATERIALS 20 BOARD LAYOUT 20.1 TOP SIDE ASSEMBLY DRAWING 20.2 BOTTOM SIDE ASSEMBLY DRAWING 11
A
B
C
DDESCRIPTION
REV 1.0
E
APPROVAL
DATE
INITIAL RELEASE
Production - STi5508/80 4
DECMEM MA[0..13]
MA[0..13]
STi5508 MA[0..13]
ADR[0..20]
MD[0..15]
MD[0..15]
MD[0..15]
DATA[0..15]
SMICLK
SMICLK
DATA[0..15]
DATA[0..15]
RAMCLK
RAMCLK
#SMICS0
#SDCS0
#SDCS0
#SMIRAS #SMICAS
#SMIRAS #SMICAS
#SDRAS #SDCAS
#SDRAS #SDCAS
#SMIWE
#SMIWE
#SDWE
SMIDQML SMIDQMU
DQML DQMH
05-DECMEM FRONT PANEL FPCLK FPDATA FPSTB FPIR
3
FPCLK FPDATA FPSTB FPIR
#CE3 #OE #WE #RESET
DQML DQMH 04-SYSMEM FLASHROM ADR[0..20]
#CE3 #OE #WE
3
#RESET 03-FLASHROM RS232
RTS CTS TXD RXD
#BPRESET
SPDIF_OUT
SPDIF_OUT
DAC_PCMCLK DAC_SCLK DAC_LRCLK DAC_DATA0 DAC_DATA1 DAC_DATA2 DAC_DATA
DAC_SCLK DAC_LRCLK DAC_DATA0 DAC_DATA1 DAC_DATA2 DAC_DATA
DATA[0..15] #FERESET
BPPIO0 BPPIO1 BPPIO2 BPPIO3 11-AUDIO OUT VIDEO OUT RED GREEN BLUE STANDBY
BPPIO0 BPPIO1 BPPIO2 BPPIO3
CHROMA LUMA CVBS 12-VIDEO OUT SEEPROM RST
CHROMA LUMA CVBS
RTS CTS TXD RXD 10-RS232 FRONTEND ADR[0..20]
SCL SDA
#CE1 R/#W #ATAPI_WR #ATAPI_RD
RED GREEN BLUE
#CE1 R/#W #ATAPI_WR #ATAPI_RD FEINT
OPEN CLOSE #SENSE #PUSH
OPEN CLOSE #SENSE #PUSH
SCL SDA POWERON
#FERESET
FEINT
DATA BCLK FLAG SYNC
SCL SDA POWERON
#SDWE
DATA[0..15]
SCL SDA 14-FRONT PANEL AUDIO OUT #BPRESET
4
SYSMEM ADR[0..20]
#SMICS0
SMIDQML SMIDQMU
2
ADR[0..20]
2
DATA BCLK FLAG SYNC SCL SDA 06-FRONTEND POWER
20-SEEPROM RST EXTPLL 22-POWER
#BPRESET ML MD MC
ML MD MC
THESE SCHEMATICS ARE PROPRIETARY AND CONFIDENTIAL INFORMATION OF RAVISENT Technologies Inc.
PCMCLK
1
PIXCLK AUDCLK 09-EXTPLL
I²C Add.: E²PROM RTC/WD NV-MEM TVM502
0xA0 0xDE 0xAE 0x30
Title
Production - Overview of Decoder Board Size
A3 Date:
A
B
1
(c) RAVISENT Technologies Inc. PIXCLK AUDCLK 02-5508
C
D
Document Number
Rev
1.1
101559 Tuesday, December 26, 2000
Sheet
E
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16
AMA[0..13]
B
C
VCC3 10K 10K 10K 10K 10K 10K 10K
TRIGIN TRIGOUT
J1
3
1 3 5 7 9 11 13 15 17 19
R36
#RESET
#RESET
R45
TDO BPPIO0 BPPIO1 BPPIO2 BPPIO3 OPEN CLOSE
BPPIO0 BPPIO1 BPPIO2 BPPIO3
2
OPEN CLOSE
DATA BCLK FLAG SYNC
DATA BCLK FLAG SYNC
MC MD
MC MD
ML
ML FPCLK FPDATA FPSTB
FPCLK FPDATA FPSTB
1
MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7
84 85 86 87 88 89 90 91
SMIDATA0 SMIDATA1 SMIDATA2 SMIDATA3 SMIDATA4 SMIDATA5 SMIDATA6 SMIDATA7
R49 R50 R51 R52
220R 220R 220R 220R
6 7 8 9 10 11 12 13
#FERESET #AUXRESET #BPRESET
#BPRESET
DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15
JP1
151 152 153 154 155 156 157 158 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7
10K
DATA[0..15] VCC3
R2
R347
10K
RAMCLK 118 CAS1/SDCS0 140 RAS1/SDCS1 138 RAS0/SDRAS 135 CAS0/SDCAS 139 R/W/SDWE 130 BE0/DQML 128 BE1/DQMH 129 WAIT 131
R5
0R0
RAMCLK
R7
0R0
#SDCS0
R10 R12 R14 R15 R17
0R0 0R0 0R0 0R0 0R0
#SDRAS #SDCAS #SDWE DQML DQMH
PIO2_3 PIO2_4 PIO1_3/TXD2 PIO1_4/RXD2
207 208 197 200
#CE3 #OE #ATAPI_RD #ATAPI_WR FEINT SPDIF_OUT
3 AUDCLK DAC_SCLK DAC_LRCLK DAC_DATA0 DAC_DATA1 DAC_DATA2 DAC_DATA
PIXCLK RED GREEN BLUE LUMA CHROMA CVBS R46 75R R48 10K
TP11
R57 20K0 1%
2
C1 47pF
RTS CTS TXD RXD
RTS CTS TXD RXD
R53 PIO1_1/SCL 195 R54 PIO1_0/SDA 194
SCL SDA
33R 33R
SCL SDA
TP9 TP10
TP5
4
R/#W #WE #CE1
ST Microelectronics STi5508/80
B_DATA B_BCLK B_FLAG B_SYNC B_WCLK/NRSS_CLK B_V4/NRSS_IN NRRS_OUT STi5508 or STi5580
TP1
10K
R58 20K0 1%
C2 47pF
R55
4K7
R56
4K7
VCC
C3 47pF
#SOFT_RESET
R59 R61 R62 R63 R64 R65
0R0 NS 0R0 NS NS 0R0
1 R60 10K Title
Production - STi5508 Core Size
A3 Ravisent Proprietary Information
A
R1
JUMPER3
33R 134 R18 133 33R 132 R20 33R 117 R22 R25 33R ATAPI_RD/PIO0_1 187 R27 33R ATAPI_WR/PIO0_2 188 R32 10K 127 IRQ0 126 FEINT IRQ1 125 R30 10K IRQ2 R31 33R 57 SPDIF_OUT ADC_PCMCLK 106 103 ADC_SCLK ADC_LRCLK 104 R35 10K ADC_DATA 105 33R R37 DAC_PCMCLK 55 R38 33R 51 DAC_SCLK R39 33R DAC_LRCLK 56 R40 33R DAC_DATA0 52 R42 33R DAC_DATA1 53 R43 33R DAC_DATA2 54 R44 33R PIO2_6/DAC_DATA 2 BOOTFROMROM PWM1/BOOTFROMROM 115 TP31 PWM0/HSYNC 116 TP32 PWM2/VSYNC 114 PIXCLK 120 PIXCLK _27Mhz RED R_OUT 27 GREEN G_OUT 26 BLUE 25 B_OUT LUMA 32 Y_OUT 33 CHROMA C_OUT CVBS CVBS_OUT 34 TP33 YUV0/PIO4_0 39 40 TP34 YUV1/PIO4_1 41 TP35 YUV2/PIO4_2 42 TP36 R47 YUV3/PIO4_3 43 10K TP37 YUV4/PIO4_4 44 TP38 YUV5/PIO4_5 45 TP39 YUV6/PIO4_6 46 TP40 YUV7/PIO4_7
PARA_DATA0/PIO3_0 PARA_DATA1/PIO3_1 PARA_DATA2/PIO3_2 PARA_DATA3/CAP0/PIO3_3 PARA_DATA4/CAP1/PIO3_4 PARA_DATA5/CAP2/PIO3_5 PARA_DATA6/PIO3_6 PARA_DATA7/PIO3_7
16 17 18 19 20 21 22
TP12
#FERESET
SMIDATA8 SMIDATA9 SMIDATA10 SMIDATA11 SMIDATA12 SMIDATA13 SMIDATA14 SMIDATA15
ADR[0..20]
CE1 CE2 CE3 OE
124 RESET TCK 113 TCK TDI 112 56R 111 TDI TMS 110 TDO #TRST 109 TMS TRST 205 PARA_REQ/PIO2_1 201 PARA_SYNC/PIO1_5 206 PARA_STR/PIO2_2 196 PARA_DVALID/PIO1_2
TP7 TP8
#SENSE #PUSH
#SENSE #PUSH
SMIADR0 SMIADR1 SMIADR2 SMIADR3 SMIADR4 SMIADR5 SMIADR6 SMIADR7 SMIADR8 SMIADR9 SMIADR10 SMIADR11 SMIADR12 SMIADR13
TP6
FPIR
FPIR
69 68 67 66 58 59 60 61 62 63 70 71 72 73
MD8 92 MD9 93 MD10 97 MD11 98 MD12 99 MD13100 MD14101 MD15102
75R
HEADER2X10 SHROUDED
R41
75R
2 4 6 8 10 12 14 16 18 20
MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13
49 VSS_PCM 5 VSS 15 VSS 38 VSS 50 VSS 65 VSS 83 VSS 96 VSS 108 VSS 121 VSS 137 VSS 150 VSS 160 VSS 172 VSS 185 VSS 199 VSS
R19 R21 R23 R24 R26 R28 R29
ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 ADR8 ADR9 ADR10 ADR11 ADR12 ADR13 ADR14 ADR15 ADR16 ADR17 ADR18 ADR19 ADR20
95 SMICLKOUT 82 SMICLKIN
24 VSS_RGB 31 VSS_YCC 123 VSS_PLL
0R0
36 I_REF DAC YCC
R16
SMICS0 SMICS1 SMIRAS SMICAS SMIWE SMIDQML SMIDQMU
29 I_REF DAC RGB 35 V_REF DAC YCC
SMICLK
74 75 76 77 78 79 80
PIO2_7 28 V_REF DAC RGB
0R0 0R0 0R0 0R0 0R0
3
0R0
R6 R8 R9 R11 R13
202 PIO1_6 203 PIO1_7
SMICLK
R4
#SMIRAS #SMICAS #SMIWE SMIDQML SMIDQMU
189 PIO0_3 190 PIO0_4 191 PIO0_5 192 PIO0_6 193 PIO0_7
#SMIRAS #SMICAS #SMIWE SMIDQML SMIDQMU
#SMICS0
186 PIO0_0
#SMICS0
VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3
4
U2
VDD_PLL 122 VDD_PCM 48 VDD_RGB 23 VDD_YCC 30 ADR1 161 ADR2 162 ADR3 163 ADR4 164 ADR5 165 ADR6 166 ADR7 167 ADR8 168 ADR9 169 ADR10 170 ADR11 173 ADR12 174 ADR13 175 ADR14 176 ADR15 177 ADR16 178 ADR17 179 ADR18 180 ADR19 181 ADR20 182 ADR21 183 DATA0 141 DATA1 142 DATA2 143 DATA3 144 DATA4 145 DATA5 146 DATA6 147 DATA7 148
TC4S81F R3 NS
+2V5-PLL
+2V5
14 37 64 94 119 149 171 198
VCC3
VDD2_5 VDD2_5 VDD2_5 VDD2_5 VDD2_5 VDD2_5 VDD2_5 VDD2_5
#JTAG_RESET U1 1 4 2
POWERON
E
ADR[0..20] DATA[0..15]
+2V5-PCM
4 47 81 107 136 159 184
MD[0..15]
D
+2V5-DENC
MD[0..15]
204 PIO2_0 1 PIO2_5
MA[0..13]
Date:
B
C
D
Document Number
Rev
1.1
101559 Tuesday, December 26, 2000
Sheet
E
2
of
16
A
B
C
D
E
Firmware Flash ROM 4
4 DATA[0..15] ADR[0..20]
DATA[0..15] ADR[0..20]
U3 A0 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 DQ5 A5 DQ6 A6 DQ7 A7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 A12 DQ12 A13 DQ13 A14 DQ14 A15 A16 DQ15/A-1 A17 A18/NC BYTE A19/NC VPP 26 CE #WP 28 OE RP 11 WE RB FLASH_1024KX16 or FLASH_512x16 100ns TSOP48
ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 ADR8 ADR9 ADR10 ADR11 ADR12 ADR13 ADR14 ADR15 ADR16 ADR17 ADR18 ADR19 ADR20
3
#CE3 #OE #WE
25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9
27 VSS 46 VSS
#CE3 #OE #WE
VCC 37
VCC-FLASH
2
29 31 33 35 38 40 42 44
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7
30 32 34 36 39 41 43 45
DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15
3
R66
47 13 14 12 15
0R0 R67 #RESET
INSTALL ZERO OHM RESISTORS FOR INTEL AND MICRON FLASH SUPPORT. DO NOT INSTALL FOR OTHER VENDORS.
0R0 R68 NS-0R0
2
ZERO OHM RESISTOR REQUIRED FOR SOME 16MB DEVICES A19 ON PIN 15
#RESET
1
1 Title
Production - FLASH ROM Memory Size
A4 Ravisent Proprietary Information
A
Date:
B
C
D
Document Number
Rev
1.1
101599 Tuesday, December 26, 2000
Sheet
3
E
of
16
A
B
C
D
E
Dedicated System Memory (Optional) DATA[0..15] ADR[0..20]
DATA[0..15] ADR[0..20] U20/1
4
3
ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 ADR8 ADR9 ADR10 ADR11 ADR12 ADR15 ADR16 #SDRAS #SDCAS #SDWE #SDCS0 DQML DQMH RAMCLK
#SDRAS #SDCAS #SDWE #SDCS0 DQML DQMH RAMCLK
R69 75R
R70 75R
R71 75R
R72 75R
R73 75R
R74 75R
R75 75R
C4 47pF
C5 47pF
C6 47pF
C7 47pF
C8 47pF
C9 47pF
C10 47pF
2
23 24 25 26 29 30 31 32 33 34 22 35 21 20
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12_BA1 A13_BA0
18 17 16 19 15 39
RAS CAS WE CS LDQM UDQM
D0 D1 D2 D3 D4 D5 D6 D7
2 4 5 7 8 10 11 13
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7
D8 D9 D10 D11 D12 D13 D14 D15
42 44 45 47 48 50 51 53
DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15
4
3
38 CLK VCC3 37 CKE SDRAM_4MX16 TSOP(II)54 125MHz 3.3V U20/2 ADR1 21 DATA0 D0 2 ADR2 22 A0 3 DATA1 A1 D1 ADR3 23 DATA2 D2 5 ADR4 24 A2 DATA3 D3 6 DATA4 ADR5 27 A3 D4 8 ADR6 28 A4 DATA5 9 A5 D5 ADR7 29 DATA6 D6 11 DATA7 ADR8 30 A6 D7 12 ADR9 31 A7 A8 ADR10 32 DATA8 D8 39 DATA9 ADR11 20 A9 D9 40 ADR12 19 A10 DATA10 2 42 A11 D10 43 DATA11 D11 DATA12 17 RAS D12 45 DATA13 16 CAS D13 46 15 WE 48 DATA14 D14 DATA15 18 CS D15 49 14 LDQM 36 UDQM Overlap footprints of /1 and /2 parts 35 CLK 34 VCC3 CKE NS-SDRAM_1MX16 125MHz 3.3V TSOP(II)50_400
1
1 Title
Production - System DRAM Memory
Note: - place RC termination close to U5 - route SDCLK as short as possible - 125MHz SDRAMs are required
Ravisent Proprietary Information
A
B
C
Size
A4 Date:
D
Document Number
Rev
1.1
101599 Tuesday, December 26, 2000
Sheet
4
E
of
16
A
B
C
D
E
Decoder / SMI Memory 4
4 MD[0..15] MA[0..13]
MD[0..15] MA[0..13] U4 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13
3 #SMIRAS #SMICAS #SMIWE #SMICS0 SMIDQML SMIDQMU SMICLK
#SMIRAS #SMICAS #SMIWE #SMICS0 SMIDQML SMIDQMU SMICLK VCC3 R76 75R
2
C11 47pF
R77 75R
C12 47pF
R78 75R
C13 47pF
R79 75R
C14 47pF
R80 75R
R81 75R
C15 47pF
C16 47pF
R82 75R
C17 47pF
23 24 25 26 29 30 31 32 33 34 22 35 21 20
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12_BA1 A13_BA0
18 17 16 19 15 39
RAS CAS WE CS LDQM UDQM
D0 D1 D2 D3 D4 D5 D6 D7
2 4 5 7 8 10 11 13
MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7
D8 D9 D10 D11 D12 D13 D14 D15
42 44 45 47 48 50 51 53
MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15
3
38 CLK 37 CKE SDRAM_4MX16 125MHz 3.3V TSOP(II)54
ROUTE SMICLK IN A LOOP FROM 5508 PIN 95 TO SDRAM THEN BACK TO 5508 PIN 82
2
1
1 Title
Production - Decoder SDRAM Memory
Note: - place RC termination close to U6 - route SDCLK as short as possible - 125MHz SDRAMs are required
Ravisent Proprietary Information
A
B
C
Size
A4 Date:
D
Document Number
Rev
1.1
101599 Tuesday, December 26, 2000
Sheet
5
E
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16
A
B
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D
E
4
4
ADR[0..20]
ADR[0..20] #FERESET
3
#FERESET #CE1 R/#W
#CE1 R/#W
#ATAPI_WR #ATAPI_RD
#ATAPI_WR #ATAPI_RD
#FERESET SCL SDA OPEN CLOSE #SENSE #PUSH
SCL SDA OPEN CLOSE #SENSE #PUSH
2
ATAPI ADR[0..20]
DATA[0..15]
DATA[0..15]
DATA[0..15]
#FERESET
3
#CE1 R/#W #ATAPI_WR #ATAPI_RD 07-ATAPI
FEINT
TVM502 #FERESET
DATA BCLK FLAG SYNC
SCL SDA OPEN CLOSE #SENSE #PUSH 08-TVM502
FEINT
FEINT
FEINT
DATA BCLK FLAG SYNC
DATA BCLK FLAG SYNC
FEINT
2
1
1 Title
Production - Front End Options Size
A4
Ravisent Proprietary Information
Date:
A
B
C
D
Document Number
Rev
101599 Tuesday, December 26, 2000
1.1 Sheet
6
E
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A
B VCC
VCC
R83 10K
4
C
D
E
VCC
R84 1K
R85 10K
4
DATA[0..15]
DATA[0..15]
ADR[0..20]
ADR[0..20]
HEADER2X20 SHROUDED HA0 35 RESET HA1 33 CS0 HA2 36 CS1 HD0 17 IOW HD1 15 IOR HD2 13 HD3 11 DMARQ HD4 9 DMACK HD5 7 HD6 5 IOCHRDY HD7 3 HIO16 PDIAG HD8 4 HD9 6 INTRQ HD10 8 HD11 10 HD12 12 DASP HD13 14 CSEL HD14 16 HD15 18
#FERESET
#FERESET
ADR19 R88 ADR20 R90
1 220R 37 220R 38
#ATAPI_WR #ATAPI_RD
#ATAPI_WR #ATAPI_RD
23 25 TP13
21 29 27 32 34
TP14
3 FEINT
FEINT
31 39 R91 10K
28 2 19 22 24
2
GND GND GND GND
20 KEY
J2
R86 R87 R89
220R ADR16 220R ADR17 220R ADR18
VCC3
DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7
2 3 4 5 6 7 8 9
DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
B1 B2 B3 B4 B5 B6 B7 B8
18 17 16 15 14 13 12 11
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7
3
1 19 DIR OE 20 VCC 74LC245 2 3 4 5 6 7 8 9
GND 40 GND 30 GND 26
U6 A1 A2 A3 A4 A5 A6 A7 A8
B1 B2 B3 B4 B5 B6 B7 B8
18 17 16 15 14 13 12 11
DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15
1 19 DIR OE 20 VCC
R/#W #CE1
R/#W #CE1
U5 A1 A2 A3 A4 A5 A6 A7 A8
2
74LC245
1
1 Title
Production - ATAPI Interface Size
A4 Ravisent Proprietary Information
A
Date:
B
C
D
Document Number
Rev
1.1
101599 Tuesday, December 26, 2000
Sheet
7
E
of
16
A
B
4
VCC-S
C
D
E
1 2
22uH C19 .1uF
4
J3
L1
C20 .1uF
L2
C18 .1uF
C21 47uF
LOCKHEADER2 U7
22uH +8V
VCC3-S
VCC-S
8 VCC1 7 VCC2
J4
TRAY MOTOR NS R333 0R0 R334
2 1 4 3 6 5 8 7 10 9 PICOFLEX10
R92 15R 1/4W
2 OUT1 1 GND
3 C24 100uF 16V
D1 6.8V
#FERESET FEINT SCL SDA
2 R102 R103
0R0 NS
TVM DRIVE TRAY MOTOR POWER
R97 0R0
R100 10K0 1%
R101 5K6 5 6 R104 10K
R93 1K
8
7V
FFC19
TVM502B --> 8V
3 2
R98 100K
FFC12 CAN BE STUFFED IN SAME FOOTPRINT
TRAY MOTOR
C25 .1uF
R95 12K1 1%
+
U8B LM393
+
7
1
R96
0R0
U8A LM393
R99
0R0
R94 1K #SENSE
4
#FERESET FEINT SCL SDA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
8
SYNC FLAG DATA BCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
#PUSH
2
in1, in2, out1, out2 pin5, pin6, pin2, pin10 0, 0, 0, 0 (idle) 0, 1, 0, 1 (open) 1, 0, 1, 0 (close) 1, 1, 0, 0 (brake) * Tray motor must be in idle state for push sense to operate
4
SYNC FLAG DATA BCLK
TVM502A --> 12V
VCC
VCC-S VCC3-S J10
#FERESET FEINT SCL SDA
3
LB1641
+12V
SYNC FLAG DATA BCLK
6 IN2 5 IN1 4 V2 3 P1
C23 .1uF
+8V +12V
CLOSE
CLOSE
+8V
FFC10 CAN BE STUFFED IN SAME FOOTPRINT
3
OPEN
OPEN
C22 .1uF
1
+12V
10 OUT2 9 P2
C26 .1uF
3
1
1
SOT23 6V8 1
2
Title
Production - TVM502 Drive Interface Size
A3 Ravisent Proprietary Information
A
Date:
B
C
D
Document Number
Rev
1.1
101599 Tuesday, December 26, 2000
Sheet
E
8
of
16
A
B
C
D
E
Stuffed, if no ext. PLL is used VCC OSC1 1 NC
4
4 VCC 8
4 GND CLK 5 27MHz Optional for better SPDIF support
Y1 27MHz
6 XT1 2 MODE 9 NC
33pF
4 7
R115 0R0
R106
MCK0 10 MCK0 11
PIXCLK
NS
U10-1 0R0 SCKO1 12 SCKO2 14 SCKO3 17 SCKO4 13 PLL1700
R108 R110
NS NS
384fs
R111 R112
NS NS
7 7W34 U10-3
768fs
R113
NS
3
256fs
1
3 R109 NS
VCC3
AUDCLK
AUDCLK
R346 NS PCMCLK
5 7W34
PCMCLK
R114 0R0
U11
R116
Q 5 Q 3
2 D 1 CLK
NS R118 NS Stuffed, if ext. PIXCLK source
R117 NS
2
6
2
PIXCLK
R107
PR 7
33pF C28
R346 CAN BE INSTALLED INSTEAD OF U10 FOR APPLICATIONS WITH NO BACK PANEL
R105 33R
CL
C27
15 GND
#BPRESET ML MD MC
U9 #BPRESET 18 RESET ML 1 ML/SR0 MD 19 MD/FS0 MC 20 MC/FS1 5 XT2
GND GNDPLL
3
VCC3
VDD 3 VDDPLL 8 VDD3 16
VCC
NS-TC7W74FU Stuffing options for back panel DACs
1
1 Title
Production - System and Audio Clocks Size
A4 Ravisent Proprietary Information
A
Date:
B
C
D
Document Number
Rev
1.1
101599 Tuesday, December 26, 2000
Sheet
9
E
of
16
A
B
C
D
E
4
4
VCC U12 1 C1+
3
C29 .1uF
C30 .1uF 3 C14 C2+
GND 15 V+ 2
C31 .1uF
RXD CTS
2
TXD RXD CTS RTS GND
: : : : :
3
2 3 7 8 5
C32 .1uF
5 C2V11 TIN1 TOUT1 10 TIN2 TOUT2 12 ROUT1 RIN1 9 ROUT2 RIN2 MAX232
TXD RTS
DB9 PINOUT (FEMALE)
VCC 16
R119 R120 R121 R122
6 14 7
TXD_B RTS_B
13 8
RXD_B CTS_B
J7 1 2 3 4 5 6 7 8 9 10 HEADER2X5 SHROUDED
2
NS NS NS NS
1
1 Title
Production - RS232 Transceiver Size
A4 Date:
A
B
C
D
Document Number
Rev
1.1
101599 Tuesday, December 26, 2000
Sheet
10
E
of
16
A
B
C
D
E
BACK PANEL PIO FUNCTIONS SIGNAL
HIGH/LOW
BPPIO0 -- 4:3/16:9
VCC
BPPIO1 -- POWER/STANDBY
4
BPPIO2 --
#BPRESET SPDIF_OUT
BPPIO3 --
DAC_DATA DAC_PCMCLK DAC_SCLK DAC_LRCLK DAC_DATA0 DAC_DATA1 DAC_DATA2 R123
BPPIO0 BPPIO1 BPPIO2 BPPIO3 SCL SDA
DAC_DATA0
0R0 R124
3
DAC_DATA
J11
#BPRESET
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FFC20
SPDIF_OUT DAC_DATA DAC_PCMCLK DAC_SCLK DAC_LRCLK DAC_DATA0 DAC_DATA1 DAC_DATA2 BPPIO0 BPPIO1 BPPIO2 BPPIO3 SCL SDA
NS
R127 75R
2
VA 7 AGND
DAC_PCMCLK
1 SDATA 2 SCLK 3 LRCLK 4 MCLK
3
AOUTL 8
C33
R125
10uF ELCO 16V
562R R126 1% 100K 1%
TV/DVD 1 SPDIF 2 OUTPUT LOCKHEADER2
C34
J13
1500pF LEFT
TV/DVD 1 2 AUDIO 3 OUTPUT LOCKHEADER3
RIGHT AOUTR 5
CS4335
C35
R128
10uF ELCO 16V
562R R129 1% 100K 1%
6
DAC_SCLK DAC_LRCLK
SDATA
PLAYER REAR PANEL CONNECTOR
J12
VCC-PCM
U13
4
C37 47pF
2
C36 1500pF
1
1 Title Size
A4
Ravisent Proprietary Information
Date:
A
B
C
D
Production - Audio Output Document Number
Rev
101599 Tuesday, December 26, 2000
1.1 Sheet
11
E
of
16
A
B
C
D VCC3
+12V
E
+8VA -8VA +5VA
1 2 3 4 5 6 7 8 PLAYER 9 10 REAR 11 PANEL 12 13 14 15 16 17 18 19 20 FFC20
E VIDEOFILTER RED
RED
GREEN
GREEN
BLUE
BLUE
CHROMA
CHROMA
LUMA
LUMA
LUMA
CVBS
CVBS
RED GREEN BLUE CHROMA
D
RED_OUT
RED_OUT
GREEN_OUT
GREEN_OUT
BLUE_OUT
BLUE_OUT
CHROMA_OUT
CHROMA_OUT LUMA_OUT
LUMA_OUT
CVBS CVBS_OUT 13-VIDEO AMP
CVBS_OUT
J14
E
D
J15 1 2 3 4 5 DVD/TV 6 OUTPUT 7 8 9 10 LOCKHEADER10
+12V
R130 10K
C
R131 R132
BC848BL Q2 1
STANDBY 10K
2 Q1 BC858BL 3 R336
1 3
10K
C
2
R133
100R
10K 3
B 3 SOT23 848 1
B
SOT23 858 1
2
2
A
A
Title
Production - Video Outputs Size
A4
Ravisent Proprietary Information
Date:
A
B
C
D
Document Number
Rev
1.1
101599 Tuesday, December 26, 2000
Sheet
12
E
of
16
A
B NS
C
D
R134
NS
R135
VCC-DENC C38 3300pF
4
R138 825R 1%
TP15 C42
VCC-DENC
C39
C40
.1uF
3300pF
R140 12R1 1%
R143 2K21 1%
R146 75R0 1%
NS
R139 825R 1%
TP16
2 Q3 2N2907 1 3
RED 100uF 16V R142 200R 1%
R136 8R2
E
CHROMA
L3
100uF 16V R144 200R 1%
RED_OUT
2.7uH C44
C45
390pF
390pF
1
2 Q4 2N2907 3
R145 2K21 1%
R148
C41 .1uF
4
R141 12R1 1%
C43
TP17
R137 8R2
R147 75R0 1%
NS
TP18 L4 CHROMA_OUT
2.7uH C46
C47
390pF
390pF
R149
VCC-DENC
VCC-DENC
3
3 C48 3300pF R152 825R 1%
TP19 C52 100uF 16V R156 200R 1%
C49
C50
.1uF
3300pF
R154 12R1 1% 2 Q5 2N2907 1 3
GREEN
R150 8R2
R157 2K21 1%
NS
R160 75R0 1%
R153 825R 1%
TP20
LUMA
L5
100uF 16V R158 200R 1%
GREEN_OUT
2.7uH C54
C55
390pF
390pF
1
2 Q6 2N2907 3
R159 2K21 1%
R162
C51 .1uF
R155 12R1 1%
C53
TP21
R151 8R2
NS
R161 75R0 1%
TP22 L6 LUMA_OUT
2.7uH C56
C57
390pF
390pF
R163
2
2 VCC-DENC C58 3300pF R166 825R 1%
TP23 C62 BLUE 100uF 16V R170 200R 1%
R164 8R2
VCC-DENC
C59
C60
.1uF
3300pF
R168 12R1 1% 2 Q7 2N2907 1 3
R171 2K21 1%
R174 75R0 1%
R167 825R 1%
TP24 C63
TP25 CVBS
L7
100uF 16V R172 200R 1%
BLUE_OUT
2.7uH C64
C65
390pF
390pF
R165 8R2
C61
3
.1uF
SOT23 2907
R169 12R1 1% 2 Q8 2N2907 1 3
R173 2K21 1%
R175 75R0 1%
1
2
TP26 L8 CVBS_OUT
2.7uH C66
C67
390pF
390pF
1
1
Title
Production - Video Buffers / Filters Size
A3 Ravisent Proprietary Information
A
Date:
B
C
D
Document Number
Rev
1.1
101599 Tuesday, December 26, 2000
Sheet
E
13
of
16
A
B
C
D
E
4
4
IR1 TSOP1840
VCC R337 100R
1 2 3
OUT GND VCC
VCC
R338 4K7
3
FPIR FPDATA FPCLK FPSTB
R339 4K7
R340 4K7
R341 4K7 C152 10uF 16V ELCO
FPIR FPDATA FPCLK FPSTB
R342 R344 R345
0R0 0R0 0R0
R343
3
0R0
C153 NS
VCC C154 NS
J16 1 2 3 4 5 6 LOCKHEADER6
C155 NS-47pF
2
2
VCC SCL SDA
SCL SDA
J17 1 I2C HEADER 2 3 4 LOCKHEADER4
1
1 Title
Production - Front Panel Size
A4 Date:
A
B
C
D
Document Number
Rev
1.1
101599 Tuesday, December 26, 2000
Sheet
14
E
of
16
A
B
C
D
E
4
4 U14 6 SCL A0 1 5 SDA A1 2 A2 3 WC 7
SCL SDA
SCL SDA
24C02 3-5V VCC
R335 1K
VCC
R178 NS-0R0
U15 SDA 5 VCC 8 SCL 6 SDA SCL RESET 3 1 NC/XIN WP/VBACK 7 4 2 NC/XOUT GND NS-X4043
3
VCC
3
R179 0R0
VCC
C70 NS-.1uF U16 3 MR VCC 4 1 GND RST 2 NS-TC1270
2
2
VCC C71
1
2
.1uF
R180 10K
PUSHBUTTON SWITCH
U17
4
S1 1
3
2
4
1 MR RESET 8 2 VCC RESET 7 3 GND NC 6
JP7 JUMPER2
3
4 PFI
PINS 1 AND 2 ARE CONNECTED INTERNALLY PINS 3 AND 4 ARE CONNECTED INTERNALLY
POWERON R181 10K
PFO 5
ADM707
VCC U20 2 VCC 1 3 GND RST
1
DS1812
1 3 SOT23 DS1812
Title
1
Size
Production - Serial EEPROM and Reset
2
A3
Ravisent Proprietary Information
Date:
A
B
C
D
Document Number
Rev
1.1
101599 Tuesday, December 26, 2000
Sheet
E
15
of
16
+3.3V
3
GND
4
GND
5
3
4
LINEAR TECH DESIGNED OUT - USE ST OR NATIONAL
3 VI
SOT-223 LD1117
6
C72 .1uF
R183
0R0
0R0
6 7
1
+8VA
8
C78
C79
C80
100uF .1uF 16V
C81
C82
100uF .1uF 16V
C83
C84
C85
C86
100uF .1uF 16V
100uF .1uF 16V
C75 .1uF
3
+5VA
+2V5
+2V5 C89
.1uF C96
.1uF C97
.1uF C107 .1uF C115
.1uF C116
.1uF C118
.1uF C121
.1uF C122 119
136 .1uF C126
10uF ELCO 16V
.1uF C119
.1uF C123
.1uF
.1uF C131
10uF ELCO 16V
GND PROBES TP27 TP28 TP29 TP30
MOUNTING HOLES MH1 MH2 MH3 MH4 MH5 MH6
22uH
C137 22uF ELCO 16V
C136 .1uF
L11
+2V5-PCM
22uH
C144 22uF ELCO 16V
C143 .1uF
22uH
C147 .1uF
C148 22uF ELCO 16V
2 3
10uF ELCO 16V
VCC3
VCC3
0R0
NS-.1uF C129 VDD
VCC3 C139
14 U2 I2C EEPROM VCC
C140
U12 TC7W74F
10uF ELCO 16V
VCC3 C150
7 .1uF C145
+5VA VCC-PCM
L12
C141
.1uF
U39 EEPROM/POR
VCC
16
.1uF
VCC C149
VCC
8
.1uF
U2 CS4335
U13 MAX232
U11 TC7W34F
VCC
5
.1uF
L13
2
VDD3
R348
22uH +5VA L10 NS-22uH
GND
VSS
GNDA
VSSA
VCC-DENC
NS-22uH
C142
C156 NS-10uF ELCO 16V
0R0
.1uF C146
Ravisent Proprietary Information 10uF ELCO 16V
C151
Title
Production - Power Supply and Decoupling
8
8
Size
.1uF
A3 Date:
B
VCC3
NS-10uF ELCO 16V
OSC1 Oscillator
C138
C106 .1uF
16
VCC
U3 TC4S81F
100uF 16V
R188 C125
10uF ELCO 16V
.1uF
A
C105
78M05 DPAK
.1uF C135
10uF ELCO 16V
+2V5-DENC
L14
0R0
49 .1uF C134
+2V5-PLL
R187
.1uF C132
49 .1uF C133
1
C104 .1uF
NS-10uF ELCO 16V
43
.1uF C130
L9
.1uF C120
.1uF C128
43
184
32 VCC3
.1uF C124
.1uF C127
159
10uF ELCO 16V
9
9
NS-.1uF C113
ANALOG 5V VO 3
C114
3
3
U21/2 1 VI
DPAK 78M05
8
.1uF
C112
27
.1uF C117
94
107
C103 37
3
2
NS-.1uF C102
.1uF
.1uF
NS-7805 TO-220
C95 3
37
VO 3
1 2 3
VCC
C94
.1uF C101
.1uF C111
27
VCC-FLASH
20
14 .1uF C110
198
64
81
1
1 VI TO-220 7805
U10 PLL
R186 NS
.1uF C100
14 .1uF C109
VCC C93
20
1 .1uF C99
U4 Flash ROM
VCC3 C92
1 .1uF C98
.1uF C108
U7 & U8 74LVT16245
VCC3 C91
171
37
47
VCC3 C90
149
14
4
2
U21/1
JUMPER2
C88
100uF .1uF 16V
+12V
FPPWD
VCC3
C77
ALTERNATE PACKAGE FOR HIGH CURRENT
100uF .1uF 16V
U6 SDRAM-SMI
C76 78M08 DPAK
4
+8V
C87
JP8
U5 SDRAM-EMI
.1uF
3
VCC
U1 STi5508/80
C74
10uF 16V
U19 TMM DRIVE SUPPLY 1 VI VO 3
2
-8VA
+2V5 C73
GND
R182
DPAK 78M08
FPPWD
TAB 4
1 2 3 +12V
+12V
ST-LD1117 SOT223 VO 2
2
2
+8VA
U18
GND
+3.3V
-8VA
E
VCC
GND
1
+12V
D
2
+5V
VCC3
C
NS-NDS8934 VCC-S Q9-1 2 7 NS-NDS8934 VCC3-S Q9-2 1 8 4 5
GND
VCC
J8
4
B
1
A
C
D
Document Number
Rev
1.1
101599 Tuesday, December 26, 2000
Sheet
E
16
of
16
1
